BM6411 CIRCUITS AND IC’S LABORATORY L T P C

0 0 3 2

LIST OF EXPERIMENTS:
1. Study of logic gates, Half adder and Full adder
2. Encoder and BCD to 7 segment decoder
3. Multiplexer and demultiplexer using digital ICs
4. Universal shift register using flip flops
5. Design of mod-N counter
6. Inverting, non-inverting amplifier and comparator
7. Integrator and Differentiator
8. Active filter – first order and second order LPF and HPF
9. Current to Voltage convertor and Voltage to Current Convertor
10. Comparator, Peak detector and Average detector
11. Instrumentation amplifier using IC741
12. Wein bridge oscillator
13. Multivibrator using IC555 Timer
14. Timer
15. Phase Lock Loop
16 A/D and D/A convertor
 List of Experiment

S. No. ExpNo. Experiment Name

Cycle - I
1 1a Study of logic gates
2 1b Half adder and Full adder
3 2 Encoder and BCD to 7 segment decoder
4 3 Multiplexer and demultiplexer using digital ICs
5 4 Universal shift register using flip flops
6 5 Design of mod-N counter
7 6. a Inverting amplifier
8 6. b Non-inverting amplifier
9 6. c Comparator
10 7. a Differentiator

Cycle - II
11 7. b Integrator
12 8 Active filter – first order and second order LPF and HPF
13 9 Current to Voltage convertor and Voltage to Current Convertor
14 10 Peak detector and Average detector
15 11 Instrumentation amplifier using IC741
16 12 Wein bridge oscillator
17 13. a MonostableMultivibrator using IC555 Timer
18 13. b AstableMultivibrator using IC555 Timer
19 14 Phase Lock Loop
20 15 A/D and D/A convertor
Exp. No.: 1 STUDY OF LOGIC GATES, HALF ADDER AND FULL ADDER

1.a. STUDY OF LOGIC GATES

AIM:
To study and verify the truth table of Logic gates

APPARATUS REQUIRED:

S No. Name of the Component/Equipment Values/Specifications Quantity

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. Digital Trainer Kit - 1

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any
one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the
inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs are
high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:
SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:

PROCEDURE:
1. Verify the gates
2. Connections were given as per circuit diagram.
3. Logical inputs were given as per truth table
4. Observe the logical output and verify with the truth tables

RESULT:
The different logic gates were studied and their truth table was verified using 74XX
IC’s.
 1. bHALF ADDER AND FULL ADDER

AIM:
To design and construct half adder, full adder and verify the truth table using
XOR and basic logic gates.

APPARATUS REQUIRED:

S No. Name of the Component/Equipment Values/Specifications Quantity

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. Bread Board - 1
4. LED - 4

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR Gate
the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.

LOGIC DIAGRAM:

HALF ADDER
TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:
FULL ADDER:
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

PROCEDURE:
5. Verify the gates
6. Connections were given as per circuit diagram.
7. Logical inputs were given as per truth table
8. Observe the logical output and verify with the truth tables

RESULT:
The half and full Adder circuits were constructed and their truth table was verified.
Exp No.: 2 DECODER AND ENCODER

AIM:
To realize the Encoder and Decoder circuit using logic gates and to verify the truth
table.

APPARATUS REQUIRED:

Sl.No Component Type Quantity

1 Trainer Kit - 1
2 OR Gate IC 7432 3
3 AND gate(3 input) IC7411 2
4 NOT gate IC 7404 1
5 Connecting wires - Required

ENCODER:
THEORY:
An encoder has 2n (or fewer) input lines and ‘n’ output lines. The output lines generate
the binary code corresponding to the input value. In encoders, it is assumed that only one
input has a value of 1 at any given time. The encoders are specified as m-to-n encoders where
m ≤ 2n .

TRUTH TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM:

DECODER :
THEORY:

A decoder is a combinational circuit that converts binary information from ‘n’ input
lines to a maximum of 2n unique output lines. It performs the reverse operation of the
encoder. If the n-bit decoded information has unused or don’t-care combinations, the decoder
output will have fewer than 2n outputs. The decoders are represented as n-to-m line decoders,
where m ≤ 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables.
The name decoder is also used in conjunction with some code converters such as BCD-to-
seven-segment decoders. Most, if not all, IC decoders include one or more enable inputs to
control the circuit operation. A decoder with an enable input can function as a de-multiplexer.

TRUTH TABLE:

INPUTS OUTPUTS
DIN X Y D0 D1 D2 D3
1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1
LOGIC DIAGRAM:

PROCEDURE:

1. The Encoder and Decoder circuit is designed and the Boolean function is found out.
2. The Low level input is Grounded and the HIGH level input is connected to the +5V
supply.
3. Connections are made as per the circuit given.
4. Observe the output for various combinations of inputs.
5. Thus the truth table is verified.

RESULT:

Thus the Encoder and Decoder circuit was designed using 74XX IC’s and the output
was verified.

Viva:

1. Say some application of decoder.

2. Say some application of encoder.
Exp No.:3 MULTIPLEXER AND DEMULTIPLEXER

AIM:
To construct and verify the truth table of multiplexer and demultiplexer circuits

APPARATUS REQUIRED:
Sl.No Component Type Quantity
1 Trainer Kit - 1
2 OR Gate IC 7432 3
3 AND gate(3 input) IC7411 2
4 NOT gate IC 7404 1
5 Connecting wires - Required

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and n selection lines whose bit combination determine which input is selected.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

CIRCUIT DIAGRAM:

MULTIPLEXER (4:1)
FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

TRUTH TABLE:

Inputs Control input Outputs (D0,D1,D2,D3)

D0 D1 D2 D3 X Y Z
1 0 0 0 0 0 D0
0 1 0 0 0 1 D1
0 0 1 0 1 0 D2
0 0 0 1 1 1 D3

DEMULTIPLEXER (1:4)
FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

TRUTH TABLE:

INPUTS CONTROL INPUTS OUTPUTS

D X Y D0 D1 D2 D3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0

PROCEDURE:

1. Give connections as per the circuit diagram

2. Inputs are given to the circuit making high ‘1’, i.e. +5 V or
+ Vcc supply to the 16th pin and for low ‘0’ i.e. GND to the 8th
pin of the gate IC
3. Verify the truth table for the multiplexer as given
4. Repeat the procedure steps for demulitplexer and verify its truth table

RESULT:
The multiplexer and demultiplexer circuits are constructed and their truth table was verified
Exp No.:4UNIVERSAL SHIFT REGISTER USING FLIP FLOPS
AIM:
To construct and verify the transition table of of 4-bit Universal shift register.

APPARATUS REQUIRED:
Sl.No Component Type Quantity
1 Trainer Kit - 1
D flip flop IC 7474 2
2 OR Gate IC 7432 3
3 AND gate(3 input) IC7411 6
4 NOT gate IC 7404 1
5 Connecting wires - Required

LOGIC DIAGRAM:
 Observation Table:

Inputs Outputs
_____ MODE SERIAL PARALLEL
Clk QA QB QC QD
Clear S1 S0 LEFT RIGHT A B C D
0 X X X X X X XXX 0 0 0 0
1 X X 0 X X X XXX 0 0 0 0
1 1 1 1 X X a b c d a b c d
1 0 1 1 X 1 X XXX 1 a b c
1 0 1 1 X 0 X XXX 0 a b c
1 1 0 1 1 X X XXX b c d 1
1 1 0 1 0 X X XXX b c d 0
1 0 0 X X X X XXX a b c d

Timing Diagram:

PROCEDURE:

1. Give connections as per the circuit diagram

2. Inputs are given to the circuit making high ‘1’, i.e. +5 V or
+ Vcc supply to the 16th pin and for low ‘0’ i.e. GND to the 8th
pin of the gate IC
3. Verify the truth table for the universal shift register as given

RESULT:
The universal shift register is constructed and the truth table and timing diagram was verified.
Exp N.:5 DESIGN OF MOD-N COUNTER
AIM:
To construct and verify the transition table of MOD-6 synchronous counter.

APPARATUS REQUIRED:
Sl.No Component Type Quantity
1 Trainer Kit - 1
D flip flop IC 7474 2
2 OR Gate IC 7432 3
3 AND gate(3 input) IC7411 6
4 NOT gate IC 7404 1
5 Connecting wires - Required

LOGIC DIAGRAM:

DESIGN PROCEDURE:
Using K Map

OBSERVATION TABLE:

Decimal No. QA QB QC
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 0 0 0

PROCEDURE:

1. Give connections as per the circuit diagram

2. Inputs are given to the circuit making high ‘1’, i.e. +5 V or
+ Vcc supply to the 16th pin and for low ‘0’ i.e. GND to the 8thpin of the gate IC
3. Verify the truth table for the MOD 6 counter as given

RESULT:
The MOD 6 is designed using D flip flop, implemented and the truth table was verified.
Exp No.6 INVERTING, NON-INVERTING AMPLIFIER AND COMPARATOR

6 a. INVERTING AMPLIFIER
AIM:
To design an Inverting Amplifier for the given specifications using Op-Amp IC
741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Connecting wires and probes As required

THEORY:
The input signal Vi is applied to the inverting input terminal through R1 and the
non-inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to
the inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor.
The output voltage is given as,
Vo = - ACL Vi
0
Here the negative sign indicates that the output voltage is 180 out of phase with
the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
PIN DIAGRAM:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN:

We know for an inverting Amplifier ACL = RF / R1

Assume R1 and find Rf
Hence Vo = - ACL Vi

OBSERVATIONS:
Output
S.No Input
Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

RESULT:

The design and testing of the inverting amplifier is done and the input and output waveforms
and frequency response were drawn
 6 b. NON - INVERTING AMPLIFIER

AIM:
To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the op-amp.
This circuit amplifies the signal without inverting the input signal. It is also called negative
feedback system since the output is feedback to the inverting input terminals. The differential
voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage
is given as,
Vo = ACL Vi

Here the output voltage is in phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the non - inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.

PIN DIAGRAM:
CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:
We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1)
Assume R1 and find Rf, Hence Vo = ACL Vi

OBSERVATIONS:
Output
S.No Input
Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

RESULT:
The design and testing of the Non-inverting amplifier is done and the input and
output waveforms and frequency response were drawn.

6 c. COMPARATOR

AIM:
To study and verify the comparator applications using IC741 operational amplifier.

APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. 1-V DC supply 1V 1
6. Bread Board 1
7. Resistors 1K 3
8. Connecting wires and probes As required

THEORY:
A comparator is a circuit which compares a signal voltage applied at one inputof
an op-amp with a known reference voltage at the other input . It is basically an openloop op-
amp with output ±Vsat as in the ideal transfer characteristics.It is clear that the change in the
output state takes place with an increment in input Vi of only 2mv. This is the uncertainty
region where output cannot be directly defined Thereare basically 2 types of comparators.
1. Non inverting comparator and.
2. In v e r t in g comp a r a to r .

The applications of comparator are zero crossing detector, window detector,

timemarker generator and phase meter.

CIRCUIT DIAGRAM:

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Select the sine wave of 5V peak to peak, 1K Hz frequency.
3. Apply the reference voltage 1V and trace the input and output wave forms.
4. Superimpose input and output waveforms and measure sine wave amplitude with reference
to Vref.
5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe
thewaveforms.
6. Replace sine wave input with 5V dc voltage and Vref = 0V.
7. Observe dc voltage at output using CRO.
8. Slowly increase Vref voltage and observe the change in saturation voltage.
9.To make a zero crossing detector, set Vref = 0V and observe the output waveforms.
OBSERVATIONS:

Voltage input Vref Observed square wave

Amplitude (PP) Time Period Amplitude Amplitude (PP) Time Period
1v
-1 v

MODEL GRAPH:

RESULT:
The operation of IC 741 Op-Amp as comparator is studied and the practical values found to
be equal to the theoretical value.

Expt. No.7 DIFFERENTIATOR AND INTEGRATOR

7. a. DIFFERENTIATOR

AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC
741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
 6. Resistors
7. Capacitors
8. Connecting wires and probes As required

THEORY:
The differentiator circuit performs the mathematical operation of differentiation;
that is, the output waveform is the derivative of the input waveform. The differentiator may
be constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a
capacitor C1 . The expression for the output voltage is given as,

Vo= - Rf C1 (dVi/dt)

Here the negative sign indicates that the output voltage is 1800out of phase with
the input signal. A resistor Rcomp= Rf is normally connected to the non-inverting input
terminal of the op-amp to compensate for the input bias current. A workable differentiator
can be designed by implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1< 1 µF, calculate the value of Rf.
2. Choose fb= 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.

The differentiator is most commonly used in waveshaping circuits to detect high

frequency components in an input signal and also as a rate–of–change detector in FM
modulators.

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN :
To design a differentiator circuit to differentiate an input signal that varies in
frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to
the differentiator , draw its output waveform.

Given fa= 1 KHz

We know the frequency at which the gain is 0 dB, fa= 1 / (2π Rf C1)
Let us assume C1 = 0.1 µF ; then
Rf = _________
Since fb = 20 fa,fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 = _________
Also since R1C1 = RfCf ; Cf = _________

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No Input Output

Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )
MODEL GRAPH:

RESULT:-
Thus the differentiator using op-amp is studied.
 7. b. INTEGRATOR

AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:
S.No Name of the Apparatus Value/ Specifications Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required

THEORY:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the
output voltage is given as,
Vo = - (1/RfC1 ) ∫Vi dt

Here the negative sign indicates that the output voltage is 1800out of phase with
the input signal. Normally between faandfb the circuit acts as an integrator. Generally, the
value of fa<fb . The input signal will be integrated properly if the Time period T of the signal
is larger than or equal to RfCf . That is,
T ≥ RfCf

The integrator is most commonly used in analog computers and ADC and signal-
wave shaping circuits.

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:
To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms
, Rf = 10 R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.

We know the frequency at which the gain is 0 dB, fb= 1 / (2π R1Cf)
Therefore fb = _____
Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2π RfCf)
We get , R1 = _______ and hence Rf = __________

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.

OBSERVATIONS:
S.No Input Output
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

MODEL GRAPH:

RESULT:-
Thus the integrator and differentiator using op-amp are studied.
Exp: 8ACTIVE FILTERS – FIRST ORDER& SECOND ORDER LPF AND HPF

AIM:
To study and design first order& Second order LPF and HPF using op-amp IC741
and to obtainfrequency response.
.
EQUIPMENTS AND COMPONENTS:

S.No Name of the Apparatus Value/ Specifications Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required

THEORY:

LOW PASS FILTER:

A frequency selective electric circuit that passes electric signals of specified band
of frequencies and attenuates the signals of frequencies outside the brand is called an electric
filter. The first order low pass filter consists of a single RC network connected to the non-
inverting input terminal of the operational amplifier. Resisters R1 and RF determine the gain
of the filter in the pass band. The low pass filter as maximum gain at f = 0Hz. The frequency
range from 0 to FH is called the pass band the frequency range f>fh is called the stop band.
The first order low pass butter worth filter uses an Rc network for filtering.
Theop-amp is used in the non inverting configuration, hence it does not load down the
RCnetwork. Resistor R1 and R2 determine the gain of the filter.
V0/Vin = Af/(1+ jf/f h)
Af = 1+ Rf /R1=passbandgainof filter
F=frequency of the input signal
Fh=1/2ΠRC =High cutt off frequency of filter
V0/Vin=Gain of the filter as a function of frequency
The gain magnitude and phase angle equations of the LPF the can be obtained by
converting V0/Vin into its equivalent polar form as follows|V0/Vin| = Af/(√1 +(f/f l2) Φ=- t
a n - 1 ( f / f h) Where Φis the phase angle in degrees. The operation of the LPF can be
verified.
From the gain magnitude equation.
CIRCUIT DIAGRAM:
1st order LPF:

2nd orderLPF:

HIGH PASS FILTER:

High pass filters are often formed simply by interchanging frequency.
Determining resistors and capacitors in LPFs that is ,a first order HPF is formed from a first
order LPF by interchanging components ‘R’ and ‘C’ figure. Shows a first order butter worth
HPF with a lower cut off frequency of ‘ Fl’. This is the frequency at which magnitude of the
gain is 0.707 times its pass band value. Obviously all frequencies, with the highest frequency
determinate by the closed loop band width of op-amp. For the first order HPF
the output voltage is
V0= [1+Rf /R1]j2ΠRCVin/(1-j2ΠfRC)
V0/Vin=Af [j(f/f l)/(1=j(f/f l)]
Where Af +Rf /R1pass band gain of the filter.
F =frequency of input signal.
Fl=1/2ΠRC = lower cutt off frequency
Since, HPFs are formed from LPFs simply by interchanging R’s and C’s
.Thedesign and frequency scaling procedures of the LPFsare also applicable to HPFs.
CIRCUIT DIAGRAM:
1st order HPF:

2nd order HPF:

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply sine wave of amplitude 2Vp-p to the non inverting input terminal.
3. Values the input signal frequency.
4. Note down the corresponding output voltage.
5 .Ca l cu l a t e ga in in db .
6 . Tab ul a t e t h e valu e s .
7. Plot a graph between frequency and gain.
8. Identify stop band and pass band from the graph.
CALCULATIONS
LPF:
Fh=1/2πRC
Choose c=0.01μf
Fh= 500Hz
R=?
Av=1+Rf/R1
With this
R1=10k
Rf=10k

OBSERVATIONS :(LPF 1st order)

Input Voltage Input Signal Output Gain

S.No
Frequency Voltage Vo/Vin 20log(Vo/Vin)
1. 10 Hz
2. 20 Hz
3. 30 Hz
4. 40 Hz
5 50 Hz
6 60 Hz
7 70 Hz
8 80 Hz
9 90 Hz
10 100 Hz
11 200 Hz
12 300Hz
13 400 Hz
14 500 Hz
15 600 Hz
16 700 Hz
17 800 Hz
18 900 Hz
19 1kHz
20 2 kHz
21 3 kHz
22 4 kHz
23 5 kHz
24 6 kHz
25 7 kHz
OBSERVATIONS :(LPF 2nd order)

Input Voltage Input Signal Output Gain

S.No
Frequency Voltage Vo/Vin 20log(Vo/Vin)
1. 10 Hz
2. 20 Hz
3. 30 Hz
4. 40 Hz
5 50 Hz
6 60 Hz
7 70 Hz
8 80 Hz
9 90 Hz
10 100 Hz
11 200 Hz
12 300Hz
13 400 Hz
14 500 Hz
15 600 Hz
16 700 Hz
17 800 Hz
18 900 Hz
19 1kHz
20 2 kHz
21 3 kHz
22 4 kHz
23 5 kHz
24 6 kHz
25 7 kHz

HPF:
Choose a standard value of Capacitor C say 0.01 μF
Then fL=1/2πRc
fL= 200Hz
R=?
A=1+Rf/R1
With this
R1=10k
Rf=10k
OBSERVATIONS :(HPF1st order)

Input Voltage Input Signal Output Gain

S.No
Frequency Voltage Vo/Vin 20log(Vo/Vin)
1. 100 Hz
2. 200 Hz
3. 300Hz
4. 400 Hz
5 500 Hz
6 600 Hz
7 700 Hz
8 800 Hz
9 900 Hz
10 1kHz
11 2 kHz
12 3 kHz
13 4 kHz
14 5 kHz
15 6 kHz
16 7 kHz
17 8 kHz
18 9 kHz
19 10 kHz
20 20 kHz
21 30 kHz
22 40 kHz
23 50 kHz
24 60 kHz
25 70 kHz

OBSERVATIONS :(HPF1st order)

Input Voltage Input Signal Output Gain

S.No
Frequency Voltage Vo/Vin 20log(Vo/Vin)
1. 100 Hz
2. 200 Hz
3. 300Hz
4. 400 Hz
5 500 Hz
6 600 Hz
7 700 Hz
8 800 Hz
9 900 Hz
 10 1kHz
11 2 kHz
12 3 kHz
13 4 kHz
14 5 kHz
15 6 kHz
16 7 kHz
17 8 kHz
18 9 kHz
19 10 kHz
20 20 kHz
21 30 kHz
22 40 kHz
23 50 kHz
24 60 kHz
25 70 kHz

MODEL GRAPH:
LPF:HPF:

RESULT:
HPF :The obtained gain Av =__________
The cutoff frequencyfor 1st order =__________
The cutoff frequency for 2nd order =__________

LPF:The obtained gain Av =__________

The cutoff frequency for 1st order=__________
The cutoff frequency for 2nd order =__________

The HPF and LPF filters are designed and obtained gain is found to be equal to
the theoretical value of gain .The frequency response of LPF and HPF is plotted using IC741
Op-Amp
Exp No: 9 CURRENT TO VOLTAGE CONVERTOR AND VOLTAGE TO
CURRENT CONVERTOR

AIM:
To design a current to voltage convertor and a voltage to current convertorcircuit
using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Value/ Specifications Quantity

1. Function Generator 3 MHz 1
2. Variable source 0 – 10 V 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board - 1
6. Resistors 1M, 100k, 1k Each 1
7. Multimeter - 1
8. Ammeter mA 1
9. Connecting wires and probes As required

THEORY:
CURRENT TO VOLTAGE CONVERTOR
An op amp can be used to produce a voltage proportional to a given current. Construct the
circuit in figure below.

CIRCUIT DIAGRAM (CURRENT TO VOLTAGE CONVERTOR):

Verify that Vout= - IinR2 for this circuit. (That is, do the following for several voltage settings
on the variable power supply: Measure the supply voltage and from this calculate Iin. Use the
formula to calculate a theoreticalVoutandcompare this to a measuredVout

VOLTAGE TO CURRENT CONVERTOR

The input voltage is applied to the non-inverting input terminal and the feedback voltage
across R drives the inverting input terminal. This circuit is also called a current series negative
feedback, amplifier because the feedback voltage across R depends on the output current IL
and is in series with the input difference voltage Vd.
IL = Iin = Vin ./ R

An op amp can be used to produce a current proportional to a given voltage. Construct the
circuit in figure below.

CIRCUIT DIAGRAM (VOLTAGE TO CURRENT CONVERTOR):

PROCEDURE:
1. Patch the connections as per the diagram
2. Measure the input Current Iin or voltage at Vin using digital multimeter.
3. Take the Output reading
4. Check the theoretical value with the experimental value.

OBSERVATIONS:

CURRENT TO VOLTAGE CONVERTOR

Output voltage (V)

S.No Input current (mA)
Practical Theoretical
1.
2.

CURRENT TO VOLTAGE CONVERTOR

Output current (mA)

S.No Input voltage (V)
Practical Theoretical
1.
2.

RESULT:
The design and testing of the voltage to current converter and current to voltage
converter using IC741 was done and the input and output reading has been tabulated.
Exp No.: 10PEAK DETECTOR AND AVERAGEDETECTOR

AIM:
To design a peak detector & an average detector circuit using op-amp

APPARATUS REQUIRED:

S.No Name of the Apparatus Value/ Specifications Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp LM 351, LM307 Each 1
5. Bread Board 1
Resistors 10 kΩ 4
1 kΩ 1
6.
100 kΩ 3
200 kΩ 2
7. Capacitors 0.1µF, 0.2 µF, 0.47 µF Each 1
8. Diode 1N914 2
9. Connecting wires and probes As required

THEORY:
Peak Detector

Square, triangular, saw-tooth and pulse waves are typical examples of non-sinusoidal wave
forms. A conventional ac voltmeter cannot be used to measure the rms value of the pure sine
wave. One possible solution for this problem is to measure the peak values of the non-
sinusoidal wave forms.

Model graph:
CIRCUIT DIAGRAM(Peak Detector):

Average Detector

RESULT:
The design and testing of the peak detector & average detector was done and the
input and output waveforms were drawn.
Exp. No.: 11INSTRUMENTATION AMPLIFIER USING IC741

AIM:
To design an Instrumentation Amplifier using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required

THEORY: Gain

CIRCUIT DIAGRAM:
PROCEDURE:
5. Patch the connections and connect the design resistances extending to have the desired
gain.
6. Measure the input voltage at Vin1 and Vin2 using digital multimeter.
7. The difference in Vin2- Vin1 is amplified and indicated in CRO display.
8. Check the theoretical value with the experimental value.

OBSERVATIONS:
Output
S.No Input
Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

RESULT:
The design and testing of the instrumentation amplifier using IC741 is done and
the input and output waveforms were drawn.

Exp No.: 12WEIN BRIDGE OSCILLATOR

AIM:
To construct a wein bridge oscillator for fo = I khz and study its operation

APPARATUS REQUIRED:
S
Name of the Component/Equipment Values/Specifications Quantity
No.
1 OP-AMP IC-741 1
2 RESISTOR 16K, 32K, 1
1.59K, 2
3 CAPACITOR 0.1f 2
4 CRO - 1
5 RPS DUAL(0-30) V 1

THEORY:
In wein bridge oscillator ,wein bridge circuit is connected between the amplifier
input terminals and output terminals . The bridge has a series rc network in one arm and
parallel network in the adjoining arm. In the remaining 2 arms of the bridge resistors R1and
Rf are connected . To maintain oscillations total phase shift around the circuit must be zero
and loop gain unity. First condition occurs only when the bridge is p balanced . Assuming that
the resistors and capacitors are equal in value ,the resonant frequency of balanced bridge is
given by

Fo = 0.159 / RC
DESIGN :
At the frequency the gain required for sustained oscillations is given by
1+Rf /R1 = 3 or Rf = 2R1
Fo = 0.65/RC and Rf = 2R1

CALCULATION:
THEORETICAL Fr = 1/(2*3.14*R*C)

CIRCUIT DIAGRAM:

CALCULATION:
THEORETICAL: F = 1/(2*3.14*R*C)

PRACTICAL: F = 1/T

OBSERVATIONS:
Output
S.No
Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

PROCEDURE:
1. R,C,R1,Rf are calculated for the given value of Fo
2. Connections are given as per the circuit diagram.
3. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
 4. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
5. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.

RESULT :
Hence the wein bridge oscillator is studied and its output waveform traced.

Exp No.:13MULTI VIBRATOR USING 555 TIMER

13 a. MONOSTABLE MULTI VIBRATOR

AIM:
Design themonostablemultivibrator using the IC555.

APPARATUS REQUIRED:
S No. Name of the Component/Equipment Values/Specifications Quantity
1 IC NE555 1
2 RESISTOR 9K 1
3 CAPACITOR 0.01F 1
0.1F 1
4 RPS (0-30) V 1
5 CRO - 1

THEORY:
A monostablemultivibrator has one stable state and a quasistable state. When it
is triggered by an external agency it switches from the stable state to quasistable state and
returns back to stable state. The time during which it states in quasistablestate is determined
from the time constant RC. When it is triggered by a continuous pulse it generates a square
wave. Monostable multi vibrator can be realized by a pair of regeneratively coupled active
devices, resistance devices and op-amps.

DESIGN :
T = 0.1ms
C = 0.01F
T = 1.096RC
R = T / 1.096C = (0.1*10 -3) / (1.096*0.01*10-6)
= 9.12 KR  9 K
CIRCUIT DIAGRAM :

PINDIAGRAM:

PROCEDURE:
1. The connections are made as per the diagram. The value of R is chosen as
9k. The DCB is set to the designed value. The power supply is switched on
and set to +5V.
2. The output of the pulse generator is set to the desired frequency. Here the
frequency of triggering should be greater than width of ON period (i.e.) T >W.
3. The output is observed using CRO and the result is compared with the
theoretical value. The experiment can be repeated for different values of C and
the results are tabulated.

OBSERVATION:
Sl No C (uf) Theoritical(Tp=1.095 RC(ms))) Practical T(ms)
Model Graph:

RESULT:
Thus the monostablemultivibrator using IC555 is designed and its output waveform is
traced

13.b. ASTABLE MULTIVIBRATOR

AIM:
To study the application of IC555 as an astablemultivibrator.

APPARATUS REQUIRED :
S No. Name of the Component/Equipment Values/Specifications Quantity
1 IC NE555 1
1K, 1
2 RESISTOR 1
2.2K
0.1F 1
3 CAPACITOR 1
0.01F
4 CRO - 1
5 RPS DUAL(0-30) V 1

THEORY:
The IC555 timer is a 8 pin IC that can be connected to external components for
astable operation. The simplified block diagram is drawn. The OP-AMP has threshold and
control inputs. Whenever the threshold voltage exceeds the control voltage, the high output
from the OP –AMP will set the flip-flop. The collector of discharge transistor goes to pin 7.
When this pin is connected to an external trimming capacitor, a high Q output from the flip
flop will saturate the transistor and discharge the capacitor. When Q is low the transistor
opens and the capacitor charges.
The complementary signal out of the flip-flop goes to pin 3 and output. When
external reset pin is grounded it inhibits the device. The on – off feature is useful in many
application. The lower OP- AMP inverting terminal input is called the trigger because of the
voltage divider. The non-inverting input has a voltage of +Vcc/3, the OP-Amp output goes
high and resets the flip flop.
CIRCUIT DIAGRAM:

PIN DIAGRAM:

PROCEDURE :
1. The connections are made as per the circuit diagram and the values of R and C are
calculated assuming anyone term and they are settled.
2. The output waveform is noted down and graph is drawn and also the theoretical and
practical time period is verified.

OBSERVATION:

Sl No. C (uf) Theoretical Practical time Theoretical Practical

time period(us) period(us) freq (kHz) freq(kHz)
CALCULATION:
THEORETICAL:T = 0.69(Ra+Rb)C=0.69(1*103 + 2.2*103)*0.01*10-6) = 0.22s
PRACTICAL: T = Ton + Toff

MODEL GRAPH:

Result :
Thus the astablemultivibrator circuit using IC555 is constructed and verified its
theoretical and practical time period.

Exp No: 14PHASE LOCK LOOP

AIM:
To construct and study the operation of PLL IC 565 and determine itsCharacteristics.

APPARATUS REQUIRED:
S.No Components Range Quantity
1 IC 565 - 1
2 Resistors 6.8 K 1
3 Capacitors 0.001 F 1 each
0.1 F, 1 F
4 Function Generator (1Hz – 1MHz.) 1
5 C.R.O - 1
6 Dual Power Supply 0- 30 V 1
CIRCUIT DIAGRAM:

PIN DIAGRAM (IC 565 - PLL)

-Vcc 1 14 No Connection

Input 2 13 No Connection

Input 3 12 No Connection

NE 565
VCO Output 4 11 No Connection

Phase Comparator VCO Input 5 10 +Vcc

Reference Output 6 9 External Capacitor for VCO

Demodulated Output 7 8 External Resistor for VCO

PROCEDURE:
1. The connections are given as per the circuit diagram.

2. Measure the free running frequency of VCO at pin 4, with the input signal Vi set
equal to zero. Compare it with the calculated value = 0.25 / (RT CT).

3. Now apply the input signal of 1 VPP square wave at a 1 KHz to pin 2. Connect
one channel of the scope to pin 2 and display this signal on the scope.

4. Gradually increase the input frequency till the PLL is locked to the input
frequency. This frequency f1 gives the lower end of the capture range. Go on
increasing the input frequency, till PLL tracks the input signal, say, to a frequency
f2.This frequency f2 gives the upper end of the lock range. If input frequency is
increased further, the loop will get unlocked.

5. Now gradually decrease the input frequency till the PLL is again locked. This is
the frequency f3, the upper end of the capture range. Keep on decreasing the input
frequency until the loop is unlocked. This frequency f4 gives the lower end of the
lock range.

6. The lock range fL = (f2 – f4). Compare it with the calculated value of  7.8 fo
/12. Also the capture range is fc = (f3 – f1).Compare it with the calculated value
of capture range.

fc =  (fL / (2)(3.6)(103) C)1/

OBSERVATION:

INPUT WAVEFORM OUTPUT WAVEFORM

Square wave Signal Square wave Signal with Multiple Freq.

Amplitude (V) Amplitude (V)

Time (ms) Time (ms)

Frequency (Hz) Frequency (Hz)
MODEL GRAPH

RESULT :
Thus the Phase lock loop using IC LM565 is constructed and verified capture and look in
range.

Exp No: 15A/D AND D/A CONVERTOR

AIM:
To construct and study the operation ofA/D and D/A convertor.

APPARATUS REQUIRED:
Sl No. Component/Equipment Values/Specifications Quantity
1 OP-AMP IC-741 1
2. ADC 0808 1
3 RESISTOR 10k, 5k, 2.5k, Each 1
1.25k,
4 LED 8
5 Multimeter - 1
6 RPS (0-30) V 1
7 Variable voltage source 0-15 V 1
THEORY:
D/A CONVERTOR:
A D/A converter using binary-weighted resistors is shown in the figure below. In the circuit,
the op-amp is connected in the inverting mode. The op-amp can also be connected in the non-
inverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of
binary inputs is four.

CIRCUIT DIAGRAM:

D/A CONVERTOR:
The ADC0808 is an 8-bit Analog-to-Digital converter IC which uses the successive
approximation technique for the conversion. It has a total unadjusted error of ±½ LSB. It is
capable of converting one of the eight analog input signals, selected with the help of an 8-
channel multiplexer. The clock signal required by the IC is generated using an
astablemultivibrator circuit constructed using 7404 inverter gates. The digital output is
displayed using an array of eight LEDs.
CIRCUIT DIAGRAM:

OBSERVATIONS:

D/A CONVERTOR

Input data Output voltage (V0)

S.No
b0 b1 b2 b3 Practical Theoretical
1.
2.
CURRENT TO VOLTAGE CONVERTOR

Input Output data

S.No
voltage (V) D0 D1 D2 D3 D4 D5 D6 D7
1.
2.

RESULT:
The design and testing of the analog to digital converter and digital to analog
converter was done and the input and output reading has been tabulated.