Quick roadmap

• Start at Level 0 (fundamentals) → 6–10 weeks; Level 1 → 8–12 weeks; Level 2 → 3–6
months; Level 3 (layout/verification + tapeout practices) → ongoing.
• Focus: understand concepts, simulate in SPICE, then implement/layout in
Cadence Virtuoso.

Level 0 — Must-know fundamentals (the foundation)

• Basic circuit theory: KCL/KVL, series/parallel, Thévenin/Norton, nodal/mesh
analysis.
• Passive elements & AC basics: resistors, capacitors, inductors, phasors,
impedance, R-C time constants, filters.
• Signals & systems (short): Fourier series/transform, Laplace, sampling theorem,
basic convolution.
• Semiconductor physics (intro): energy bands, PN junction, carrier drift/diffusion,
depletion, built-in potential.
• Diode & BJT basics: diode I–V, small-signal diode model, BJT operation regions,
biasing.
• MOSFET basics: device terminals, regions (cut-off/triode/sat), threshold voltage,
body effect.
• Small-signal modelling: gm, ro, small-signal π/hybrid models for BJT and MOS,
lambda (channel-length modulation).
• Basic mathematics: complex numbers, linear algebra (for solving circuits),
probability basics (for mismatch/noise).
• SPICE intro: write a netlist, run DC/AC/transient, plot waveforms, sweep
parameters.

Level 1 — Core analog circuit design (single-transistor →

op-amp)
• Single-stage amplifiers: CS/CE/CG/CD operation, biasing, gain, input/output
swing, load effects.
• Small-signal analysis of stages: calculate Av, Rin, Rout, bandwidth, Miller effect.
• Current mirrors & biasing: simple mirror, Wilson/cascode mirrors, reference
design.
• Differential amplifiers: tail currents, common-mode rejection ratio (CMRR),
differential pair behaviour.
 • Frequency response: poles/zeros, Bode plots, dominant pole, gain-bandwidth
product.
• Noise fundamentals: thermal vs flicker (1/f) noise, input-referred noise, noise
figure basics.
• Feedback & stability: loop gain, phase margin, unity-gain crossing, Miller
compensation.
• Operational amplifiers: single-stage, two-stage, telescopic & folded-cascode
topologies — design tradeoffs.
• Design tradeoffs: power vs noise vs bandwidth vs area — how specs trade with
device sizing.

Level 2 — Intermediate / advanced analog VLSI concepts

• Op-amp topologies in depth: telescopic cascode, folded cascode, two-stage with
Miller, gain boosting.
• Fully differential design: differential signalling, common-mode feedback (CMFB)
design & stability.
• Advanced biasing & references: bandgap references, sub-threshold design,
replica biasing.
• Matching & device mismatch: Pelgrom’s law, sizing vs matching tradeoffs,
distance effects.
• Noise & distortion: input-referred noise, phase noise (for oscillators/PLLs),
harmonic distortion/THD.
• Low-voltage & low-power techniques: body biasing, stacked devices, dynamic
biasing.
• Switched-cap & sampled systems: sample-and-hold, switched-capacitor filters.
• Data converters (overview + deeper): ADC architectures (SAR, Sigma-Delta,
pipeline, flash), DAC types and design considerations.
• Clocking / PLLs / VCOs: basics of PLL loop, VCO design, phase noise concepts.
• Power management blocks: LDO design fundamentals, PMOS/NMOS pass
devices, PSRR basics.

Level 3 — Layout, post-layout and manufacturing (how

silicon is really made)
• Analog layout fundamentals: common-centroid, interdigitation, symmetrical
routing, dummy structures.
• Parasitics & extraction: metal/interconnect parasitic capacitances,
resistor/capacitor modeling, parasitic extraction (PEX).
• DRC / LVS / PEX flows: run design-rule checks, layout-versus-schematic, parasitic
extraction → required for tapeout (industry tools: Calibre).
 • Process Design Kits (PDK): how PDKs supply device models, PCells, rule files and
why designers must use a PDK.
• Device models & simulation accuracy: BSIM/BSIM4 & compact models, corners,
temperature, and voltage variations.
• Statistical analysis: Monte-Carlo, corner (PVT) analysis, mismatch budgeting and
yield estimation.
• Reliability & foundry sign-offs: ESD/EMI considerations, antenna rules, metal
density rules, sign-off verification.

Tools & software (what to learn, in order)

• LTspice / Ngspice: quick circuit exploration and learning.
• Cadence Virtuoso + Spectre (Analog design flow): schematic → simulation →
layout → LVS/PEX → sign-off.
• Calibre (Siemens) or Mentor tools: DRC/LVS/physical verification.
• Scripting & automation: Python for data analysis, SKILL for Cadence automation,
Verilog-A for compact models.
• MATLAB/Octave: system-level modeling, filter & control analysis.
• Version control & docs: Git + clear design reports and datasheets for interview
portfolio.

Recommended chapter-wise book/course mapping (study

in this order)
• MOSFET physics & single-device: Razavi Ch.2 + BSIM docs.
• Single-stage amplifiers & mirrors: Razavi Ch.3–5.
• Frequency response & noise: Razavi / NPTEL advanced analog course.
• Op-amp topologies & compensation: Razavi / Baker / Johns & Martin.
• Layout & matching: Baker (CMOS layout chapters) + papers on common-
centroid/interdigitation.
• Data converters & PLLs: Razavi (data converters) + specialist texts (Razavi ADC
book).

Projects that show employers you’re serious (begin →

advanced)
• Beginner: simulate MOSFET I–V and simple CS amplifier in LTspice.
• Intermediate: design & simulate a 2-stage op-amp (specify GBW, PM, gain) and
show small-signal/noise analysis.
 • Layout project: create a matched current mirror layout with common-centroid
fingers and pass DRC/LVS.
• Advanced: design a SAR ADC front-end or a folded-cascode op-amp, do post-
layout extraction and Monte-Carlo, write a 2-page spec & test plan.
• Showcase: Github (schematics + netlists), PDF design reports, Cadence
screenshots, and measured results if you can tape out/test.

What recruiters at core analog VLSI companies look for

• Hands-on Cadence/spectre + post-layout simulation experience and clear
project reports.
• Strong MOSFET understanding, noise & mismatch reasoning, and layout sense.
• Ability to trade off area/power/noise/bandwidth and explain decisions in
interviews.

Study & practise checklist (short)

• Learn MOSFET physics → simulate devices in SPICE.
• Do small-signal analysis by hand for CS/diff pair → verify in SPICE.
• Build and simulate op-amp topologies → add compensation and check PM.
• Create layouts for matched devices → run DRC/LVS (Calibre or tool provided).
• Run PEX & post-layout simulation → do Monte-Carlo & corner analysis.
• Prepare 3 project reports (theory + schematic + layout + results).

Quick resource links (books & courses to grab first)

• Behzad Razavi — Design of Analog CMOS Integrated Circuits (core analog).
• Jake Baker — CMOS Circuit Design, Layout and Simulation (layout + practical).
• Johns & Martin / Carusone et al. — Analog IC Design (complementary
perspectives).
• NPTEL / Swayam Analog IC Design — syllabus & lecture notes for advanced op-
amp, noise & mismatch.
• Cadence Virtuoso docs & Spectre tutorials — learn the actual tool flow.

If you want, I can now:

• Turn this into a downloadable checklist (spreadsheet or PDF) you can tick off, or
 • Make a week-by-week 6-month study plan with exact chapters, lab exercises
(LTspice + Cadence), and projects.

Which would you like next?