Lecture Notes 4

CMOS Image Sensors

• CMOS Passive Pixel Sensor (PPS)

◦ Basic operation
◦ Charge to output voltage transfer function
◦ Readout speed
• CMOS Photodiode Active Pixel Sensor (APS)
◦ Basic operation
◦ Charge to output voltage transfer function
◦ Readout speed
• Photogate and Pinned Diode APS
• Multiplexed APS

EE 392B: CMOS Image Sensors 4-1

 Introduction

• CMOS image sensors are fabricated in “standard” CMOS technologies

• Their main advantage over CCDs is the ability to integrate analog and
digital circuits with the sensor
◦ Less chips used in imaging system
◦ Lower power dissipation
◦ Faster readout speeds
◦ More programmability
◦ New functionalities (high dynamic range, biometric, etc)
• But they generally have lower perofrmance than CCDs:
◦ Standard CMOS technologies are not optimized for imaging
◦ More circuits result in more noise and fixed pattern noise
• In this lecture notes we discuss various CMOS imager architectures
• In the following lecture notes we discuss fabrication and layout issues

EE 392B: CMOS Image Sensors 4-2

 CMOS Image Sensor Architecture

Word

Row Decoder
Pixel:
Photodetector
& Readout
treansistors Bit

Column Amplifiers/Caps

Output
Column Mux

• Readout performed by transferring one row at a time to the column

storage capacitors, then reading out the row, one (or more) pixel at a
time, using the column decoder and multiplexer
• In many CMOS image sensor architectures, row integration times are
staggerred by the row/column readout time (scrolling shutter)

EE 392B: CMOS Image Sensors 4-3

 CMOS Image Sensor Pixel Architectures

• Passive pixel (PPS) word

◦ 1 transistor per pixel

◦ small pixel, large fill factor
◦ slow, low SNR Bit

• Active pixel (APS)

◦ 1.5-4 transistors per pixel
◦ faster, higher SNR
◦ larger pixel, lower fill factor
◦ current technology of choice
• Digital pixel (DPS)
◦ 5+ transistors per pixel
◦ scales well with technology
ADC MEM
◦ very fast, no column noise or FPN
◦ larger pixel, complex implementation

EE 392B: CMOS Image Sensors 4-4

 Passive Pixel Sensor (PPS)

Pixel (i, j) Column Amp/Cap/Mux Output Amplifier

Word i

Reset

Bit j

Col j
Cf
Out

Coj
V_REF

Reset

Integration Time Word i

Col j
Row i Read
Word i+1

EE 392B: CMOS Image Sensors 4-5

 Comments on Operation

• Charge is read out via a column charge amplifier (also referred to as

Capacitive Trans-impedence Amplifier (CTIA))
• Reading is destructive (much like a DRAM)
• Vertical charge binning is very easy to implement
• Diode reverse bias voltage at end of reading ≈ vREF
PSfrag replacements

• Column and chip amplifiers are simple follower amplifiers

vDD

vbias1

Colj
Out
From output
of charge vbias2
amplifier
Coutj

Column Follower Amp Chip Follower Amp

• Depending on the design, frame readout time can be limited either by the
row transfer time or by the column readout time
EE 392B: CMOS Image Sensors 4-6
 PPS Charge to Output Voltage Transfer Function

• Consider the PPS column read circuit

PSfrag replacements Word

CD Cb

Cf
vo(∞)
vREF
vo
t
vREF

• In steady state, assuming charge Qsig (electrons) accumulated on the

photodiode at the end of integration (and ignoring “feedthrough” voltage
added when the reset transistor is turned off and opamp offset voltage),
the output voltage
qQsig
vo = vREF +
Cf
Thus the sensor conversion gain is Cq V/electron
f

EE 392B: CMOS Image Sensors 4-7

 • Now let’s find the sensor voltage swing vs
The minimum output voltage occurs when Qsig = 0 and we obtain
vomin = vREF
The maximum output voltage occurs when the voltage on the diode
reaches ground, which gives
CD
vomax = vREF + vREF ,
Cf
provided that vomax does not exceed the opamp maximum output voltage
vSat (in this case vomax = vSat)
Thus the sensor voltage swing
 
CD
vs = min vREF , vSat − vREF
Cf
• Note: Since the CTIA can be designed to have very high linearity, the
output voltage (at the column) is quite linear in illumination (F0) (this is
not the case in APS as we shall see)

EE 392B: CMOS Image Sensors 4-8

 PPS Readout Speed

• Row readout is performed in two stages; first the row is transferred to the
column capacitors, then the column decoder/multiplexer is used to serially
read out the pixel values
• Row transfer time trow is the time from Word going high to the time vo is
within  of its final value vo(∞)
• For k bits of resolution we need to choose
vs
≤ k
V,
2×2
where vs is the output voltage swing, e.g., for k = 8 bits,
vs
≤
512
• Worst transfer time occurs when vo(∞) is maximum, i.e., equal to vomax
• Example: consider a PPS with n = 256 rows, CD = Cf = 20fF, and
Cb = n × 2.6fF= 0.6656pF, find the maximum row transfer time assuming
k = 8 bits of resolution
EE 392B: CMOS Image Sensors 4-9
 To simplify the analysis we assume:
◦ Single-pole open-loop model for op-amp of charge amplifier, i.e.,
Vo(s) A
= A(s) = ,
V+(s) − V−(s) 1 + ( ωso )
with dc gain A = 6 × 104 and 3dB bandwidth ωo = 100rad/s
◦ Access transistor has negligible ON resistance
To find the row transfer time trow , we assume that the charge sharing
between CD and Cb occurs instantaneously (the access transistor treated
as a short circuit) and use the equivalent circuit
Cf

PSfrag replacements t=0

vo(t)
Cb + C D
vREF

EE 392B: CMOS Image Sensors 4-10

 To find
PSfrag the transfer
replacements time we substitute the single-pole opamp model to get
Cb + CD Cf
Vo (s)

−
Vi (s) −A(s)V− (s)
+

The transfer function is

Vo(s) Cb + CD 1
≈− · s(C +C +C )
Vi(s) Cf 1 + bAωoDC f
f

Thus the circuit time constant is

Cb + CD + Cf
τ= = 5.88µs,
AωoCf
and the worst case transfer time is given by
trow = τ ln(256 × 2) = 36.5µs

EE 392B: CMOS Image Sensors 4-11

 • Note that
◦ Row transfer time increases almost linearly with Cb (and the number
of rows)
◦ If we try to achieve higher conversion gain by making Cf small, we
increase row transfer time !
◦ Readout time can be reduced by increasing the gain-bandwidth
product of the opamp (Aωo), which would increase power
consumption

EE 392B: CMOS Image Sensors 4-12

 3-T Active Pixel Sensor (APS)

Pixel (i,j)
Reset i

Word i

Bit j
Col j

Out
Vbias Coj

Column Amp/Mux

Word i
Integration Time Reset i
Col j
Row i Read Word i+1
Reset i+1

EE 392B: CMOS Image Sensors 4-13

 Comments on Operation

• Direct integration is used. Voltage is read out of the pixel

• Output of the photodiode is “buffered” using pixel level follower amplifier
— reading is non-destructive and can be much faster than PPS
• Each row has a separate reset (used after reading)
• The photodiode reset voltage vD depends on the type of reset used:
◦ Soft reset: The reset gate is set to vDD and vD = vDD − vT R, where
vT R is the reset transistor threshold voltage (including body effect)
◦ Hard reset: The reset gate is > vDD + vT R and vD = vDD
• By setting the voltage on the reset gate vReset ≥ vT R during integration
(instead of ground), blooming can be controlled (reset transistor doubles
as an anti-blooming device)
• Except for eliminating the charge amplifier, the column amplifier and
decoder are identical to PPS

EE 392B: CMOS Image Sensors 4-14

 APS Charge to Output Voltage Transfer Function
vDD vDD
PSfrag replacements
Reset

Cb
Word
vo

vbias Co

• Assuming charge Qsig is accumulated on the photodiode at the end of

integration, soft reset is used, and ignoring the voltage drop across the
access transistor, then in steady state, the output voltage
qQsig
vo = v D − − vGSF
CD
qQsig
= (vDD − vT R) − − vGSF ,
CD
where vGSF is the follower transistor gate to source voltage and
EE 392B: CMOS Image Sensors 4-15
 q
The sensor conversion gain is thus CD
µV/electron
• Now, let’s find the voltage swing vs
To keep the bias transistor in saturation we choose
vomin = vbias − vT B ,
where vT B is the bias transistor threshold voltage
The maximum output voltage occurs when Qsig = 0, thus
vomax = vDD − vT R − vGSF
• To find vGSF consider the circuit (in steady state) (ibias is column amp
bias current)
vDD
PSfrag replacements
follower
vD ibias

vomax

vbias
ibias
bias

EE 392B: CMOS Image Sensors 4-16

 Assuming the static first order MOS transistor model, we obtain
kn W F
ibias = · (vGSF − vT F )2,
2 LF
where WF and LF are the follower transistor width and length, kn is its
transconductance parameter (A/V2), and vT F is its threshold voltage
Thus r
2LF
vGSF = vT F + ibias
kn W F
Thus the voltage swing is given by
vs = vDD − vT R − vGSF − vbias + vT B
• Remarks:
◦ The available well capacity qQmax = vD × CD cannot be fully utilized,
since vomin is achieved before the diode voltage drops to ground
◦ The column output voltage is quite nonlinear in illumination (F0)
∗ The collected charge is converted to voltage using the diode
capacitance
∗ The follower nonlinearity due to backgate effect (body tied to
ground) and channel length modulation
EE 392B: CMOS Image Sensors 4-17
 • Example: Consider an APS implemented in the 0.5µ CMOS technology
described in Handout 4 with n = 256 rows, vT F = 0.9V, vT R = 1.1V,
vT B = 0.8V, and the parameters shown in the figure
PSfrag replacements 3.3V 3.3V

Reset 4/2
4/2

4/2 Cb = n × 3f F
Word
vo

16/32
1V Co = 3pF

Let’s compute the output voltage swing vs. The minimum output voltage
vomin = vbias − vT B = 0.2V
The bias current using kn = 188µA/V2 is ibias = 1.88µA, and the
maximum output voltage is
vomax = vDD − vT R − vGSF = 3.3 − 1.1 − 1.0 = 1.2V
Thus the voltage swing
vs = 1.0V
EE 392B: CMOS Image Sensors 4-18
 APS Readout Speed

• Readout time for a row is the sum of the time to transfer the row to the
column capacitors and the time to read out the pixel values via the
column multiplexer (column readout time)
• APS column readout time (and not row transfer time) is the real
performance limiter if the sensor is read out serially (row readout time
becomes the limiting factor for parallel/on-chip readout)
• Let’s find the row transfer time assuming k = 8 bits of resolution for the
example APS
To find the worst case row transfer time, we use the following equivalent
circuit

EE 392B: CMOS Image Sensors 4-19

 3.3V

PSfrag replacements 2.2V follower

3.3V

0V vo

1.88µA Co0 = (3 + 0.768)pF

Define the row transfer time trow as the time from the access transistor
turning on to the output voltage vo reaching to within half a bit of its
steady state value, i.e.,
vs
vo(trow ) ≥ vo(∞) − k+1
2
By KCL
dvo
1.88 × 10−6 + Co0 = 188 × 10−6 × (1.3 − vo)2
dt

EE 392B: CMOS Image Sensors 4-20

 This differential equation can be solved analytically by separation of
variables, and we obtain
Co0
 
(β + ρ)(α − ρ)
trow = √ ln ,
2 knibias (β − ρ)(α + ρ)
where
r
ibias
ρ =
kn
α = vo(∞) + ρ − vo(0)
β = vo(∞) + ρ − vo(trow )

Using the previous parameter values and assuming k = 8bits, we have

◦ vo(0) = vomin = 0.2V
◦ vo(∞) = vomax = 1.2V
◦ vo(trow ) = 1.198V
Substituting, we obtain
trow = 444 ns

EE 392B: CMOS Image Sensors 4-21

 APS Readout Speed from HSPICE Simulation

1.2

1.1

1.0

0.9

0.8
vo (V)

0.7

0.6

0.5

0.4
ag replacements
0.3 trow
0.2
0 0.25 0.5 0.75 1.0 1.25 1.5

time (µs)
EE 392B: CMOS Image Sensors 4-22
 Comments on APS Readout Speed

• The row transfer time increases linearly with Cb (same as PPS)

• It decreases with bias current ibias. Reducing bias current also increases
voltage swing and reduces power consumption
• It is considerably shorter than PPS. Our estimate, however, is somewhat
optimistic as you can see from the HSPICE simulations, which gives
around 570ns. This is because we made several simplifying assumptions
including ignoring access transistor resistance, transistor channel
modulation, and assuming quadratic current law. The effects of these
nonidealities are discussed in [Salama’ 03]
• The analysis we performed assumed that the bitline is reset after each row
read. If the bitline is not reset and is allowed to be discharged through the
bias current, the row transfer time becomes dominated by the discharge
time
• PPS can be made as fast as APS by using a faster charge amplifier.
However, readout power consumption becomes much higher than APS
EE 392B: CMOS Image Sensors 4-23
 4.1-Mpixel APS Example

• 0.35 µm 2P3M process

• 2352(H)×1728(V) pixels
• 240 Frames/sec
• 7µm × 7µm pixel
• 10 bit column ADC
• Conversion gain: 39 µV/e-
• Sensitivity @550nm: 2.5 V/[Link]

Krymski et al. “A High-Speed, 240-Frames/s, 4.1-Mpixel CMOS Sensor,” IEEE Transactions on Electron Devices,
vol. 50, pp. 130-135, January 2003

EE 392B: CMOS Image Sensors 4-24

 4.1-Mpixel APS Circuit and Layout

• APS readout circuit sampled and directly converted by per-column

successive approximation ADC

Krymski et al. “A High-Speed, 240-Frames/s, 4.1-Mpixel CMOS Sensor,” IEEE Transactions on Electron Devices,
vol. 50, pp. 130-135, January 2003

EE 392B: CMOS Image Sensors 4-25

 CMOS Photogate APS
vDD
Reset i
vDD
Gij Xi
Dij

P-sub n+ n+
PSfrag replacements
Pixel(i, j) Word i

bit j

Reset i

vX Xi

Gij
vDD
integration

Word i

EE 392B: CMOS Image Sensors 4-26

 Potential Well Diagram for Photogate APS

vDD
G X
Reset

During integration

During reset

PSfrag replacements

During charge transfer

During readout

EE 392B: CMOS Image Sensors 4-27

 Comments on Operation

• Before reading a row

◦ Floating node Dij is reset
◦ To transfer the accumulated charge on the photogate to the floating
node Dij , the transfer gate is turned to an intermediate voltage
vX ≤ vDD
2
V and the gate voltage is lowered to 0V (CCD like
operation)
• The transfer gate can also be kept at a constant intermediate voltage
throughout to avoid blooming and to reduce switching noise
• Well capacity is determined by the voltage swing on the floating node and
its capacitance Cd
• Column and chip circuits are identical to photodiode APS and the rest of
readout operation is identical to photodiode APS
• The subcircuit consisting of the transfer gate, reset transistor and follower
transistor is the same as the CCD output amplifier circuit

EE 392B: CMOS Image Sensors 4-28

 Advantages and Disadvantages of Photogate

Advantages:
• Conversion gain Cq is independent of photodetector, can achieve higher
d
conversion gain than photodiode APS (lower QE, however)
• Cd very useful, can be used for
◦ Providing “snap shot” operation by globally turning on all transfer
gates (readout still performed one row at a time)
◦ Performing true correlated double sampling (CDS)
Disadvantages:
• More devices (larger pixel or lower fill factor than photodiode)
• Lower QE, poor blue response
• Incomplete charge transfer due to the n+ drain of the transfer gate (we
are assuming a standard CMOS process here)

EE 392B: CMOS Image Sensors 4-29

 Pinned Diode APS
vDD

Reset i
vDD
PSfrag replacements Xi
Dij
vDD p+ n+
P-sub n

Pixel(i, j) Word i

bit j

Reset i
integration

vX Xi
Gij
Word i

EE 392B: CMOS Image Sensors 4-30

 Comments on Operation

• Operation similar to photogate APS

• Before reading a row
◦ Floating node Dij is reset to vDD
◦ The transfer gate is turned on to transfer the accumulated charge to
the floating node Dij
• “snap-shot” operation can be performed by globally turning on all transfer
gates (readout performed one row at a time)
• Well capacity is determined by the voltage swing on the floating node and
its capacitance Cd

EE 392B: CMOS Image Sensors 4-31

 Advantages and Disadvantages of Pinned Photodiode

Advantages:
• Conversion gain Cq is independent of photodiode capacitance and can be
d
tailored for application (e.g., low-light sensitivity)
• Allows for true correlated double sampling (CDS)
• High QE in blue range
• Typically much lower dark current than standard nwell/psub diode
• Isolated floating diffusion allows for transistor sharing
Disadvantages:
• Requires significant modifications to standard CMOS process
• Higher reset voltage required for complete transfer
• Larger pixel required unless transistors are shared

EE 392B: CMOS Image Sensors 4-32

 1.3-Mpixel Pinned Diode APS Example

• 0.35 µm 1P3M CMOS process

• 1280(H)×1024(V) pixels
• 30 Frames/sec
• 5.6 µm x 5.6 µm pixel
• 11 bit ADC
• Conversion gain: 26 µV/e-
• Sensitivity @550nm: 1.4 V/Lux-sec

Findlater et al. “SXGA Pinned Photodiode CMOS Image Sensor in 0.35µm Technology,” IEEE International
Solid-State Circuits Conference, 12.4, 2003

EE 392B: CMOS Image Sensors 4-33

 Multiplexed Pinned Diode APS

• Charge transfer devices may share readout transistors

◦ The floating diffusion (FD) is common to multiple transfer gates
◦ Less transistors per pixel – increased fill factor
TX0
VDD
VDD
RT
RT
PSfrag replacements TX
PSfrag replacements
=⇒ TX1 FD
FD

RS RS

COL COL

• Sharing is not possible with 3T type APS structure

EE 392B: CMOS Image Sensors 4-34

 1.75 Transistors Per Pixel
TX0

TX1
VDD

RT

FD
TX2

RS

COL
PSfrag replacements

TX3

EE 392B: CMOS Image Sensors 4-35

 1.75T Imager Example

Mori et al. “1/4-Inch 2-Mpixel MOS Image Sensor With 1.75 Transistors/Pixel,” IEEE Journal of Solid-State
Circuits, vol. 39, pp 2426-2430, December 2004

EE 392B: CMOS Image Sensors 4-36

 1.5 Transistors Per Pixel

TX0

TX1 COL(i, j)

RS(k, j)
VDD
FD

TX2 TX(i, j)

RS
PSfrag
COL replacements
FD(k, j)
PSfrag replacements

rowtime
TX3

EE 392B: CMOS Image Sensors 4-37

 Comments on Operation

• Operation made possible by the inherent isolation between floating

diffusion and photodiode during integration
• Works through “winner-take-all” nature of source follower:
1. Reset the diffusion by pulling column line high and turning RS on
2. Turn TX on to transfer, then read out
3. Turn TX off, then RS on, while pulling column line low
◦ This sets the floating diffusion low, which disables the source
follower from acting on the column line until next selection

EE 392B: CMOS Image Sensors 4-38

 1.5T Imager Example

Takahashi et al. “A 3.9-µm Pixel Pitch VGA Format 10-b Digital Output Cmos Image Sensor With 1.5
Transistor/Pixel,” IEEE Journal of Solid-State Circuits, vol. 39, pp 2417-2425, December 2004

EE 392B: CMOS Image Sensors 4-39

 Disadvantages of Multiplexing

• Requires the use of pinned diode (or photogate)

• Longer array readout
• Introduces additional pixel nonuniformity due to layout asymmetry
◦ Less of a problem when color filter array is used (high uniformity
among groups of 2 × 2 pixels)
• More complex row readout operation

EE 392B: CMOS Image Sensors 4-40

 Digital Pixel Sensor (DPS)

• An important trend in digital imaging system design is the integration of

CMOS image sensor with analog and digital processing down to the pixel
level
• Such integration saves power and reduces system size
• More interestingly, it provides the ability to rethink the imaging system
architecture
• An important example is where and how to perform the A/D conversion
• DPS integrates an ADC per pixel

EE 392B: CMOS Image Sensors 4-41

 ADC Integration Options

Per-pixel (DPS)
Row Decoder

Per-chip
Per-column

PSfrag replacements

Column Multiplexer

EE 392B: CMOS Image Sensors 4-42

 Per-Level ADC (DPS)

• Each pixel (or group of pixels) has an ADC, all ADCs operate in parallel
• Advantages:
◦ High speed readout due to parallel conversion and digital readout
◦ High signal swing
◦ Eliminates column temporal noise and FPN (more on this later)
◦ Process scalable – low speed ADCs using simple circuits
• Disadvantage:
◦ Large pixel size (existing ADC implementations not feasible)
◦ Limited ADC resolution (because of limited pixel size)
◦ Complexity of implementation
• It is possible to perform A/D conversion with very few transistors per
pixels, and
• Pixel size problem becomes less severe as technology scales

EE 392B: CMOS Image Sensors 4-43

 Multi-Channel Bit-Serial (MCBS) ADC [Yang’ 99]

• ADC implements a quantization table

ADC Input Gray Code

0 − 18 000
1 2
8 − 8 001
2 3
8
− 8
011
3
8
− 48 010
4
8
− 58 110
5
8
− 68 111
6
8
− 78 101
7
8 −1 100

• Key Point: Each output bit can be separately generated (this is how flash
ADC performs the conversion)

EE 392B: CMOS Image Sensors 4-44

acements
How 1-bit Comparator/Latch Works

S LSB

RAMP
1 BITX
7 0
8
input2
1
5 D Q OUT
8
input1 0
3 S
8 G
1 RAMP
1
8 0 latch
comparator
Time
1 1

BITX 0 0 0

EE 392B: CMOS Image Sensors 4-45

 MCBS ADC – Block Diagram

channel 1
D
analog
Q out 1
input 1
G

channel 2
D
analog
DAC Q
Controller input 2 out 2
RAMP G
CODE

BITX
BITX

channel n
D
analog
Q
input n out n
G

EE 392B: CMOS Image Sensors 4-46

 Output Image Format

PSfrag replacements 1

0
1
2
1
1
1 1 Next Frame
m
Bit Plane
4
3
2
0 Frame
1
Time

EE 392B: CMOS Image Sensors 4-47

 CCTV DPS Chip [Bidermann’ 04]

• 0.18µm CMOS technology

• 742 × 554 pixel array
• Per pixel-quad MCBS ADC
• 7µ × 7µ pixels
• 5M-bit frame buffer
• Per-column DSP
• Micro-controller
• 500 frames/sec internal
• 60 frames/sec external
• 14-bit dynamic range

EE 392B: CMOS Image Sensors 4-48

 Multiplexed MCBS ADC Pixel Circuit [Bidermann’ 04]

EE 392B: CMOS Image Sensors 4-49

 Single-Slope Based DPS [Kleinfelder’ 01]

• 0.18µm CMOS technology

• 352 × 288 pixels (CIF)
• 9.4µ × 9.4µ pixels
• 37 transistors/pixel
• 3.8 million transistors
• 8 bit single slope ADC and
memory/ pixel
• 64 wide digital output bus at
167 MHz
• > 10, 000 frames/s continu-
ous imaging

EE 392B: CMOS Image Sensors 4-50

 ADC Operation

Counter
(Gray Code)
Latched
Value
Ramp

Gray Code Input

Counter
Analog
8 Comp. 0
Ramp 1 0
Memory Out
Input
8
Memory Memory
Comp. Out Digital Out Loading Latched

EE 392B: CMOS Image Sensors 4-51

 Pixel Schematic

Bias 2
Bias 1 Data I/O
Reset V
Ramp Read 8
Pixel Reset *
TX
PG

* *
*

Sensor Comparator 8-Bit Memory

EE 392B: CMOS Image Sensors 4-52

 Summary

• Described several CMOS image sensor architectures:

◦ PPS
◦ Photodiode APS
◦ Photogate APS
◦ Pinned-diode APS
◦ Multiplexed pinned-diode APS
• Discussed their advantages and disadvantages
• Analyzed PPS and APS readout circuit:
◦ Charge to voltage transfer function
◦ Voltage swing
◦ Readout speed

EE 392B: CMOS Image Sensors 4-53

 Architecture Comparsion

PPS 3T APS Photogate APS Pinned-diode APS

Transistors/pixel 1 3 1.5–4 1.5–4
QE of blue OK OK Bad Very good
Reset Before readout After readout Before readout Before readout
Shutter Scrolling Scrolling Snap-shot Snap-shot
Transfer function Linearity High Low Low Low
Row transfer time Slow Fast Fast Fast

EE 392B: CMOS Image Sensors 4-54