Scribd
Upload
17 views1 page

De Unittest 1

This document outlines the details for the Diploma III-Semester Unit Test in Digital Electronics at Srinivasa Institute of Technology and Science, scheduled for August 12, 2025. It includes information on the exam structure, with Part A consisting of short answer questions and Part B featuring longer, detailed questions. The exam covers various topics such as Boolean algebra, logic families, and CMOS technology.

Uploaded by

shaik jaffar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
17 views1 page

De Unittest 1

This document outlines the details for the Diploma III-Semester Unit Test in Digital Electronics at Srinivasa Institute of Technology and Science, scheduled for August 12, 2025. It includes information on the exam structure, with Part A consisting of short answer questions and Part B featuring longer, detailed questions. The exam covers various topics such as Boolean algebra, logic families, and CMOS technology.

Uploaded by

shaik jaffar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

SRINIVASA INSTITUTE OF TECHNOLOGY AND SCIENCE

CHENNAI-HYDERABADBYPASSROAD,UKKAYAPALLI,KADAPA-516002
Diploma III-SEMISTER Unit Test - I Examinations AUGUST-2025
Course : Diploma
Branch : DECE Date:12-08-2025 (10.30AM - 12.00PM)
Subject: DIGITAL ELECTRONICS(EC-303) Duration: 90 Minutes
Max Marks : 40 Marks Roll No:

PART - A
Answer the following questions 16 M
BT Marks
Q.No Questions Unit Covered
Level Allotted
a) In the ___________ system only the digits 0 and 1 are used.
b)ASCII stands for ________________ and it is widely used
character encoding standard. 1& CO1
1 L2 4
c) Universal gates are _________and__________ 2 &CO2
d) Number of NOR gates required to realize AND gate
is____________________
2 Explain the working of EX-OR gate with Truth Table? 1 L2 CO1 3
Define
3 A) SOP form 1 L2 CO1 3
B) POS form
4 Explain the working principle of CMOS technology with diagram? 2 L2 CO2 3

5 Compare the TTL,CMOS and ECL logic families? 2 L2 CO2 3


PART - B
Answer the following questions 3×8=24 M
BT Marks
Q. No Questions Unit Covered
Level Allotted

6
State different postulates in Boolean algebra? 1 L2 CO1 8
(a)
(OR)
(b) What is K-map and simplify Boolean expression using K-map? 1 L5 CO1 8
Classify the logic families and list the important characterstics of
7 L5
different logic families and voltage and current logic levels of TTL and 2 CO2 8
(a)
CMOS IC’S?
(OR)
Explain the working of Totem pole output TTL NAND gate with
(b) 2 L2 CO2 8
circuit diagram?
Explain the working of open collector TTL NAND gate with
8
circuit diagram? 2 L4 CO2 8
(a)
(OR)

State the concept of combinational logic circuit and explain Half adder
(b) 3 L4 CO3 8
circuit using X-OR, AND gates?

L1 – Remember L2 – Understand L3 – Application L4 – Analyze L5 – Evaluate L6 – Create

Prepared by G. Sharon Rose

You might also like