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LAB MANUAL
For
Analog Electronics Lab
PHYS-312
For
M.Sc. Physics Part-I (Annual System)
M.Sc. Physics Semester-II
BS Physics Semester-VI

By
Shahzad Ali Nasir
Lecturer in Electronics,
Department of Physics,
Government Postgraduate College,
Sahiwal.
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List of Practical
1. Design of Logic Gates
2. Design of Full Wave Rectifier with Capacitor Filter
3. Design of Common Emitter Voltage Amplifier
4. Design of Common Collector Amplifier
5. Design of Astable Multi-Vibrator
6. Design of Mono-Stable Multi-Vibrator
7. Design of Bi-Stable Multi-Vibrator
8. Design of Inverting Amplifier Using Operational
Amplifier
9. Design of Non-Inverting Amplifier Using
Operational Amplifier
10. Design of Unity Follower Using Operational
Amplifier
11. Design of RC-Phase Shift Oscillator

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Practical No.1

Design and Implement different logic gates on

bread board using Diode-Resistor/Diode-
Transistor logics.

(a) Two Input OR-Gate

(b) Two Input And-Gate
(c) NOT-Gate
(d) Two Input NOR-Gate
(e) Two Input NAND-Gate

Apparatus:
1. 5 Volt DC Power Supply
2. 1N4007 Diodes
3. C945 Transistor
4. 1/4 Watt Carbon film Resistors
5. Crystal LEDs
6. Connecting Wires
7. Digital Multi-Meter
8. Light Emitting Diodes (LEDs)

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Two Input OR-Gate

The OR-gate is a logic gate that implements logical disjunction. A HIGH output (1) results if
one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0)
results. In another sense, the function of OR effectively finds the maximum between two
binary digits.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Apply different combinations of logical inputs on input terminals A & B.
3. Measure the corresponding logical output at the output terminal labeled as X.
i. One way to check output logic level is with the help of a Multi-Meter.
(Voltage range 0 V to 1.5 V will indicate Logic 0 while voltage range of 3.5 V
to 5 V will indicate Logic 1)
ii. Another way to check output logic level is to insert a Crystal LED in series
with the resistance R. (ON LED will indicate Logic 1 and OFF LED will
indicate Logic 0)
4. Record all possible input and output combinations in the table.

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Working:

1. When A = 0 and B = 0 then both the diodes are reverse biased there will be no current
through the load resistance R and voltage drop across load resistance will be zero volt So X =
0.
2. When A = 0 and B = 1 then the D 1 is reverse biased and D 2 is forward biased, current will
pass through load resistance R and voltage drop across load resistance will be high So X = 1.
3. When A = 1 and B = 0 then the D 1 is forward biased and D 2 is reverse biased, current will
pass through load resistance R and voltage drop across load resistance will be high So X = 1.
4. When A = 1 and B = 1 then both the diodes are forward biased and current will pass through
the load resistance R and voltage drop across load resistance will be high So X = 1.

Truth Table:

A B X
0 0 0
0 1 1
1 0 1
1 1 1

Calculations:

We have chooses 1N4007 Silicon diodes which have a typical forward voltage of 0.7 V and
can handle an average forward current of 1 A.

The output Logic level is obtained across the ¼ watt carbon film resistor so we have to be
careful in choosing its value.

In case of Logic 1 at output maximum value of Vout = 5 V

So we can choose minimum value of as

R = (Vout )2 /P

= (5)2 /0.25

= 100 Ω (You may use any value of R equal or greater than this minimum value)

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For example use R = 220 Ω

In case of Crystal LED indicator we have to limit its forward current IF to 20 mA because it
can handle only this amount of forward current. So in this case we have to choose minimum
value of R by following procedure:

Vout = VLED + VR

= VLED + IF R (VLED = 3.2 V for White Crystal LED)

 R = (Vout - VLED)/IF
= 1.8 V/20 mA
= 90 Ω (You may use any value of R equal or greater than this minimum value of R)
For example use R = 220 Ω.

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Two Input AND-Gate

The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH
output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one
input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND
effectively finds the minimum between two binary digits. Therefore, the output is always 0
except when all the inputs are 1s.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Apply different combinations of logical inputs on input terminals A & B.
3. Measure the corresponding logical output at the output terminal labeled as X.
i. One way to check output logic level is with the help of a Multi-Meter.
(Voltage range 0 V to 1.5 V will indicate Logic 0 while voltage range of 3.5 V
to 5 V will indicate Logic 1)
ii. Another way to check output logic level is to insert a Crystal LED in series
with the resistance R1 between terminal X and Ground. (ON LED will indicate
Logic 1 and OFF LED will indicate Logic 0)
4. Record all possible input and output combinations in the table.

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Working:

1. When A = 0 and B = 0 both diodes are forward biased and offer low resistance to current.
Current will pass through both diodes and will be grounded. Voltage at output terminal will
be 0.7 V which is considered as low So X = 0.
2. When A = 0 and B = 1 D2 is reverse biased and D 1 is forward biased and offer low resistance
to current. Current will pass through D 1 and will be grounded. Voltage at output terminal will
be 0.7 V which is considered as low So X = 0.

3. When A = 1 and B = 0 D1 is reverse biased and D 2 is forward biased and offer low resistance
to current. Current will pass through D 2 and will be grounded. Voltage at output terminal will
be 0.7 V which is considered as low So X = 0.
4. When A = 1 and B = 1 both diodes are reverse biased and offer high resistance to current.
Current will not pass through any of the diodes. Voltage at output terminal will be Vcc which
is considered as High So X = 1.

Truth Table:

A B X
0 0 0
0 1 0
1 0 0
1 1 1

Calculations:

We have choosen 1N4007 Silicon diodes which have a typical forward voltage of 0.7 V and
can handle an average forward current of 1 A.

The output Logic level is obtained between terminal-X and ground so we have to be careful
in choosing the value of R which is connected between DC power supply and terminal-X.

In case of Logic 0 at output maximum value of VR = 5 V

So we can choose minimum value of as

R = (Vout )2 /P

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= (5)2 /0.25

= 100 Ω (You may use any value of R equal or greater than this minimum value)

In case of Crystal LED indicator we have to limit its forward current I F to 20 mA because it
can handle only this amount of forward current. So in this case we have to choose minimum
value of R and R1 by following procedure:

VDC = VLED + VR + VR1

= VLED + IF (R + R1 ) (VLED = 3.2 V for White Crystal LED)

 R + R1 = (VDC - VLED)/IF
= 1.8 V/20 mA
= 90 Ω (You may use any value of R & R1 whose sum is equal or greater than this
minimum value of R + R1 )
For example use both R = R1 = 100 Ω

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NOT Gate
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation.
An inverter circuit outputs a voltage representing the opposite logic-level to its input. The
inverter is a basic building block in digital electronics. Multiplexers, decoders, state
machines, and other sophisticated digital devices may use inverters .

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Apply different combinations of logical inputs on input terminals A & B.
3. Measure the corresponding logical output at the output terminal labeled as X.
i. One way to check output logic level is with the help of a Multi-Meter.
(Voltage range 0 V to 1.5 V will indicate Logic 0 while voltage range of 3.5 V
to 5 V will indicate Logic 1)
ii. Another way to check output logic level is to insert a Crystal LED in series
with the resistance R between terminal X(Collector) and Ground. (ON LED
will indicate Logic 1 and OFF LED will indicate Logic 0)
4. Record all possible input and output combinations in the table.

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Working:

1. When A = 0, Emitter-Base junction of Q is reverse biased and it is in cutoff condition.

IB = 0  IC = β IB = 0.
Apply KVL to output loop VCE = VCC - IC RC = VCC which is High so X = 1.
2. When A = 1, Emitter Base junction is forward biased and allows a large current through base
which is enough to drive the transistor in saturation region.
Ideally VCE(SAT) = 0 V but practically VCE(SAT) = 0.3 V which is low so X = 0.

Truth Table:

A X
0 1
1 0

Calculations:

For cut-off the mathematical conditions are given as:

VBE < 0.7 V which will ensure IB = 0  IC = β IB = 0

Now Apply KVL to output loop:

VCE = VCC - IC RC = VCC

For saturation the mathematical conditions are given as:

IB(MIN) >> IC(SAT)/ βDC

So we can choose IB(MIN) = 2IC(SAT)/ βDC

Where IC(SAT) = (VCC - VCE(SAT))/RC and IB(MIN) = (VCC – VBE )/RB and βDC = 100 (From data
sheet)

Now put VCC = 5 V, VCE(SAT) = 0.3 V and VBE = 0.7 V

We get 4.3/RB = 2(4.7)/100RC

 RB/RC = 457.5
 RB = 457.5 RC

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For example if we choose RC = 220 Ω then RB = 100 kΩ

In case of Crystal LED indicator we have to limit its forward current I F to 20 mA because it
can handle only this amount of forward current. So in this case we have to choose minimum
value of R by following procedure:

VCC = VLED + VR

= VLED + IFR (VLED = 3.2 V for White Crystal LED)

 R = (VCC - VLED)/IF
= 1.8 V/20 mA
= 90 Ω (You may use any value of R equal or greater than this value)
For example use R = 100 Ω

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Two Input NOR-Gate

The NOR gate is a digital logic gate that implements logical NOR. A HIGH output (1) results
if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output
(0) results. NOR is the result of the negation of the OR operator. It can also be seen as an
AND gate with all the inputs inverted. NOR is a functionally complete operation. NOR gates
can be combined to generate any other logical function. By contrast, the OR operator
is monotonic as it can only change LOW to HIGH but not vice versa .

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Apply different combinations of logical inputs on input terminals A & B.
3. Measure the corresponding logical output at the output terminal labeled as X.
i. One way to check output logic level is with the help of a Multi-Meter.
(Voltage range 0 V to 1.5 V will indicate Logic 0 while voltage range
of 3.5 V to 5 V will indicate Logic 1)

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ii. Another way to check output logic level is to insert a Crystal LED in
series with the resistance R1 between terminal Y (Collector) and
Ground. (ON LED will indicate Logic 1 and OFF LED will indicate
Logic 0)
4. Record all possible input and output combinations in the table.

Working:

1. When A = 0 and B = 0 then both the diodes are reverse biased there will be no current
through the load resistance R and voltage drop across load resistance R will be zero volt
which means X = 0, this will keep transistor in cutoff region so Y = 1.
2. When A = 0 and B = 1 then the D 1 is reverse biased and D 2 is forward biased, current will
pass through load resistance R and voltage drop across load resistance will be high which
means X = 1, this will drive transistor in saturation region so Y = 0.
3. When A = 1 and B = 0 then the D 1 is forward biased and D 2 is reverse biased, current will
pass through load resistance R and voltage drop across load resistance will be high which
means X = 1, this will drive transistor in saturation region so Y = 0.

4. When A = 1 and B = 1 then both the diodes are forward biased and current will pass through
the load resistance R and voltage drop across load resistance will be high which means X = 1,
this will drive transistor in saturation region so Y = 0.

Truth Table:

A B X Y
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

Calculations:

For initial half of circuit (Two Input OR-Gate)

We have choosen 1N4007 Silicon diodes which have a typical forward voltage of 0.7 V and
can handle an average forward current of 1 A.

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The output Logic level is obtained across the ¼ watt carbon film resistor so we have to be
careful in choosing its value.

In case of Logic 1 at output maximum value of Vout = 5 V

So we can choose minimum value of as

R = (Vout )2 /P

= (5)2 /0.25

= 100 Ω (You may use any value of R equal or greater than this minimum value)

For example use R = 220 Ω

For remaining half of circuit (NOT-Gate)

For cut-off the mathematical conditions are given as:

VBE < 0.7 V which will ensure IB = 0  IC = β IB = 0

Now Apply KVL to output loop:

VCE = VCC - IC RC = VCC

For saturation the mathematical conditions are given as:

IB(MIN) >> IC(SAT)/ βDC

So we can choose IB(MIN) = 2IC(SAT)/ βDC

Where IC(SAT) = (VCC - VCE(SAT))/RC and IB(MIN) = (VCC – VBE )/RB and βDC = 100 (From data
sheet)

Now put VCC = 5 V, VCE(SAT) = 0.3 V and VBE = 0.7 V

We get 4.3/RB = 2(4.7)/100RC

 RB/RC = 457.5
 RB = 457.5 RC

For example if we choose RC = 220 Ω then RB = 100 kΩ

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In case of Crystal LED indicator we have to limit its forward current I F to 20 mA because it
can handle only this amount of forward current. So in this case we have to choose minimum
value of R1 by following procedure:

VCC = VLED + VR1

= VLED + IFR1 (VLED = 3.2 V for White Crystal LED)

 R1 = (VCC - VLED)/IF
= 1.8 V/20 mA
= 90 Ω (You may use any value of R1 equal or greater than this value)
For example use R1 = 100 Ω

NOTE:

This circuit can be used for both OR gate and NOR gate.

The output X gives the status of OR gate while output Y gives the status of NOR gate.

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Two Input NAND-Gate

In digital electronics, a NAND gate (negative-OR) is a logic gate which produces an output
that is false only if all its inputs are true; thus its output is complement to that of the AND
gate. A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both
inputs are LOW (0), a HIGH (1) output results. The NAND gate is significant because
any Boolean function can be implemented by using a combination of NAND gates. This
property is called functional completeness. Digital systems employing certain logic circuits
take advantage of NAND's functional completeness.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Apply different combinations of logical inputs on input terminals A & B.
3. Measure the corresponding logical output at the output terminal labeled as X.

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i. One way to check output logic level is with the help of a Multi-Meter.
(Voltage range 0 V to 1.5 V will indicate Logic 0 while voltage range
of 3.5 V to 5 V will indicate Logic 1)
ii. Another way to check output logic level is to insert a Crystal LED in
series with the resistance R1 between terminal Y (Collector) and
Ground. (ON LED will indicate Logic 1 and OFF LED will indicate
Logic 0)
4. Record all possible input and output combinations in the table.

Working:

1. When A = 0 and B = 0 both diodes are forward biased and offer low resistance to current.
Current will pass through both diodes and will be grounded. Voltage at output terminal will
be 0.7 V which means X = 0, this will keep transistor in cutoff so Y = 1.
2. When A = 0 and B = 1 D2 is reverse biased and D 1 is forward biased and offer low resistance
to current. Current will pass through D 1 and will be grounded. Voltage at output terminal will
be 0.7 V which means X = 0, this will keep transistor in cutoff so Y = 1.
3. When A = 1 and B = 0 D1 is reverse biased and D 2 is forward biased and offer low resistance
to current. Current will pass through D 2 and will be grounded. Voltage at output terminal will
be 0.7 V which means X = 0, this will keep transistor in cutoff so Y = 1.

4. When A = 1 and B = 1 both diodes are reverse biased and offer high resistance to current.
Current will not pass through any of the diodes. Voltage at output terminal will be V CC which
means X = 1, this will drive transistor in saturation region so Y = 0.

Truth Table:
A B X Y
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

Calculations:

For initial half of circuit (Two Input OR-Gate)

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We have chooses 1N4007 Silicon diodes which have a typical forward voltage of 0.7 V and
can handle an average forward current of 1 A.

The output Logic level is obtained between terminal-X and ground so we have to be careful
in choosing the value of R which is connected between DC power supply and terminal-X.

In case of Logic 0 at output maximum value of VR = 5 V

So we can choose minimum value of as

R = (Vout )2 /P

= (5)2 /0.25

= 100 Ω (You may use any value of R equal or greater than this minimum value)

For remaining half of circuit (NOT-Gate)

For cut-off the mathematical conditions are given as:

VBE < 0.7 V which will ensure IB = 0  IC = β IB = 0

Now Apply KVL to output loop:

VCE = VCC - IC RC = VCC

For saturation the mathematical conditions are given as:

IB(MIN) >> IC(SAT)/ βDC

So we can choose IB(MIN) = 2IC(SAT)/ βDC

Where IC(SAT) = (VCC - VCE(SAT))/RC and IB(MIN) = (VCC – VBE )/RB and βDC = 100 (From data
sheet)

Now put VCC = 5 V, VCE(SAT) = 0.3 V and VBE = 0.7 V

We get 4.3/RB = 2(4.7)/100RC

 RB/RC = 457.5
 RB = 457.5 RC

For example if we choose RC = 220 Ω then RB = 100 kΩ

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In case of Crystal LED indicator we have to limit its forward current IF to 20 mA because it
can handle only this amount of forward current. So in this case we have to choose minimum
value of R1 by following procedure:

VCC = VLED + VR1

= VLED + IFR1 (VLED = 3.2 V for White Crystal LED)

 R1 = (VCC - VLED)/IF
= 1.8 V/20 mA
= 90 Ω (You may use any value of R1 equal or greater than this value)
For example use R1 = 100 Ω

NOTE:

This circuit can be used for both AND gate and NOT gate.

The output X gives the status of AND gate and output Y gives the status of NAND gate.

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Practical No. 2

(a) Design and study different parameters of

full wave bridge rectifier i.e. VP(out) and
VDC.
(b) Study the effect of Capacitor filter on
output of full wave bridge rectifier by
calculating different parameters i.e.
VP(rect), VDC, Vγ(pp) and γ.

Apparatus:
1. 1N4007 Diodes
2. 1/4 Watt Carbon film Resistors
3. Electrolytic Capacitors
4. Connecting Wires
5. Transformer
6. Cathode Ray Oscilloscope (CRO)
7. Digital Multi-Meter (DMM)

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Full Wave Bridge Rectifier

A diode bridge is an arrangement of four diodes in a bridge circuit configuration that
provides the same polarity of output for either polarity of input. When used in its most
common application, for conversion of an alternating current (AC) input into a direct
current (DC) output, it is known as a bridge rectifier. A bridge rectifier provides full-wave
rectification from a two-wire AC input, resulting in lower cost and weight as compared to a
rectifier with a 3-wire input from a transformer with a center-tapped secondary winding. The
essential feature of a diode bridge is that the polarity of the output is the same regardless of
the polarity at the input.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Turn on the power switch and apply the different input voltages on specified terminals
from transformer.
3. Observe the shape of output voltage on CRO.
4. Measure and record the peak value of output voltage by adjusting the knob of relevant
CRO channel to a suitable value.

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5. Measure and record the average value of output voltage by using a DMM at output
terminals.
6. Record at least three different readings in the table.

Working:

1. During the positive half cycle of the input voltage, the diodes D1 and D3 are forward
biased and conduct current into the load.
2. During the negative half cycle of the input voltage, the diodes D2 and D4 are forward
biased and conduct current into the load.
3. The peak value of output voltage is 1.4 V less than the peak values of the input
voltage due to 0.7 V drop across each forward biased silicon diode.

Measurements and Calculations:

Theoretical:

Sr. No. VP(in) VP(out) = VP(in) – 1.4 VDC = 2 VP(out)/π

V V V
1 3 1.6 1.02
2 6 4.6 2.93
3 9 7.6 4.84

Practical:

Sr. No. VP(in) VP(out) (By CRO) VDC (By DMM)

V V V
1 3
2 6
3 9

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Error Measurement:

VP(out) %age Error VDC %age Error

Sr. No. V V
Theoretical Practical x 100% Theoretical Practical x 100%
T P T P
1
2
3

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Full Wave Bridge Rectifier

(With Capacitor Filter)
We saw in the previous section that the full-wave bridge rectifier gives us a greater mean DC
value (0.637 Vmax ) with less superimposed ripple while the output waveform is twice that of
the frequency of the input supply frequency. We can therefore increase its average DC output
level even higher by connecting a suitable smoothing capacitor across the output of the bridge
circuit. The smoothing capacitor converts the full-wave rippled output of the rectifier into a
smooth DC output voltage. Generally for DC power supply circuits the smoothing capacitor
is an Aluminum Electrolytic type that has a capacitance value of 100µF or more with
repeated DC voltage pulses from the rectifier charging up the capacitor to peak voltage.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given in the figure 1 above.
2. Turn on the power switch and apply the different input voltages on specified
terminals from transformer.
3. Observe the shape of output voltage on CRO.
4. Measure and record the peak value of output voltage by adjusting the knob of
relevant CRO channel to a suitable value.

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5. Measure and record the peak to peak ripple voltage value by adjusting the knob of
relevant CRO channel to a suitable value.
6. Measure and record the average value of output voltage by using a DMM at
output terminals.
7. Record at least three different readings in the table.

Working:

1. During the positive half quarter of the input voltage, the diodes D1 and D3 are
forward biased and conduct current and capacitor C charges.
2. During the remaining cycle of the input voltage and a small portion of the next
cycle, the capacitor discharges through the load resistance R.
3. The Capacitor charges again when input voltage exceeds the capacitor voltage
by 1.4 V and this process continues for indefinite time until input power is
switched off.

Measurements and Calculations:

Load resistance = R = 10 KΩ

Filter Capacitor = C = 470 µF

Input frequency = f = 50 Hz

Theoretical:

Sr. No. VP(in) VP(rect)=VP(in)–1.4 V ( pp )

VDC =(1- ) VP(rect) Vγ(pp) = VP(rect)
V V  
VDC
V V

1 3 1.6 1.6 0.007 0.44 %

2 6 4.6 4.59 0.02 0.44 %
3 9 7.6 7.58 0.03 0.40 %

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Practical:
Sr. No. VP(in) VP(rect) (By CRO) VDC ( By DMM) Vγ(pp) (By CRO) γ = Vγ(pp)/VDC
V V V V

1 3
2 6
3 9

Error Measurement:

Sr. No. VP(rect) %age Error VDC %age Error

V V
Theoretical Practical x 100% Theoretical Practical x 100%
T P T P
1
2
3
Sr. No. Vγ(pp) %age Error γ %age Error
V
Theoretical Practical x 100% Theoretical Practical x 100%
T P T P
1
2
3

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Practical No.3

Design a Common Emitter Voltage Amplifier

using NPN transistor with the following
specifications and data:

AV = 100

f = 1 kHz

βDC = βac = hfe = 100

hie = 1 kΩ

VCC = 9 V

Apparatus:
1. C945 Transistor (NPN)
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Cathode Ray Oscilloscope
6. Signal Generator (Oscillator)
7. Digital Multi-Meter
8. Connecting Wires

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Common Emitter Voltage Amplifier

In electronics, a common emitter amplifier is one of three basic single-stage bipolar junction
transistor (BJT) amplifier topologies, typically used as a voltage amplifier. In this circuit the
base terminal of the transistor serves as the input, the collector is the output, and the emitter
is common to both (for example, it may be tied to ground reference or a power supply rail),
hence its name.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Apply a small input voltage of known value 1 kHz frequency from the oscillator.
4. Measure and record the output voltage by connecting the probe of the CRO at the
output terminal.
5. Record at least three readings in the table.
6. Calculate the average voltage gain.
7. Calculate the error in voltage gain.

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Working:

1. Upon applying the DC biasing battery the transistor Q-Point is established in active
region where its base, collector and emitter currents and voltages are fixed at their
nominal values according to the design.
2. When a small AC-Voltage of sinusoidal shape is applied capacitively at the base of
the transistor, it increases and decreases the fixed base voltage.
3. As a result of change in base voltage, base current also changes correspondingly.
4. Changes in base current produce a proportional change in collector current.
5. Change in collector current produces an opposite change in collector voltage and an
amplified plus 180o out of phase voltage signal is achieved at the output terminal of
the amplifier.

Design:

Stable DC biasing plays an important role in working of the transistor. A mid biased
transistor always operates as a reasonably good voltage amplifier because it always remains
in active region during the positive and negative excursions of the ac input cycle.

That’s why we will design CE-Amplifier with voltage divider biasing because it gives us a
stable Q-point even if there is a large change in operating conditions.

Another advantage is that we can bias both input and output with the help of a single battery
by the use of voltage divider configuration.

Calculation of R C:

The voltage gain of CE amplifier is given by the equation

AV = hfe RC/hie

100 = 100 RC/1000

 RC = 1000 Ω = 1 kΩ (Available in lab)

Calculation of R 2:

As R2 is in parallel with the input impedance of the CE-Amplifier

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And for stiff voltage divider bias we have to choose R2 >> Zin so that input voltage source is
not loaded.

We choose R2 = 10 hie ( Zin ≈ hie )

So R2 = 10 kΩ

I2 = VB / R2

= 1.6 V/10 kΩ

= 0.16 mA

Calculation of IC & IB:

Generally, the quiescent Q-point of the amplifier is with zero input-signal applied to the Base,
so the Collector sits half-way along the load line between zero volts and the supply voltage
VCC i.e. (VCC/2).

RE is used to stabilize IC so we have to keep emitter at a very small voltage near the ground.

So we can choose

VE = VCC/10

= 9/10

= 0.9 V

VCE = (VCC + VE)/2

= (9 + 0.9)/2

= 4.95 V

VC = VCE + VE

= 4.95 + 0.9

= 5.85 V

Therefore, the Collector current at the Q-point of the amplifier will be given as:

IC = (VCC – VCE)/RC

= (9 – 4.95)/1000

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= 4.05 mA

So the base current is:

IB = IC/βDC

= 4.05 mA/100

= 40.5 µA

= 0.04 mA

Calculation of R 1:

I1 = IB + I2

= 0.04 + 0.16

= 0.20 mA

VB = VBE + VE

= 0.7 + 0.9

= 1.6 V

R1 = (VCC – VB)/I1

= 7.4 V /0.20 mA

= 37 kΩ (39 kΩ Available)

Calculation of R E:

As VE = IE RE

 RE = VE / IE

= 0.9 V/4.05 mA

= 222 Ω ( 220 Ω Available )

Calculation of Ci :

We have to choose C i such that it does not affect the AC-voltage reaching at the base (It is
used to block any DC part present in AC signal)

XCi << hie

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We can choose XCi = hie/10

1/XCi = 10/hie

2πfCi = 0.01

Ci = 0.01/(2 x 3.14 x 1000)

= 2 µF (10 µF Available)

Calculation of Co:

We have to choose C 0 such that it does not affect the AC-voltage at the load (It is used to
block any DC part present in AC signal)

XCo << RC

We can choose XCi = RC/10

1/XCo = 10/RC

2πfC0 = 0.01

C0 = 0.01/(2 x 3.14 x 1000)

= 2 µF (10 µF Available)

Calculation of CE:

We have to choose C E such that it effectively grounds the Emitter terminal (It is used to block
any DC part present in AC signal)

XCe << RE

We can choose XCe = RE/10

1/XCe = 10/RE

2πfCE = 0.045455

CE = 0.045455/(2 x 3.14 x 1000)

= 7 µF but we can use as large as 100 µF or greater for effective grounding of Emitter
terminal.

Observations And Measurements:

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Sr. No. Vin Vout AV= Vout/Vin

mV V

Theoretical Value of voltage gain = P =

Theoretical Value of Voltage gain = T = 100

Percentage Error = x 100 %

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Practical No.4
Design a Common Collector Voltage Amplifier
using NPN transistor with the following
specifications and data:

AV = 1

f = 1 kHz

βDC = βac = hfe = 100

hie = 1 kΩ

VCC = 9 V

IC = 3 mA
Apparatus:
1. C945 Transistor (NPN)
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Cathode Ray Oscilloscope
6. Signal Generator (Oscillator)
7. Digital Multi-Meter
8. Connecting Wires
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Common Collector Voltage Amplifier

In electronics, a common collector amplifier (also known as an emitter follower) is one of
three basic single-stage bipolar junction transistor (BJT) amplifier topologies, typically used
as a voltage buffer. In this circuit the base terminal of the transistor serves as the input, the
emitter is the output, and the collector is common to both (for example, it may be tied
to ground reference or a power supply rail), hence its name. The low output impedance
allows a source with a large output impedance to drive a small load impedance; it functions
as a voltage buffer. In other words, the circuit has current gain (which depends largely on the
hfe of the transistor) instead of voltage gain. A small change to the input current results in
much larger change in the output current supplied to the output load.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Apply a small input voltage of known value 1 kHz frequency from the oscillator.

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4. Measure and record the output voltage by connecting the probe of the CRO at the
output terminal.
5. Record at least three readings in the table.
6. Calculate the average voltage gain.
7. Calculate the error in voltage gain.

Working:

1. Upon applying the DC biasing battery the transistor Q-Point is established in

active region where its base, collector and emitter currents and voltages are fixed
at their nominal values according to the design.
2. When a small AC-Voltage of sinusoidal shape is applied capacitively at the base
of the transistor, it increases and decreases the fixed base voltage.
3. The output is replica of the input voltage because the output voltage is obtained at
emitter terminal in this and emitter is at 0.7 V below the base voltage. So we can
say output voltage at emitter follows the input base voltage.
4. There is no phase shift between input and output voltage.

Design:

Stable DC biasing plays an important role in working of the transistor. A mid biased
transistor always operates as a reasonably good voltage amplifier because it always remains
in active region during the positive and negative excursions of the ac input cycle.

That’s why we will design CC-Amplifier with voltage divider biasing because it gives us a
stable Q-point even if there is a large change in operating conditions.

Another advantage is that we can bias both input and output with the help of a single battery
by the use of voltage divider configuration.

Calculation of R E:

As Emitter is the output terminal so we have to keep it at VCC/2.

VE = VCC/2

= 9/2

= 4.5 V

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RE = VE/IE

= 4.5 V/3 mA

= 1.5 kΩ (Available in Lab)

Calculation of R 2:

As R2 is in parallel with the input impedance of the CC-Amplifier

And for stiff voltage divider bias we have to choose R2 >> Zin so that input voltage source is
not loaded.

We choose R2 = 10 hie (Zin ≈ hie)

So R2 = 10 kΩ

VB = VE + VBE

= 4.5 + 0.7

= 5.2 V

I2 = VB / R2

= 5.2 V/10 kΩ

= 0.52 mA

Calculation of IB:

The base current is:

IB = IC/βDC

= 3 mA/100

= 30 µA

= 0.03 mA

Calculation of R 1:

I1 = IB + I2

= 0.03 + 0.52

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= 0.55 mA

R1 = (VCC – VB)/I1

= 3.8 V /0.55 mA

= 6.9 kΩ (6.8 kΩ Available)

Calculation of Ci :

We have to choose C i such that it does not affect the AC-voltage reaching at the base (It is
used to block any DC part present in AC signal)

XCi << hie

We can choose XCi = hie/10

1/XCi = 10/hie

2πfCi = 0.01

Ci = 0.01/(2 x 3.14 x 1000)

= 2 µF (10 µF Available)

Calculation of Co:

We have to choose C 0 such that it does not affect the AC-voltage at the load (It is used to
block any DC part present in AC signal)

XCo << RE

We can choose XCo = RE/10

1/XCo = 10/RE

2πfC0 = 0.007

C0 = 0.007/(2 x 3.14 x 1000)

= 1 µF (Available in Lab)

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Observations And Measurements:

Sr. No. Vin Vout AV= Vout/Vin

mV mV

Theoretical Value of voltage gain = P =

Theoretical Value of Voltage gain = T = 1

Percentage Error = x 100 %

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Practical No.5
Design an Astable Multi-Vibrator using NPN
transistors with the following specifications and
data:

f = 100 Hz

T = 10 ms

βDC =100

VCC = 9 V

IC(sat) = 20 mA

DC = 50 %
Apparatus:
1. C945 Transistors (NPN)
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Cathode Ray Oscilloscope
6. Digital Multi-Meter
7. Connecting Wires
8. Light Emitting Diodes (LEDs)
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Astable Multi-Vibrator
The Astable Multi-Vibrator has automatic built in triggering which switches it continuously
between its two unstable states both set and reset. The Astable Multi-Vibrator is another type
of cross-coupled transistor switching circuit that has no stable output states as it changes from
one state to the other all the time. The Astable circuit consists of two switching transistors, a
cross-coupled feedback network, and two time delay capacitors which allow oscillation
between the two states with no external trigger signal to produce the change in state.
In Electronic Circuits, Astable multi-Vibrators are also known as Free-running Multi-
Vibrator as they do not require any additional inputs or external assistance to oscillate.
Astable oscillators produce a continuous square wave from its output or outputs, (two outputs
no inputs) which can then be used to flash lights or produce a sound in a loudspeaker.

Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.

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3. Observe the flashing LEDs D1 and D2 i.e. when D1 is on, D2 will be off and vice
versa.
4. Now connect the probe of CRO at collector terminal of Q1 or Q2 and observe the
waveform just like the square wave.
5. Measure the time period and frequency of this square wave by adjusting time sweep
to a suitable value.
6. Now connect the probe of CRO at base terminal of Q1 or Q2 and observe the
waveform.

Working:

1. When the circuit is switched on by plugging in the DC supply one of the transistors
will be driven to saturation (due to high value of β) and other will remain in cutoff
(due to low value of β).

2. Assume that transistor Q1 has just switched OFF and its collector voltage is rising
towards VCC, meanwhile transistor Q2 has just turned ON. Right plate of capacitor C2
(which is connected to base of Q1) starts charging towards VCC.

3. When this plate voltage rises to 0.7 V then Q1 turns ON because it emitter base
junction is forward biased due to this voltage. As Q1 turns ON, its collector voltage
drops from VCC to 0.

4. At the same time he differentiator circuit made by RB-C1 differentiates this negative
going voltage on collector of Q1. This negative swing cuts Q2 OFF and its collector
voltage rises from 0 to VCC.

5. Now Q1 is in ON state and Q2 is in OFF state.

6. Now C1 charges from –VCC to +VCC and when it reaches 0.7 V it turns Q2 ON again
and differentiator RB-C2 turns Q1 OFF.

7. This working continues for an indefinite time until the power supply is switched off.

Waveforms:

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Theoretical Calculations:

ON and OFF time of Q1 and Q2 is actually controlled by charging and discharging of C 1 &
C2 .

We have made a symmetric Astable Multi-Vibrator with the following assumptions:

Both capacitors are same  C1 = C2 = C

Both collector resistors are same  RC1 = RC2 = RC

Both base resistors are same  RB1 = RB2 = RB

These assumptions make ON and OFF time of both the transistors same.

So we calculate the ON and OFF time of Q1 and same are valid for Q2.

OFF time:

When Q1 is OFF then Capacitor C 1 is charging from –VCC to +VCC. The equation of charging
of capacitor is given as:

VC = Vinitial + (Vfinal – Vinitial)(1 – e-t/RBC)

Where VC = Average capacitor voltage = 0

Vinitial = -VCC

Vfinal = +VCC

t = TOFF

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0 = -VCC + [VCC – (-VCC)](1 – e-t/RBC)

0.5 = 1 – e-t/RBC

t = TOFF = 0.693 RBC

ON time:

When Q1 is ON then Capacitor C 2 is charging from –VCC to +VCC. The equation of charging
of capacitor is given as:

VC = Vinitial + (Vfinal – Vinitial)(1 – e-t/RBC)

Where VC = Average capacitor voltage = 0

Vinitial = -VCC

Vfinal = +VCC

t = TON

0 = -VCC + [VCC – (-VCC)](1 – e-t/RBC)

0.5 = 1 – e-t/RBC

t = TON = 0.693 RBC

Time Period:

T = TON + TOFF

= 0.693 RBC + 0.693 RBC

= 1.386 RBC

Frequency:

f = 1/T

= 1/1.386 RBC

= 0.72/RBC

Duty Cycle:

DC = TON/T

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Components Calculations:

Given that T = 10 ms

 TON = 0.5 T

 TON = TOFF = 0.5 T

 TON = TOFF = 5 ms

5 x 10-3 = 0.693 RB C Equation (1)

Calculation of R C:

We have to calculate component in order to drive Q1 and Q2 into saturation easily.

Apply KVL at output loop

VCC = VCE(sat) + IC(sat)RC

RC = (VCC - VCE(sat))/IC(sat)

= 435 Ω (470 Ω Available in lab)

Calculation of R B:

Apply KVL at input loop

VCC = VBE + IBRB

We choose IB = 10 IC(sat)/βDC

So IB = 2 mA

RB = (VCC – VBE)/IB

= 4.15 kΩ (4.7 kΩ Available in lab)

Calculation of C:

As we see equation (1)

5 x 10-3 = 0.693 RB C Equation (1)

C = 1.53 µF (2.2 µF Available in lab)

Approximations made:

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RB = 4.7 kΩ

RC = 470 Ω

C = 2.2 µF

Theoretical Value (T) Measured Value (P) Percentage Error

T = 1.386 R B C By CRO
x 100%
ms

14.33

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Practical No.6

Design a Monostable Multi-Vibrator using NPN

transistors with the following specifications and
data:

TW = 10 ms

βDC =100

VCC = 9 V

IC(sat) = 20 mA

Apparatus:
1. C945 Transistors (NPN)
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Cathode Ray Oscilloscope
6. Digital Multi-Meter
7. Connecting Wires
8. Light Emitting Diodes (LEDs)

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Monostable Multi-Vibrator
Multi-Vibrators are sequential regenerative circuits either synchronous or asynchronous and
are used extensively in electronic timing applications. Multi-Vibrators produce an output
wave shape resembling that of a symmetrical or asymmetrical square wave and as such are
the most commonly used of all the square wave generators. Monostable Multi-Vibrators have
only ONE stable state (hence their name: “Mono”), and produce a single output pulse when it
is triggered externally. Monostable Multi-Vibrators only return back to their first original and
stable state after a period of time determined by the time constant of the RC coupled circuit.
Monostable Multi-Vibrators or “One-Shot Multi-Vibrators” as they are also called are used to
generate a single output pulse of a specified width, either “HIGH” or “LOW” when a suitable
external trigger signal or pulse T is applied. This trigger signal initiates a timing cycle which
causes the output of the Monostable to change its state at the start of the timing cycle and will
remain in this second state. The timing cycle of the Monostable is determined by the time
constant of the timing capacitor, C and the resistor, R until it resets or returns itself back to its
original (stable) state. The Monostable Multi-Vibrator will then remain in this original stable
state indefinitely until another input pulse or trigger signal is received. Then, Monostable
Multi-Vibrators have only ONE stable state and go through a full cycle in response to a single
triggering input pulse. Monostable Multi-Vibrators can produce a very short pulse or a much
longer rectangular shaped waveform whose leading edge rises in time with the externally
applied trigger pulse and whose trailing edge is dependent upon the RC time constant of the
feedback components used. This RC time constant may be varied with time to produce a
series of pulses which have a controlled fixed time delay in relation to the original trigger
pulse.

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Circuit Diagram:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Observe the status of LEDs D1 and D2 i.e. if D1 is ON then D2 will be OFF. This
is the stable state of Monostable Multi-Vibrator.
4. Apply a single positive trigger at base of Q1 and observe the status of LEDs D1 &
D2. You will see that the LED which was previously ON will turn off and the
LED which was previously OFF will turn on. This is unstable state of Monostable
Multi-Vibrator. But this will happen for very short time and the LEDs will return
to their original stable state.
5. To measure the time for which this Multi-Vibrator went into its unstable state, we
have to apply a recurring (square wave type) trigger signal at base of Q1 which
will take Monostable Multi-Vibrator into its unstable state at each trigger. Keep in
mind that the Time period of applied trigger voltage should be at least 10 times
greater than the pulse width TW of unstable state for normal operation.

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6. Attach the probe of CRO to the collector of Q2 and observe the HIGH pulse width
by adjusting time sweep to a suitable point.

Working:

1. When power is firstly applied, the base of transistor Q2 is connected to VCC via the
biasing resistor, R thereby turning the transistor “fully-ON” and into saturation and at
the same time turning Q1 “OFF” in the process. This then represents the circuits
“Stable State” with zero output.

2. If a positive trigger pulse is now applied at the input, the fast decaying edge of the
pulse will pass straight through capacitor, C1 to the base of transistor, Q1 via the
blocking diode turning it “ON”. The collector of Q1 which was previously
at VCC drops quickly to below zero volts effectively giving capacitor C a reverse
charge of -VCC across its plates.

3. This action results in transistor Q2 now having a minus base voltage at

point X holding the transistor fully “OFF”. This then represents the circuit’s second
state, the “Unstable State” with an output voltage equal to VCC.

4. Timing capacitor, C begins to discharge this -VCC through the timing resistor R,
attempting to charge up to the supply voltage VCC. This negative voltage at the base of
transistor Q2 begins to decrease gradually at a rate determined by the time constant of
the RC combination.

5. As the base voltage of Q2 increases back up to VCC, the transistor begins to conduct
and doing so turns “OFF” again transistor Q1 which results in the Monostable Multi-
Vibrator automatically returning back to its original stable state awaiting a second
negative trigger pulse to restart the process once again.
Waveforms:

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Theoretical Calculations:

Both collector resistors are same  RC1 = RC2 = RC

Pulse Width:

When trigger is applied at base of Q1 it makes it ON and takes Q2 in OFF state.

The Capacitor C starts charging from –VCC to +VCC. The equation of charging of capacitor is
given as:

VC = Vinitial + (Vfinal – Vinitial)(1 – e-t/RC)

Where VC = Average capacitor voltage = 0

Vinitial = -VCC

Vfinal = +VCC

t = TW

0 = -VCC + [VCC – (-VCC)](1 – e-t/RC)

0.5 = 1 – e-t/RC

t = TW = 0.693 RC

Components Calculations:

Given that TW = 10 ms

 10 x 10-3 = 0.693 RC Equation (1)

Calculation of R C:

We have to calculate component in order to drive Q1 and Q2 into saturation easily.

Apply KVL at output loop

VCC = VCE(sat) + IC(sat)RC

RC = (VCC - VCE(sat))/IC(sat)

= 435 Ω (470 Ω Available in lab)

Calculation of R B:

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Apply KVL at input loop

VCC = VBE + IBRB

We choose IB = 10 IC(sat)/βDC

So IB = 2 mA

RB = (VCC – VBE)/IB

= 4150 Ω (4.7 kΩ Available)

Calculation of C:

As we see equation (1)

10 x 10-3 = 0.693 RC Equation (1)

We can choose C = 1 µF because it is easily available in lab.

 R = 14.4 kΩ (15 kΩ Available in lab)

Calculation of frequency of trigger voltage & R 1C1 for trigger circuit:

TW = 10 ms

Trigger Time Period = T = 10TW = 100 ms

Trigger frequency = f = 0.1 kHz

So R1 C1 = T/10 = 10 ms

Choose C1 = 1 µF  R1 = 10 kΩ

Approximations made:

R = 15 kΩ

RC = 470 Ω

RB = 4.7 kΩ

C = 1 µF

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Observations:

Theoretical Value (T) Measured Value (P) Percentage Error

TW = 0.693 RC By CRO
x 100%
ms

10.4

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Practical No.7

Design Bi-stable Multi-Vibrator using NPN

transistors with the following specifications and
data:

βDC =100

VCC = 9 V

IC(sat) = 20 mA

Apparatus:
1. C945 Transistors (NPN)
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Digital Multi-Meter
6. Connecting Wires
7. Light Emitting Diodes (LEDs)

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Bi-stable Multi-Vibrator
The Bi-stable Multi-Vibrator is another type of two state device similar to the Monostable
Multi-Vibrator we looked at in the previous tutorial but the difference this time is that BOTH
states are stable. Bi-stable Multi-Vibrators have TWO stable states (hence the name: “Bi”
meaning two) and maintain a given output state indefinitely unless an external trigger is
applied forcing it to change state. The Bi-stable Multi-Vibrator can be switched over from
one stable state to the other by the application of an external trigger pulse thus; it requires two
external trigger pulses before it returns back to its original state. As Bi-stable Multi-Vibrators
have two stable states they are more commonly known as Latches and Flip-flops for use in
sequential type circuits. The discrete Bi-stable Multi-Vibrator is a two state non-regenerative
device constructed from two cross-coupled transistors operating as “ON-OFF” Transistor
Switches. In each of the two states, one of the transistors is cut-off while the other transistor
is in saturation; this means that the Bi-stable circuit is capable of remaining indefinitely in
either stable state. To change the Bi-stable over from one state to the other, the Bi-stable
circuit requires a suitable trigger pulse and to go through a full cycle, two triggering pulses,
one for each stage are required. Its more common name or term of “flip-flop” relates to the
actual operation of the device, as it “flips” into one logic state, remains there and then
changes or “flops” back into its first original state.
Circuit Diagram:

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Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Observe the status of LEDs D1 and D2 i.e. if D1 is ON then D2 will be OFF. This is
the first stable state of Bi-stable Multi-Vibrator. It will remain in this state for
indefinite time if power supply remains on and there is no trigger voltage applied to
this Multi-Vibrator.
4. Apply a single positive trigger at base of Q1 and observe the status of LEDs D1 &
D2. You will see that the LED which was previously ON will turn off and the LED
which was previously OFF will turn on. This is the second stable state of Bi-Stable
Multi-Vibrator. It will remain in this state for indefinite time if power supply remains
on and there is no trigger voltage applied to this Multi-Vibrator.
5. Apply a single positive trigger at base of Q2 and observe the status of LEDs D1 &
D2. You will see that the LED which was previously ON will turn off and the LED
which was previously OFF will turn on. This is again the first stable state of Bi-Stable
Multi-Vibrator.
6. Upon applying first trigger the Bi-stable Multi-Vibrator “Flips” to second stable state
and when another trigger is applied if “Flops” to its initial state. This is the reason we
also call it Flip-Flop.

Working:

1. When power is firstly applied, one of the transistors is driven to saturation due to its
high β value while the other remains in cutoff due to its low β value.

2. This is first stable state of Bi-Stable Multi-Vibrator.

3. Assume Q1 is OFF and Q2 is ON. LED D1 will be OFF while LED D2 will be ON.

4. Apply positive trigger on base of Q1, it will drive it to saturation turning it in ON state
from OFF state. Its collector voltage falls from VCC to zero which drives Q2 in OFF
state from ON state. Now LED D1 will be ON while LED D2 will be OFF.

5. Now positive trigger should be applied to base of Q2, which will bring the Bi-stable
Multi-Vibrator to its original state.

Theoretical Calculations:
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Both collector resistors are same  RC1 = RC2 = RC

Both base resistors are same  RB1 = RB2 = RB

Calculation of R C:

We have to calculate component in order to drive Q1 and Q2 into saturation easily.

Apply KVL at output loop

VCC = VCE(sat) + IC(sat)RC

RC = (VCC - VCE(sat))/IC(sat)

= 435 Ω (470 Ω Available in lab)

Calculation of R B:

Apply KVL at input loop

VCC = VBE + IBRB

We choose IB = 10 IC(sat)/βDC

So IB = 2 mA

RB = (VCC – VBE)/IB

= 4150 Ω ( 4.7 kΩ Available)

Approximations made:

RC = 470 Ω

RB = 4.7 kΩ

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Practical No.8

Design an inverting amplifier using Operational

Amplifier with the following specifications and
data:

+VCC = +4.5 V

-VCC = -4.5 V

f = 1 kHz

ACL(I) = -10

Apparatus:
1. LM741 IC
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Digital Multi-Meter
5. Connecting Wires
6. Signal Generator (Oscillator)
7. Cathode Ray Oscilloscope

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Inverting Amplifier
We know that the Open Loop Gain AOL of an operational amplifier can be very high, as much
as 1,000,000 (120dB) or more. However, this very high gain is of no real use to us as it
makes the amplifier both unstable and hard to control as the smallest of input signals, just a
few micro-volts would be enough to cause the output voltage to saturate and swing towards
one or the other of the voltage supply rails losing complete control of the output. As the open
loop DC gain of an Operational Amplifiers is extremely high we can therefore afford to lose
some of this high gain by connecting a suitable resistor across the amplifier from the output
terminal back to the inverting input terminal to both reduce and control the overall gain of the
amplifier. This then produces and effect known commonly as Negative Feedback, and thus
produces a very stable Operational Amplifier based system. Negative Feedback is the process
of “feeding back” a fraction of the output signal back to the input, but to make the feedback
negative, we must feed it back to the negative or “inverting input” terminal of the op-amp
using an external Feedback Resistor called R2 . This feedback connection between the output
and the inverting input terminal forces the differential input voltage towards zero. This effect
produces a closed loop circuit to the amplifier resulting in the gain of the amplifier now being
called its Closed-loop Gain. Then a closed-loop inverting amplifier uses negative feedback to
accurately control the overall gain of the amplifier, but at a cost in the reduction of the
amplifiers gain. This negative feedback results in the inverting input terminal having a
different signal on it than the actual input voltage as it will be the sum of the input voltage
plus the negative feedback voltage giving it the label or term of a Summing Point. We must
therefore separate the real input signal from the inverting input by using an Input Resistor R1 .
As we are not using the positive non-inverting input this is connected to a common ground or
zero voltage terminal as shown below, but the effect of this closed loop feedback circuit
results in the voltage potential at the inverting input being equal to that at the non-inverting
input producing a Virtual Earth summing point because it will be at the same potential as the
grounded reference input.

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Diagram:

Practical Implementation:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Apply a small input voltage of known value 1 kHz frequency from the oscillator.
4. Measure and record the output voltage by connecting the probe of the CRO at the
output terminal.
5. Record at least three readings in the table.

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6. Calculate the average voltage gain.

7. Calculate the error in voltage gain.

Working:

1. When AC input signal is applied, the output saturates to +VCC and –VCC on its
positive and negative half cycles.

2. A negative feedback resistor R2 feedbacks the output voltage to inverting terminal

which is virtually grounded.

3. Continuous feedback from output to inverting terminal reduces the potential

difference between the inverting and non-inverting terminal to such a low value that
the output voltage waveform is converted to sinusoidal waveform as the input voltage.

4. The voltage gain is controlled by the external resistors R2 and R1 .

Theoretical Calculations:

As the non-inverting terminal is grounded and Op-Amp is being used in feedback mode, the
inverting terminal is also grounded (virtually) because the open loop voltage gain is very high
and input impedance is also infinite.

The Current Iin = (Vin -V-)/Rin

The Current If = (V- - Vout )/Rf

As Iin = If

 Vout /Vin = ACL(I) = -Rf/Rin

In our practical implementation

Rf = R2

Rin = R1

Calculation of R 1:

As ACL(I) = -10

 -R2 /R1 = -10

 R2 = 10 R1

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We can choose R1 of any suitable value.

We choose R1 = 1 kΩ

Calculation of R 2:

As R2 = 10 R1

R2 = 10 kΩ

Conversion of +9 V battery into +4.5V & -4.5V:

As R = V2 /P

 R = (4.5)2 /0.25

 R = 81 Ω (use any value greater than this value)

We will use R = 1 kΩ

Observations and Measurements:

Sr. No. Vin Vout ACL(I)

mV V

1 10

2 20

3 50

Error Measurements:

Average voltage gain = P =

Theoretical voltage gain = T = 10

Percentage Error = x 100%

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Practical No.9

Design a non-inverting amplifier using

Operational Amplifier with the following
specifications and data:

+VCC = +4.5 V

-VCC = -4.5 V

f = 1 kHz

ACL(NI) = 11

Apparatus:
1. LM741 IC
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Digital Multi-Meter
5. Connecting Wires
6. Signal Generator (Oscillator)
7. Cathode Ray Oscilloscope

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Non-Inverting Amplifier
We know that the Open Loop Gain AOL of an operational amplifier can be very high, as much
as 1,000,000 (120dB) or more. However, this very high gain is of no real use to us as it
makes the amplifier both unstable and hard to control as the smallest of input signals, just a
few micro-volts would be enough to cause the output voltage to saturate and swing towards
one or the other of the voltage supply rails losing complete control of the output. As the open
loop DC gain of an Operational Amplifiers is extremely high we can therefore afford to lose
some of this high gain by connecting a suitable resistor across the amplifier from the output
terminal back to the inverting input terminal to both reduce and control the overall gain of the
amplifier. This then produces and effect known commonly as Negative Feedback, and thus
produces a very stable Operational Amplifier based system. Negative Feedback is the process
of “feeding back” a fraction of the output signal back to the input, but to make the feedback
negative, we must feed it back to the negative or “inverting input” terminal of the op-amp
using an external Feedback Resistor called R2 . This feedback connection between the output
and the inverting input terminal forces the differential input voltage towards zero. This effect
produces a closed loop circuit to the amplifier resulting in the gain of the amplifier now being
called its Closed-loop Gain. Then a closed-loop non-inverting amplifier uses negative
feedback to accurately control the overall gain of the amplifier, but at a cost in the reduction
of the amplifiers gain. As we are using non-inverting terminal as input so the output will be in
phase with the input.

Diagram:

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66 | P a g e

Practical Implementation:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Apply a small input voltage of known value 1 kHz frequency from the oscillator.
4. Measure and record the output voltage by connecting the probe of the CRO at the
output terminal.
5. Record at least three readings in the table.
6. Calculate the average voltage gain.
7. Calculate the error in voltage gain.

Working:

1. When AC input signal is applied, the output saturates to +VCC and –VCC on its
positive and negative half cycles.

2. A negative feedback resistor R2 feedbacks the output voltage to inverting terminal

which is virtually grounded.
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3. Continuous feedback from output to inverting terminal reduces the potential

difference between the inverting and non-inverting terminal to such a low value that
the output voltage waveform is converted to sinusoidal waveform as the input voltage.

4. The voltage gain is controlled by the external resistors R2 and R1 .

Theoretical Calculations:

The input voltage is applied at non-inverting terminal.

The output voltage is being fed back to inverting terminal by the external feedback resistor
Rf.

Vout = AOL (Vin - Vf )

Vf = B Vout

Where B = Rin / (Rin +Rf )

Vout = AOL Vin – AOL B Vout

ACL(NI) = Vout /Vin = AOL/(1+AOLB)

AOLB>>1 so we can neglect 1 in the denominator.

ACL(NI) = Vout /Vin = 1/B

ACL(NI) = Vout /Vin = 1 +

In our practical implementation

Rf = R2

Rin = R1

Calculation of R 1:

As ACL(NI) = 11

 1+ R2 /R1 = 11

 R2 = 10 R1

We can choose R1 of any suitable value.

We choose R1 = 1 kΩ

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Calculation of R 2:

As R2 = 10 R1

R2 = 10 kΩ

Conversion of +9 V battery into +4.5V & -4.5V:

As R = V2 /P

 R = (4.5)2 /0.25

 R = 81 Ω (use any value greater than this value)

We will use R = 1 kΩ

Observations and Measurements:

Sr. No. Vin Vout ACL(NI)

mV V

1 10

2 20

3 50

Error Measurements:

Average voltage gain = P =

Theoretical voltage gain = T = 11

Percentage Error = x 100%

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Practical No.10

Design a voltage follower using Operational

Amplifier with the following specifications and
data:

+VCC = +4.5 V

-VCC = -4.5 V

f = 1 kHz

ACL(VF) = 1

Apparatus:
1. LM741 IC
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Digital Multi-Meter
5. Connecting Wires
6. Signal Generator (Oscillator)
7. Cathode Ray Oscilloscope

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Voltage Follower
If we made the feedback resistor, Rƒ equal to zero, (Rƒ = 0), and resistor R2 equal to infinity,
(R2 = ∞), then the circuit would have a fixed gain of “1” as all the output voltage would be
present on the inverting input terminal (negative feedback). This would then produce a
special type of the non-inverting amplifier circuit called a Voltage Follower or also called a
“unity gain buffer”. As the input signal is connected directly to the non-inverting input of the
amplifier the output signal is not inverted resulting in the output voltage being equal to the
input voltage, Vout = Vin. This then makes the voltage follower circuit ideal as a Unity Gain
Buffer circuit because of its isolation properties. The advantage of the unity gain voltage
follower is that it can be used when impedance matching or circuit isolation is more
important than amplification as it maintains the signal voltage. The input impedance of the
voltage follower circuit is very high, typically above 1MΩ as it is equal to that of the
operational amplifiers input resistance times its gain ( Rin x AOL ). Also its output impedance
is very low since an ideal op-amp condition is assumed.

Diagram:

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Practical Implementation:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Apply a small input voltage of known value 1 kHz frequency from the oscillator.
4. Measure and record the output voltage by connecting the probe of the CRO at the
output terminal.
5. Record at least three readings in the table.
6. Calculate the average voltage gain.
7. Calculate the error in voltage gain.

Working:

1. When AC input signal is applied, the output saturates to +VCC and –VCC on its
positive and negative half cycles.

2. A wire feeds the output voltage to inverting terminal.

3. Continuous feedback from output to inverting terminal reduces the potential

difference between the inverting and non-inverting terminal to such a low value that
the output voltage waveform is converted to sinusoidal waveform as the input voltage.

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Theoretical Calculations:

The input voltage is applied at non-inverting terminal.

The output voltage is being fed back to inverting terminal by the external feedback resistor
Rf.

Vout = AOL ( Vin - Vf )

Vf = B Vout

Where B = Rin / ( Rin +Rf )

Vout = AOL Vin – AOL B Vout

ACL(NI) = Vout /Vin = AOL/(1+AOLB)

AOLB>>1 so we can neglect 1 in the denominator.

ACL(NI) = Vout /Vin = 1/B

ACL(NI) = Vout /Vin = 1 +

In our practical implementation

Rf = R2

Rin = R1

We want to make it Unity Follower so

ACL(VF) = 1

Calculation of R 2 & R1:

As ACL(VF) = 1

 1+ R2 /R1 = 1

 R2 / R1 = 0

So there are following two possibilities:

Rf = R2 = 0

Rin = R1 = ∞

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Conversion of +9 V battery into +4.5V & -4.5V:

As R = V2 /P

 R = (4.5)2 /0.25

 R = 81 Ω (use any value greater than this value)

We will use R = 1 kΩ

Observations and Measurements:

Sr. No. Vin Vout ACL(NI)

mV V

1 10

2 20

3 50

Error Measurements:

Average voltage gain = P =

Theoretical voltage gain = T = 1

Percentage Error = x 100%

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Practical No.11

Design a RC-Phase Shift Oscillator using

Operational Amplifier with the following
specifications and data:

+VCC = +4.5 V

-VCC = -4.5 V

f = 1 kHz

Apparatus:
1. LM741 IC
2. 9 Volt DC Power Supply
3. 1/4 Watt Carbon Film Resistors
4. Electrolytic Capacitors
5. Digital Multi-Meter
6. Connecting Wires
7. Cathode Ray Oscilloscope

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RC-Phase Shift Oscillator

The basic RC Oscillator which is also known as a Phase-shift Oscillator, produces a sine
wave output signal using regenerative feedback obtained from the resistor-capacitor
combination. This regenerative feedback from the RC network is due to the ability of the
capacitor to store an electric charge, (similar to the LC tank circuit). This resistor-capacitor
feedback network can be connected as shown above to produce a leading phase shift (phase
advance network) or interchanged to produce a lagging phase shift (phase retard network) the
outcome is still the same as the sine wave oscillations only occur at the frequency at which
the overall phase-shift is 360o . By varying one or more of the resistors or capacitors in the
phase-shift network, the frequency can be varied and generally this is done by keeping the
resistors the same and using a 3-ganged variable capacitor.

Since the resistor-capacitor combination in the RC Oscillator circuit also acts as an attenuator
producing an attenuation of -1/29th ( Vo/Vi = β ) per stage, the gain of the amplifier must be
sufficient to overcome the circuit losses. Therefore, in our three stage RC network above the
amplifier gain must be greater than 29.

The loading effect of the amplifier on the feedback network has an effect on the frequency of
oscillations and can cause the oscillator frequency to be up to 25% higher than calculated.
Then the feedback network should be driven from a high impedance output source and fed
into a low impedance load such as a common emitter transistor amplifier but better still is to
use an Operational Amplifier as it satisfies these conditions perfectly.

Diagram:

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Practical Implementation:

Procedure:

1. Connect the circuit according to the circuit diagram given above in figure 1.
2. Plug in the DC biasing battery.
3. Touch the probe of CRO to the output terminal of Op-Amp pin 6.
4. Observe the output waveform in sinusoidal form.
5. Measure and record its frequency by adjusting time sweep to a suitable point.
6. Calculate the error in frequency.

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Working:

For an oscillator to sustain oscillations indefinitely, sufficient feedback of the correct phase,
ie, “Positive Feedback” must be provided with the amplifier being used as one inverting stage
to achieve this. In an RC Oscillator circuit the input is shifted 180o through the amplifier
stage and 180o again through a second inverting stage giving us “180o + 180o = 360o ” of
phase shift which is effectively the same as 0 o thereby giving us the required positive
feedback. In other words, the phase shift of the feedback loop should be “0”.

1. Operational amplifier provides voltage gain of 29 to week feedback signal.

2. It also provides 180o phase shift because it is in inverting amplifier configuration.

3. After taking gain from the amplifier, the signal is attenuated 29 times by the feedback
network which consists of three RC circuits working as high pass filters.

4. This feedback circuit also provides 180o phase shift to this signal.

5. Thus both the conditions of oscillator are fulfilled i.e. loop gain is unity and phase
shift around the loop is 1.

Theoretical Calculations:

For symmetric circuit, we have assumed R1 = R2 = R3 = R (say)

C1 = C2 = C3 = C (say)

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We have to calculate attenuation factor of the RC feedback network and the resonance
frequency of the oscillator. Only one frequency will satisfy the condition of sinusoidal
oscillator.

The input to this feedback network is output of amplifier Vout and output of this feedback
ntwork is feedback signal voltage Vf.

We have to calculate B = Vf/Vout

For this reason we have to solve this RC network using loop analysis.

Assume current I1 , I2 and I3 in three loops from left to right respectively.

Vf = I3 R

Converting this circuit to matrix form and then solving for I3 is easy.

Capacitor will be represented by its impedance ZC = -jXC where –j represents complex

variable iota representing a phase shift of 90o .

 R  jX C R 0   I1  Vout 
   0 
 R 2 R  jX C R  I2  =  
 0 R 2 R  jX C   I 3   0 


I3 = |D3 |/|D|

Where

 R  jX C R 0 
 
D =  R 2 R  jX C R 
 0 R 2 R  jX C 


 R  jX C R Vout 
 
D3 =   R 2 R  jX C 0 
 0 R 0 


|D3 | = R2 (Vout )

1
|D| =
( R  5RX )  j (6 R 2 X C  X C3 )
3 2
C

Vout R3
Vf =
( R3  5RX C2 )  j (6 R 2 X C  X C3 )

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R3
B = Vf/Vout =
( R3  5RX C2 )  j (6 R 2 X C  X C3 )

It will be real if its complex part is zero so for real B

6R 2 X C  X C3 = 0

1
 f 
2 6 RC

 B = -1/29

A B = 1  A = -29

A = gain of inverting amplifier = -Rf/R

Calculation of R, Rf & C:

Given f = 1000 Hz

We know that

1
f 
2 6 RC

We may choose C = 1 µF as it is easily available in the lab.

So we get R = 65 Ω ( Use 100 Ω which is available in lab)

Rf = 29 R

= 2.9 kΩ ( Use 3.3 kΩ in order to compensate losses in the circuit)

Conversion of +9 V battery into +4.5V & -4.5V:

As R = V2 /P

 R = (4.5)2 /0.25

 R = 81 Ω (use any value greater than this value)

We will use R = 1 kΩ

Approximations:

R = 100 Ω

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Rf = 3.3 kΩ

So now theoretical frequency = 650 Hz

Error Measurements:

Frequency observed by CRO = P =

Theoretical Frequency set = T = 650 Hz

Percentage Error = x 100%

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