1.
Question 1:
Translation Explanation
1. Line 1: addi x30, x10, 8
o This instruction adds the value 8 to the value in register x10, and stores the
result in register x30.
x30 = A + 8;
2. Line 2: addi x31, x10, 0
o This instruction simply copies the value in x10 into register x31 by adding 0 to
x10.
x31 = A;
3. Line 3: sd x31, 0(x30)
o This instruction stores the value in x31 (which holds the base address of array
A) into the memory location at the address in x30 (which is A + 8).
A[1] = (long)A;
4. Line 4: ld x30, 0(x30)
o This instruction loads the value from the memory location at the address in x30
(which is A + 8) into x30.
x30 = A[1];
5. Line 5: add x5, x30, x31
o This instruction adds the values in registers x30 and x31 and stores the result in
x5.
x5 = (long)A + (long)A;
C code:
long* A;
long* B;
long f, g, h, i, j;
x30 = A + 8;
x31 = A;
A[1] = (long)A;
x30 = A[1];
f = (long)A + (long)A;
2.Question2:.
Line 1:
Imm Rs1 Funct3 rd opcode
8 10 000 30 00100011
Line 2:
Imm Rs1 Funct3 rd opcode
0 10 000 31 00100011
Line 3:
Imm[11:5] Rs2 Rs1 Funct3 Imm[4:0] opcode
00000000 31 30 011 0000 0100011
Line 4:
Imm[11:5] Rs1 Rd Funct3 Imm[4:0] opcode
00000000 30 30 010 0000 0000011
Line 5:
Funct7 Rs2 Rs1 Funct3 rd opcode
00000000 31 30 000 5 0110011
3.Question 3:
a. add x30, x5, x6
x5 = 0x8000000000000000 → Signed value = -9223372036854775808 (negative number)
x6 = 0xD000000000000000 → Signed value = -1152921504606846976 (negative number)
Now, adding them:
−9223372036854775808+(−1152921504606846976)=−10388263521355484864
Thus, x30 = 0xC800000000000000.
b. An overflow has occurred because the result exceeds the representable
range of a 64-bit signed integer.
c. sub x30, x5, x6
o x5 = 0x8000000000000000 → -9223372036854775808 (signed value)
o x6 = 0xD000000000000000 → -1152921504606846976 (signed value)
−9223372036854775808−(−1152921504606846976=−8070450532247928832
Convert the result back to hexadecimal:
Result = 0xF800000000000000
Thus, x30 = 0xF800000000000000.
d. Result = -8070450532247928832 (in decimal) is within the range of a 64-bit
signed integer.
Therefore, there has been no overflow, and the result is as expected.
e.
o x5 = 0x8000000000000000 → -9223372036854775808
o x6 = 0xD000000000000000 → -1152921504606846976
The result of the first addition (from part a) is:
o x30 = 0xC800000000000000 (i.e., -10388263521355484864)(Overflow already)
The second add instruction adds x30 and x5:
o x30 = 0xC800000000000000 → -10388263521355484864
o x5 = 0x8000000000000000 → -9223372036854775808
Now, adding:
−10388263521355484864+(−9223372036854775808)=− 19611635958110260672
Convert the result back to hexadecimal:
o Result = 0x8800000000000000
Thus, x30 = 0x8800000000000000.
f. An overflow has occurred because the result exceeds the representable range
of a 64-bit signed integer.
4.Question 4:
Decoding the Binary:
In RISC-V, the binary value 0000 0000 0001 0000 1000 0000 1011 0011 corresponds to a 32-
bit instruction. Let's decode it according to the RISC-V instruction format.
The opcode 0110011 corresponds to the R-type instruction format in RISC-V.
Decode the R-type fields
For R-type instructions, the fields are:
funct7 (bits [31:25]): 0000000
rs2 (bits [24:20]): 00001 (1 in decimal)
rs1 (bits [19:15]): 00001 (1 in decimal)
funct3 (bits [14:12]): 000
rd (bits [11:7]): 00001 (1 in decimal)
opcode (bits [6:0]): 0110011
This combination corresponds to the ADD instruction in RISC-V.
Assembly Language Instruction:
The assembly language instruction for this binary value is: add x1, x1, x1
5.Question 5:
Instruction: sd x5, 32(x30) (S-Type)
The S-type format in RISC-V is used for store instructions (e.g., sd for storing a doubleword). The
fields are structured as follow
imm[11:5] (7 bits) rs2 (5 bits) rs1 (5 bits) funct3 (3 bits) imm[4:0] (5 bits) opcode (7 bits)
Identify the Fields
1. rs1 (Base Register): x30
2. rs2 (Source Register): x5
3. Immediate (Offset): 32
4. opcode: 0100011
5. funct3: 011
Encode the Immediate Value
The immediate value 32 is split into two parts in the S-type format:
imm[11:5]: Upper 7 bits of the immediate.
imm[4:0]: Lower 5 bits of the immediate.
The immediate value 32 in binary is:
32 (decimal) = 000000100000 (binary)
imm[11:5]: 0000001 (upper 7 bits)
imm[4:0]: 00000 (lower 5 bits)
Full Binary Encoding
Combining all the fields, the full 32-bit binary encoding for the instruction sd x5, 32(x30) is:
Copy
imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode
0000001 00101 11110 011 00000 0100011
Or, written as a continuous 32-bit binary value:
0000 0010 0101 1111 0011 0000 0010 0011
Which is written in hex: 0x025F3023
6.Question 6:
Identify the Instruction Type
The opcode 0x33 (0110011 in binary) corresponds to R-type instructions.
Match the Function Fields
funct7 = 0x20 (0100000 in binary)
funct3 = 0x0 (000 in binary)
For an R-type instruction, these fields define the operation. In RISC-V:
funct7 = 0100000
funct3 = 000
opcode = 0110011
This combination corresponds to the SUB (Subtract) instruction.
Step 3: Assign Register Values
rs1 = 7 → x7
rs2 = 5 → x5
rd = 6 → x6
Thus, the assembly instruction is:
SUB x6, x7, x5
Step 4: Construct the Binary Representation
R-type Format:
| funct7 | rs2 | rs1 | funct3 | rd | opcode |
| 0100000 | 00101 | 00111 | 000 | 00110 | 0110011 |
Final Answer
Instruction Type: R-type
Assembly Instruction: SUB x6, x7, x5
Binary Representation: 0100 0000 0101 0011 1000 0011 0011 0011
