ESP32

Technical Reference Manual Version 5.5

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About This Document
The ESP32 Technical Reference Manual is targeted at developers working on low level software projects that
use the ESP32 SoC. It describes the hardware modules listed below for the ESP32 SoC and other products in
ESP32 series. The modules detailed in this document provide an overview, list of features, hardware
architecture details, any necessary programming procedures, as well as register descriptions.

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Release Status at a Glance GoBack

Release Status at a Glance

No. Chapter Progress

Part I. Microprocessor and Master
1 ULP Coprocessor (ULP) Published
2 DMA Controller (DMA) Published
Part II. Memory Organization
3 System and Memory Published
4 Memory Management and Protection Units (MMU, MPU) Published
5 eFuse Controller Published
Part III. System Component
6 IO MUX and GPIO Matrix (GPIO, IO MUX) Published
7 Reset and Clock Published
8 Interrupt Matrix (INTERRUPT) Published
9 Low-Power Management (RTC_CNTL) Published
10 Timer Group (TIMG) Published
11 Watchdog Timers (WDT) Published
12 DPort Registers Published
13 Process ID Controller (PID) Published
Part IV. Cryptography/Security Component
14 AES Accelerator (AES) Published
15 RSA Accelerator (RSA) Published
16 SHA Accelerator (SHA) Published
17 External Memory Encryption and Decryption (FLASH) Published
18 Random Number Generator (RNG) Published
Part V. Connectivity Interface
19 UART Controller (UART) Published
20 SPI Controller (SPI) Published
21 I2C Controller (I2C) Published
22 I2S Controller (I2S) Published
23 Pulse Count Controller (PCNT) Published
24 Ethernet Media Access Controller (EMAC) Published
25 Two-Wire Automotive Interface (TWAI) Published
26 SDIO Slave Controller (SDIO) Published
27 SD/MMC Host Controller (SDHOST) Published
28 LED PWM Controller (LEDC) Published
29 Motor Control PWM (MCPWM) Published
30 Remote Control Peripheral (RMT) Published
Part VI. Analog Signal Processing
31 On-Chip Sensors and Analog Signal Processing Published

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Note:

Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/documentation/esp32_technical_reference_manual_en.pdf

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Contents

I Microprocessor and Master 28

1 ULP Coprocessor (ULP) 29

1.1 Introduction 29
1.2 Features 29
1.3 Functional Description 30
1.4 Instruction Set 30
1.4.1 ALU - Perform Arithmetic/Logic Operations 31
1.4.1.1 Operations Among Registers 31
1.4.1.2 Operations with Immediate Value 32
1.4.1.3 Operations with Stage Count Register 33
1.4.2 ST – Store Data in Memory 33
1.4.3 LD – Load Data from Memory 34
1.4.4 JUMP – Jump to an Absolute Address 35
1.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 35
1.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 36
1.4.7 HALT – End the Program 36
1.4.8 WAKE – Wake up the Chip 36
1.4.9 Sleep – Set the ULP Timer’s Wake-up Period 37
1.4.10 WAIT – Wait for a Number of Cycles 37
1.4.11 ADC – Take Measurement with ADC 37
1.4.12 I2C_RD/I2C_WR – Read/Write I2C 38
1.4.13 REG_RD – Read from Peripheral Register 39
1.4.14 REG_WR – Write to Peripheral Register 39
1.5 ULP Program Execution 40
1.6 RTC_I2C Controller 41
1.6.1 Configuring RTC_I2C 42
1.6.2 Using RTC_I2C 42
1.6.2.1 I2C_RD - Read a Single Byte 42
1.6.2.2 I2C_WR - Write a Single Byte 43
1.6.2.3 Detecting Error Conditions 43
1.6.2.4 Connecting I2C Signals 44
1.7 Register Summary 45
1.7.1 SENS_ULP Address Space 45
1.7.2 RTC_I2C Address Space 45
1.8 Registers 47
1.8.1 SENS_ULP Address Space 47
1.8.2 RTC_I2C Address Space 49

2 DMA Controller (DMA) 56

2.1 Overview 56
2.2 Features 56

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2.3 Functional Description 56

2.3.1 DMA Engine Architecture 57
2.3.2 Linked List 57
2.4 UART DMA (UDMA) 58
2.5 SPI DMA Interface 59
2.6 I2S DMA Interface 60

II Memory Organization 61

3 System and Memory 62

3.1 Introduction 62
3.2 Features 62
3.3 Functional Description 65
3.3.1 Address Mapping 65
3.3.2 Embedded Memory 65
3.3.2.1 Internal ROM 0 67
3.3.2.2 Internal ROM 1 67
3.3.2.3 Internal SRAM 0 67
3.3.2.4 Internal SRAM 1 68
3.3.2.5 Internal SRAM 2 68
3.3.2.6 DMA 69
3.3.2.7 RTC FAST Memory 69
3.3.2.8 RTC SLOW Memory 69
3.3.3 External Memory 69
3.3.4 Cache 70
3.3.5 Peripherals 71
3.3.5.1 Asymmetric PID Controller Peripheral 73
3.3.5.2 Non-Contiguous Peripheral Memory Ranges 73
3.3.5.3 Memory Speed 73

4 Memory Management and Protection Units (MMU, MPU) 74

4.1 Introduction 74
4.2 Features 74
4.3 Functional Description 74
4.3.1 PID Controller 74
4.3.2 MPU/MMU 75
4.3.2.1 Embedded Memory 75
4.3.2.2 External Memory 82
4.3.2.3 Peripheral 88

5 eFuse Controller 90
5.1 Introduction 90
5.2 Features 90
5.3 Functional Description 90
5.3.1 Structure 90
5.3.1.1 System Parameter efuse_wr_disable 92

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5.3.1.2 System Parameter efuse_rd_disable 92

5.3.1.3 System Parameter coding_scheme 93
5.3.1.4 BLK3_part_reserve 94
5.3.2 Programming of System Parameters 94
5.3.3 Software Reading of System Parameters 97
5.3.4 The Use of System Parameters by Hardware Modules 99
5.3.5 Interrupts 99
5.4 Register Summary 99
5.5 Registers 102

III System Component 113

6 IO MUX and GPIO Matrix (GPIO, IO MUX) 114

6.1 Overview 114
6.2 Peripheral Input via GPIO Matrix 116
6.2.1 Summary 116
6.2.2 Functional Description 116
6.2.3 Simple GPIO Input 117
6.3 Peripheral Output via GPIO Matrix 117
6.3.1 Summary 117
6.3.2 Functional Description 118
6.3.3 Simple GPIO Output 119
6.4 Direct I/O via IO MUX 119
6.4.1 Summary 119
6.4.2 Functional Description 119
6.5 RTC IO MUX for Low Power and Analog I/O 119
6.5.1 Summary 119
6.5.2 Analog Function Description 120
6.6 Light-sleep Mode Pin Functions 120
6.7 pin Hold Feature 120
6.8 I/O Pin Power Supplies 121
6.8.1 VDD_SDIO Power Domain 122
6.9 Peripheral Signal List 123
6.10 IO MUX Pin List 132
6.11 RTC_MUX Pin List 133
6.12 Register Summary 133
6.12.1 GPIO Matrix Register Summary 133
6.12.2 IO MUX Register Summary 135
6.12.3 RTC IO MUX Register Summary 136
6.13 Registers 137
6.13.1 GPIO Matrix Registers 137
6.13.2 IO MUX Registers 146
6.13.3 RTC IO MUX Registers 148

7 Reset and Clock 164

7.1 System Reset 164

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7.1.1 Introduction 164

7.1.2 Reset Source 164
7.2 System Clock 165
7.2.1 Introduction 165
7.2.2 Clock Source 166
7.2.3 CPU Clock 167
7.2.4 Peripheral Clock 167
7.2.4.1 APB_CLK 168
7.2.4.2 REF_TICK 168
7.2.4.3 LEDC_SCLK Source 168
7.2.4.4 APLL_SCLK Source 169
7.2.4.5 PLL_F160M_CLK Source 169
7.2.4.6 Clock Source Considerations 169
7.2.5 Wi-Fi BT Clock 169
7.2.6 RTC Clock 169
7.2.7 Audio PLL 169
7.3 Register Summary 170
7.4 Registers 171

8 Interrupt Matrix (INTERRUPT) 173

8.1 Overview 173
8.2 Features 173
8.3 Functional Description 173
8.3.1 Peripheral Interrupt Source 174
8.3.2 CPU Interrupt 177
8.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 177
8.3.4 CPU NMI Interrupt Mask 178
8.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 178
8.4 Registers 178

9 Low-Power Management (RTC_CNTL) 179

9.1 Introduction 179
9.2 Features 179
9.3 Functional Description 180
9.3.1 Overview 180
9.3.2 Digital Core Voltage Regulator 180
9.3.3 Low-Power Voltage Regulator 181
9.3.4 Flash Voltage Regulator 182
9.3.5 Brownout Detector 183
9.3.6 RTC Module 183
9.3.7 Low-Power Clocks 185
9.3.8 Power-Gating Implementation 187
9.3.9 Predefined Power Modes 188
9.3.10 Wakeup Source 189
9.3.11 Reject Sleep 190
9.3.12 RTC Timer 191

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9.3.13 RTC Boot 191

9.4 Register Summary 193
9.5 Registers 194

10 Timer Group (TIMG) 222

10.1 Introduction 222
10.2 Functional Description 222
10.2.1 16-bit Prescaler 222
10.2.2 64-bit Time-base Counter 222
10.2.3 Alarm Generation 223
10.2.4 MWDT 223
10.2.5 Interrupts 223
10.3 Register Summary 223
10.4 Registers 226

11 Watchdog Timers (WDT) 233

11.1 Introduction 233
11.2 Features 233
11.3 Functional Description 233
11.3.1 Clock 233
11.3.2 Operating Procedure 234
11.3.3 Write Protection 234
11.3.4 Flash Boot Protection 234
11.4 Registers 235

12 DPort Registers 236

12.1 Introduction 236
12.2 Features 236
12.3 Functional Description 236
12.3.1 System and Memory Register 236
12.3.2 Reset and Clock Registers 236
12.3.3 Interrupt Matrix Register 237
12.3.4 DMA Registers 237
12.3.5 MPU/MMU Registers 237
12.3.6 APP_CPU Controller Registers 237
12.3.7 Peripheral Clock Gating and Reset 237
12.4 Register Summary 238
12.5 Registers 244

13 Process ID Controller (PID) 270

13.1 Overview 270
13.2 Features 270
13.3 Functional Description 270
13.3.1 Interrupt Identification 270
13.3.2 Information Recording 271
13.3.3 Proactive Process Switching 272

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13.4 Register Summary 274

13.5 Registers 274

IV Cryptography/Security Component 279

14 AES Accelerator (AES) 280

14.1 Introduction 280
14.2 Features 280
14.3 Functional Description 280
14.3.1 AES Algorithm Operations 280
14.3.2 Key, Plaintext and Ciphertext 280
14.3.3 Endianness 281
14.3.4 Encryption and Decryption Operations 283
14.3.5 Speed 283
14.4 Register Summary 283
14.5 Registers 284

15 RSA Accelerator (RSA) 286

15.1 Introduction 286
15.2 Features 286
15.3 Functional Description 286
15.3.1 Initialization 286
15.3.2 Large Number Modular Exponentiation 286
15.3.3 Large Number Modular Multiplication 288
15.3.4 Large Number Multiplication 288
15.4 Register Summary 289
15.5 Registers 290

16 SHA Accelerator (SHA) 292

16.1 Introduction 292
16.2 Features 292
16.3 Functional Description 292
16.3.1 Padding and Parsing the Message 292
16.3.2 Message Digest 292
16.3.3 Hash Operation 293
16.3.4 Speed 293
16.4 Register Summary 294
16.5 Registers 296

17 External Memory Encryption and Decryption (FLASH) 302

17.1 Overview 302
17.2 Features 302
17.3 Functional Description 303
17.3.1 Key Generator 303
17.3.2 Flash Encryption Block 304
17.3.3 Flash Decryption Block 304

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17.4 Register Summary 305

17.5 Register 305

18 Random Number Generator (RNG) 307

18.1 Introduction 307
18.2 Feature 307
18.3 Functional Description 307
18.4 Programming Procedure 308
18.5 Register Summary 308
18.6 Register 308

V Connectivity Interface 309

19 UART Controller (UART) 310

19.1 Overview 310
19.2 UART Features 310
19.3 Functional Description 310
19.3.1 Introduction 310
19.3.2 UART Architecture 311
19.3.3 UART RAM 312
19.3.4 Baud Rate Detection 313
19.3.5 UART Data Frame 313
19.3.6 AT_CMD Character Structure 314
19.3.7 Flow Control 314
19.3.7.1 Hardware Flow Control 315
19.3.7.2 Software Flow Control 315
19.3.8 UART DMA 316
19.3.9 UART Interrupts 316
19.3.10 UHCI Interrupts 317
19.4 Register Summary 317
19.4.1 UART Register Summary 317
19.4.2 UHCI Register Summary 319
19.5 Registers 321
19.5.1 UART Registers 321
19.5.2 UHCI Registers 341

20 SPI Controller (SPI) 353

20.1 Overview 353
20.2 SPI Features 354
20.3 GP-SPI 354
20.3.1 GP-SPI Four-line Full-duplex Communication 355
20.3.2 GP-SPI Four-line Half-duplex Communication 355
20.3.3 GP-SPI Three-line Half-duplex Communication 356
20.3.4 GP-SPI Data Buffer 357
20.4 GP-SPI Clock Control 357
20.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 357

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20.4.2 GP-SPI Timing 359

20.5 Parallel QSPI 360
20.5.1 Communication Format of Parallel QSPI 360
20.6 GP-SPI Interrupt Hardware 361
20.6.1 SPI Interrupts 361
20.6.2 DMA Interrupts 361
20.7 Register Summary 362
20.8 Registers 365

21 I2C Controller (I2C) 388

21.1 Overview 388
21.2 Features 388
21.3 Functional Description 388
21.3.1 Introduction 388
21.3.2 Architecture 389
21.3.3 I2C Bus Timing 390
21.3.4 I2C cmd Structure 391
21.3.5 I2C Master Writes to Slave 392
21.3.6 Master Reads from Slave 396
21.3.7 Interrupts 398
21.4 Register Summary 400
21.5 Registers 402

22 I2S Controller (I2S) 414

22.1 Overview 414
22.2 Features 416
22.3 The Clock of I2S Module 416
22.4 I2S Mode 417
22.4.1 Supported Audio Standards 417
22.4.1.1 Philips Standard 418
22.4.1.2 MSB Alignment Standard 418
22.4.1.3 PCM Standard 418
22.4.2 Module Reset 419
22.4.3 FIFO Operation 419
22.4.4 Sending Data 419
22.4.5 Receiving Data 421
22.4.6 I2S Master/Slave Mode 423
22.4.7 I2S PDM 423
22.5 Camera-LCD Controller 425
22.5.1 LCD Master Transmitting Mode 425
22.5.2 Camera Slave Receiving Mode 426
22.5.3 ADC/DAC mode 427
22.6 I2S Interrupts 428
22.6.1 FIFO Interrupts 428
22.6.2 DMA Interrupts 429
22.7 Register Summary 429

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22.8 Registers 431

23 Pulse Count Controller (PCNT) 449

23.1 Overview 449
23.2 Functional Description 449
23.2.1 Architecture 450
23.2.2 Counter Channel Inputs 450
23.2.3 Watchpoints 451
23.2.4 Examples 452
23.2.5 Interrupts 452
23.3 Register Summary 453
23.4 Registers 454

24 Ethernet Media Access Controller (EMAC) 460

24.1 Overview 460
24.2 EMAC_CORE 462
24.2.1 Transmit Operation 462
24.2.1.1 Transmit Flow Control 463
24.2.1.2 Retransmission During a Collision 463
24.2.2 Receive Operation 463
24.2.2.1 Reception Protocol 464
24.2.2.2 Receive Frame Controller 464
24.2.2.3 Receive Flow Control 464
24.2.2.4 Reception of Multiple Frames 465
24.2.2.5 Error Handling 465
24.2.2.6 Receive Status Word 465
24.3 MAC Interrupt Controller 466
24.4 MAC Address Filtering 466
24.4.1 Unicast Destination Address Filtering 466
24.4.2 Multicast Destination Address Filtering 466
24.4.3 Broadcast Address Filtering 466
24.4.4 Unicast Source Address Filtering 466
24.4.5 Inverse Filtering Operation 467
24.4.6 Good Transmitted Frames and Received Frames 468
24.5 EMAC_MTL (MAC Transaction Layer) 469
24.6 PHY Interface 469
24.6.1 MII (Media Independent Interface) 469
24.6.1.1 Interface Signals Between MII and PHY 469
24.6.1.2 MII Clock 470
24.6.2 RMII (Reduced Media-Independent Interface) 471
24.6.2.1 RMII Interface Signal Description 471
24.6.2.2 RMII Clock 472
24.6.3 Station Management Agent (SMA) Interface 472
24.6.4 RMII Timing 472
24.7 Ethernet DMA Features 473
24.8 Linked List Descriptors 474

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24.8.1 Transmit Descriptors 474

24.8.2 Receive Descriptors 478
24.9 Register Summary 483
24.10 Registers 485

25 Two-Wire Automotive Interface (TWAI) 524

25.1 Overview 524
25.2 Features 524
25.3 Functional Protocol 525
25.3.1 TWAI Properties 525
25.3.2 TWAI Messages 526
25.3.2.1 Data Frames and Remote Frames 526
25.3.2.2 Error and Overload Frames 528
25.3.2.3 Interframe Space 530
25.3.3 TWAI Errors 530
25.3.3.1 Error Types 530
25.3.3.2 Error States 531
25.3.3.3 Error Counters 531
25.3.4 TWAI Bit Timing 532
25.3.4.1 Nominal Bit 532
25.3.4.2 Hard Synchronization and Resynchronization 533
25.4 Architectural Overview 533
25.4.1 Registers Block 534
25.4.2 Bit Stream Processor 535
25.4.3 Error Management Logic 535
25.4.4 Bit Timing Logic 535
25.4.5 Acceptance Filter 536
25.4.6 Receive FIFO 536
25.5 Functional Description 536
25.5.1 Modes 536
25.5.1.1 Reset Mode 536
25.5.1.2 Operation Mode 536
25.5.2 Bit Timing 537
25.5.3 Interrupt Management 537
25.5.3.1 Receive Interrupt (RXI) 538
25.5.3.2 Transmit Interrupt (TXI) 538
25.5.3.3 Error Warning Interrupt (EWI) 538
25.5.3.4 Data Overrun Interrupt (DOI) 539
25.5.3.5 Error Passive Interrupt (TXI) 539
25.5.3.6 Arbitration Lost Interrupt (ALI) 539
25.5.3.7 Bus Error Interrupt (BEI) 539
25.5.4 Transmit and Receive Buffers 539
25.5.4.1 Overview of Buffers 539
25.5.4.2 Frame Information 540
25.5.4.3 Frame Identifier 541
25.5.4.4 Frame Data 542

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25.5.5 Receive FIFO and Data Overruns 542

25.5.6 Acceptance Filter 542
25.5.6.1 Single Filter Mode 543
25.5.6.2 Dual FIlter Mode 544
25.5.7 Error Management 544
25.5.7.1 Error Warning Limit 544
25.5.7.2 Error Passive 545
25.5.7.3 Bus-Off and Bus-Off Recovery 545
25.5.8 Error Code Capture 546
25.5.9 Arbitration Lost Capture 547
25.6 Register Summary 548
25.7 Registers 549

26 SDIO Slave Controller (SDIO) 562

26.1 Overview 562
26.2 Features 562
26.3 Functional Description 562
26.3.1 SDIO Slave Block Diagram 562
26.3.2 Sending and Receiving Data on SDIO Bus 563
26.3.3 Register Access 564
26.3.4 DMA 564
26.3.5 Packet-Sending/-Receiving Procedure 565
26.3.5.1 Sending Packets to SDIO Host 565
26.3.5.2 Receiving Packets from SDIO Host 567
26.3.6 SDIO Bus Timing 568
26.3.7 Interrupt 569
26.3.7.1 Host Interrupt 569
26.3.7.2 Slave Interrupt 569
26.4 Register Summary 570
26.5 SLC Registers 572
26.6 SLC Host Registers 580
26.7 HINF Registers 594

27 SD/MMC Host Controller (SDHOST) 596

27.1 Overview 596
27.2 Features 596
27.3 SD/MMC External Interface Signals 597
27.4 Functional Description 597
27.4.1 SD/MMC Host Controller Architecture 597
27.4.1.1 BIU 598
27.4.1.2 CIU 598
27.4.2 Command Path 598
27.4.3 Data Path 599
27.4.3.1 Data Transmit Operation 599
27.4.3.2 Data Receive Operation 600
27.5 Software Restrictions for Proper CIU Operation 600

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27.6 RAM for Receiving and Sending Data 602

27.6.1 Transmit RAM Module 602
27.6.2 Receive RAM Module 602
27.7 Descriptor Chain 602
27.8 The Structure of a Linked List 602
27.9 Initialization 604
27.9.1 DMAC Initialization 605
27.9.2 DMAC Transmission Initialization 605
27.9.3 DMAC Reception Initialization 605
27.10 SD/MMC Timing 606
27.11 Clock Phase Selection 607
27.12 Interrupt 608
27.13 Register Summary 608
27.14 Registers 609

28 LED PWM Controller (LEDC) 628

28.1 Introduction 628
28.2 Functional Description 628
28.2.1 Architecture 628
28.2.2 Timers 629
28.2.3 Channels 630
28.2.4 Interrupts 632
28.3 Register Summary 632
28.4 Registers 636

29 Motor Control PWM (MCPWM) 646

29.1 Introduction 646
29.2 Features 646
29.3 Submodules 648
29.3.1 Overview 648
29.3.1.1 Prescaler Submodule 648
29.3.1.2 Timer Submodule 649
29.3.1.3 Operator Submodule 650
29.3.1.4 Fault Detection Submodule 651
29.3.1.5 Capture Submodule 652
29.3.2 PWM Timer Submodule 652
29.3.2.1 Configurations of the PWM Timer Submodule 652
29.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 652
29.3.2.3 PWM Timer Shadow Register 656
29.3.2.4 PWM Timer Synchronization and Phase Locking 657
29.3.3 PWM Operator Submodule 657
29.3.3.1 PWM Generator Submodule 657
29.3.3.2 Dead Time Generator Submodule 667
29.3.3.3 PWM Carrier Submodule 671
29.3.3.4 Fault Handler Submodule 674
29.3.4 Capture Submodule 675

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29.3.4.1 Introduction 675

29.3.4.2 Capture Timer 676
29.3.4.3 Capture Channel 676
29.4 Register Summary 676
29.5 Registers 679

30 Remote Control Peripheral (RMT) 726

30.1 Introduction 726
30.2 Functional Description 726
30.2.1 RMT Architecture 726
30.2.2 RMT RAM 726
30.2.3 Clock 728
30.2.4 Transmitter 728
30.2.5 Receiver 728
30.2.6 Interrupts 728
30.3 Register Summary 729
30.4 Registers 730

VI Analog Signal Processing 735

31 On-Chip Sensors and Analog Signal Processing 736

31.1 Introduction 736
31.2 Capacitive Touch Sensor 736
31.2.1 Introduction 736
31.2.2 Features 736
31.2.3 Available GPIOs 737
31.2.4 Functional Description 737
31.2.5 Touch FSM 738
31.3 SAR ADC 739
31.3.1 Introduction 739
31.3.2 Features 740
31.3.3 Outline of Function 740
31.3.4 RTC SAR ADC Controllers 742
31.3.5 DIG SAR ADC Controllers 742
31.4 DAC 744
31.4.1 Introduction 744
31.4.2 Features 744
31.4.3 Structure 745
31.4.4 Cosine Waveform Generator 745
31.4.5 DMA support 746
31.5 Register Summary 746
31.5.1 Sensors 746
31.5.2 Advanced Peripheral Bus 747
31.5.3 RTC I/O 748
31.6 Registers 749
31.6.1 Sensors 749

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31.6.2 Advanced Peripheral Bus 758

31.6.3 RTC I/O 762

VII Appendix 763

Related Documentation and Resources 764

Glossary 765
Abbreviations for Peripherals 765
Abbreviations Related to Registers 765
Access Types for Registers 767

Programming Reserved Register Field 769

Introduction 769
Programming Reserved Register Field 769

Interrupt Configuration Registers 770

Revision History 771

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List of Tables GoBack

List of Tables
1.4-1 ALU Operations Among Registers 32
1.4-2 ALU Operations with Immediate Value 33
1.4-3 ALU Operations with Stage Count Register 33
1.4-4 Input Signals Measured Using the ADC Instruction 38

3.3-1 Address Mapping 65

3.3-2 Embedded Memory Address Mapping 67
3.3-3 Module with DMA 69
3.3-4 External Memory Address Mapping 69
3.3-5 Cache memory mode 70
3.3-6 Peripheral Address Mapping 71

4.3-1 MPU and MMU Structure for Internal Memory 75

4.3-2 MPU for RTC FAST Memory 76
4.3-3 MPU for RTC SLOW Memory 76
4.3-4 Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 77
4.3-5 Page Boundaries for SRAM0 MMU 78
4.3-6 Page Boundaries for SRAM2 MMU 79
4.3-7 DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG 80
4.3-8 MPU for DMA 81
4.3-9 Virtual Address for External Memory 83
4.3-10 MMU Entry Numbers for PRO_CPU 83
4.3-11 MMU Entry Numbers for APP_CPU 83
4.3-12 MMU Entry Numbers for PRO_CPU (Special Mode) 84
4.3-13 MMU Entry Numbers for APP_CPU (Special Mode) 84
4.3-14 Virtual Address Mode for External SRAM 85
4.3-15 Virtual Address for External SRAM ( Normal Mode ) 86
4.3-16 Virtual Address for External SRAM ( Low-High Mode ) 86
4.3-17 Virtual Address for External SRAM (Even–Odd Mode) 86
4.3-18 MMU Entry Numbers for External RAM 87
4.3-19 MPU for Peripheral 88
4.3-20 DPORT_AHBLITE_MPU_TABLE_X_REG 89

5.3-1 System Parameters 90

5.3-2 BLOCK1/2/3 Encoding 93
5.3-3 Program Registers 94
5.3-4 Timing Configuration 96
5.3-5 Software Read Registers 97

6.6-1 IO_MUX Light-sleep Pin Function Registers 120

6.9-1 GPIO_Matrix 123
6.10-1 IO_MUX Pin Summary 132
6.11-1 RTC IO MUX Pin Summary 133
6.12-1 GPIO Matrix Register Summary 133
6.12-2 IO MUX Register Summary 135

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6.12-3 RTC IO MUX Register Summary 136

6.13-1 Mapping of Bits to Pins 153

7.1-1 PRO_CPU and APP_CPU Reset Reason Values 165

7.2-1 CPU_CLK Source 167
7.2-2 CPU_CLK Derivation 167
7.2-3 Peripheral Clock Usage 167
7.2-4 APB_CLK 168
7.2-5 REF_TICK 168
7.2-6 LEDC_SCLK Derivation 169

8.3-1 PRO_CPU, APP_CPU Interrupt Configuration 175

8.3-2 CPU Interrupts 177

9.3-1 RTC Power Domains 187

9.3-2 Wake-up Source 190

13.3-1 Interrupt Vector Entry Address 271

13.3-2 Configuration of PIDCTRL_LEVEL_REG 271
13.3-3 Configuration of PIDCTRL_FROM_n_REG 272

14.3-1 Operation Mode 280

14.3-2 AES Text Endianness 281
14.3-3 AES-128 Key Endianness 282
14.3-4 AES-192 Key Endianness 282
14.3-5 AES-256 Key Endianness 282

20.1-1 Mapping Between SPI Bus Signals and Pin Function Signals 353
20.3-1 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode 356
20.4-1 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master 358
20.4-2 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave 358

21.3-1 SCL Frequency Configuration 390

22.1-1 I2S Signal Bus Description 415

22.4-1 Register Configuration 420
22.4-2 Send Channel Mode 420
22.4-3 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration 422
22.4-4 The Register Configuration to Which the Four Modes Correspond 422
22.4-5 Upsampling Rate Configuration 424
22.4-6 Down-sampling Configuration 425

24.4-1 Destination Address Filtering 467

24.4-2 Source Address Filtering 468
24.6-1 Timing Parameters - Receiving Data 473
24.6-2 Timing Parameters – Transmitting Data 473
24.8-1 Transmit Descriptor 0 (TDES0) 474
24.8-2 Transmit Descriptor 1 (TDES1) 478
24.8-3 Transmit Descriptor 2 (TDES2) 478

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24.8-4 Transmit Descriptor 3 (TDES3) 478

24.8-5 Receive Descriptor 0 (RDES0) 479
24.8-6 Receive Descriptor 1 (RDES1) 481
24.8-7 Receive Descriptor 2 (RDES2) 482
24.8-8 Receive Descriptor 3 (RDES3) 482
24.8-9 Receive Descriptor 4 (RDES4) 482

25.3-1 Data Frames and Remote Frames in SFF and EFF 527
25.3-2 Error Frame 529
25.3-3 Overload Frame 529
25.3-4 Interframe Space 530
25.3-5 Segments of a Nominal Bit Time 532
25.5-1 Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0x18 537
25.5-2 Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0x1c 537
25.5-3 Buffer Layout for Standard Frame Format and Extended Frame Format 539
25.5-4 TX/RX Frame Information (SFF/EFF); TWAI Address 0x40 540
25.5-5 TX/RX Identifier 1 (SFF); TWAI Address 0x44 541
25.5-6 TX/RX Identifier 2 (SFF); TWAI Address 0x48 541
25.5-7 TX/RX Identifier 1 (EFF); TWAI Address 0x44 541
25.5-8 TX/RX Identifier 2 (EFF); TWAI Address 0x48 541
25.5-9 TX/RX Identifier 3 (EFF); TWAI Address 0x4c 541
25.5-10 TX/RX Identifier 4 (EFF); TWAI Address 0x50 541
25.5-11 Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0x30 546
25.5-12 Bit Information of Bits SEG.4 - SEG.0 547
25.5-13 Bit Information of TWAI_ARB LOST CAP_REG; TWAI Address 0x2c 548

27.3-1 SD/MMC Signal Description 597

27.8-1 DES0 603
27.8-2 DES1 604
27.8-3 DES2 604
27.8-4 DES3 604
27.10-1 SD/MMC Timing Requirements 606

28.2-1 Commonly-used Frequencies and Resolutions 630

29.3-1 Configuration Parameters of the Operator Submodule 650

29.3-2 Timing Events Used in PWM Generator 658
29.3-3 Timing Events Priority When PWM Timer Increments 659
29.3-4 Timing Events Priority when PWM Timer Decrements 659
29.3-5 Dead Time Generator Switches Control Registers 668
29.3-6 Typical Dead Time Generator Operating Modes 669

31.2-1 ESP32 Capacitive Sensing Touch Pads 737

31.3-1 Inputs of SAR ADC 741
31.3-2 ESP32 SAR ADC Controllers 742
31.3-3 Fields of the Pattern Table Register 743
31.3-4 Fields of Type I DMA Data Format 744
31.3-5 Fields of Type II DMA Data Format 744

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31.6-4 Configuration of ENA/RAW/ST Registers 770

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List of Figures
1.2-1 ULP Coprocessor Diagram 30
1.4-1 The ULP Coprocessor Instruction Format 31
1.4-2 Instruction Type — ALU for Operations Among Registers 31
1.4-3 Instruction Type — ALU for Operations with Immediate Value 32
1.4-4 Instruction Type — ALU for Operations with Stage Count Register 33
1.4-5 Instruction Type — ST 33
1.4-6 Instruction Type — LD 34
1.4-7 Instruction Type — JUMP 35
1.4-8 Instruction Type — JUMPR 35
1.4-9 Instruction Type — JUMP 36
1.4-10 Instruction Type — HALT 36
1.4-11 Instruction Type — WAKE 36
1.4-12 Instruction Type — SLEEP 37
1.4-13 Instruction Type — WAIT 37
1.4-14 Instruction Type — ADC 37
1.4-15 Instruction Type — I2C 38
1.4-16 Instruction Type — REG_RD 39
1.4-17 Instruction Type — REG_WR 39
1.5-1 Control of ULP Program Execution 40
1.5-2 Sample of a ULP Operation Sequence 41
1.6-1 I2C Read Operation 43
1.6-2 I2C Write Operation 43

2.3-1 DMA Engine Architecture 57

2.3-2 Linked List Structure 57
2.4-1 Data Transfer in UDMA Mode 58
2.5-1 SPI DMA 59

3.2-1 System Structure 63

3.2-2 System Address Mapping 64
3.3-1 Cache Block Diagram 70

4.3-1 MMU Access Example 77

6.1-1 IO MUX, RTC IO MUX and GPIO Matrix Overview 114

6.1-2 Internal Structure of a Pad 115
6.2-1 Peripheral Input via IO MUX, GPIO Matrix 116
6.3-1 Output via GPIO Matrix 118
6.8-1 ESP32 I/O Pin Power Sources (QFN 6*6, Top View) 121
6.8-2 ESP32 I/O Pin Power Sources (QFN 5*5, Top View) 122

7.1-1 System Reset 164

7.2-1 System Clock 166

8.2-1 Interrupt Matrix Structure 173

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9.2-1 ESP32 Power Control 180

9.3-1 Digital Core Voltage Regulator 181
9.3-2 Low-Power Voltage Regulator 182
9.3-3 Flash Voltage Regulator 183
9.3-4 Brownout Detector 183
9.3-5 RTC Structure 185
9.3-6 RTC Low-Power Clocks 186
9.3-7 Digital Low-Power Clocks 186
9.3-8 RTC States 187
9.3-9 Power Modes 189
9.3-10 ESP32 Boot Flow 192

13.3-1 Interrupt Nesting 273

17.3-1 Flash Encryption/Decryption Module Architecture 303

18.3-1 Noise Source 307

19.3-1 UART Basic Structure 311

19.3-2 UART Shared RAM 312
19.3-3 UART Data Frame Structure 313
19.3-4 AT_CMD Character Format 314
19.3-5 Hardware Flow Control 315

20.1-1 SPI Architecture 353

20.3-1 SPI Master and Slave Full-duplex/Half-duplex Communication 355
20.3-2 SPI Data Buffer 357
20.4-1 GP-SPI Slave Data Output 360
20.5-1 Parallel QSPI 360
20.5-2 Communication Format of Parallel QSPI 361

21.3-1 I2C Master Architecture 389

21.3-2 I2C Slave Architecture 389
21.3-3 I2C Sequence Chart 390
21.3-4 Structure of The I2C Command Register 391
21.3-5 I2C Master Writes to Slave with 7-bit Address 392
21.3-6 I2C Master Writes to Slave with 10-bit Address 393
21.3-7 I2C Master Writes to addrM in RAM of Slave with 7-bit Address 394
21.3-8 Master Writes to Slave with 7-bit Address in Three Segments 395
21.3-9 Master Reads from Slave with 7-bit Address 396
21.3-10 Master Reads from Slave with 10-bit Address 397
21.3-11 Master Reads N Bytes of Data from addrM in Slave with 7-bit Address 397
21.3-12 Master Reads from Slave with 7-bit Address in Three Segments 398

22.1-1 I2S System Block Diagram 414

22.3-1 I2S Clock 417
22.4-1 Philips Standard 418
22.4-2 MSB Alignment Standard 418

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22.4-3 PCM Standard 419

22.4-4 Tx FIFO Data Mode 420
22.4-5 The First Stage of Receiving Data 421
22.4-6 Modes of Writing Received Data into FIFO 422
22.4-7 PDM Transmitting Module 423
22.4-8 PDM Sends Signal 424
22.4-9 PDM Receives Signal 424
22.4-10 PDM Receive Module 425
22.5-1 LCD Master Transmitting Mode 425
22.5-2 LCD Master Transmitting Data Frame, Form 1 426
22.5-3 LCD Master Transmitting Data Frame, Form 2 426
22.5-4 Camera Slave Receiving Mode 426
22.5-5 ADC Interface of I2S0 427
22.5-6 DAC Interface of I2S 427
22.5-7 Data Input by I2S DAC Interface 428

23.2-1 PULSE_CNT Architecture 450

23.2-2 PULSE_CNT Upcounting Diagram 452
23.2-3 PULSE_CNT Downcounting Diagram 452

24.1-1 Ethernet MAC Functionality Overview 460

24.1-2 Ethernet Block Diagram 462
24.6-1 MII Interface 469
24.6-2 MII Clock 471
24.6-3 RMII Interface 471
24.6-4 RMII Clock 472
24.6-5 RMII Timing - Receiving Data 473
24.6-6 RMII Timing – Transmitting Data 473
24.8-1 Transmit Descriptor 474
24.8-2 Receive Descriptor 479

25.3-1 The bit fields of Data Frames and Remote Frames 527
25.3-2 Various Fields of an Error Frame 528
25.3-3 The Bit Fields of an Overload Frame 529
25.3-4 The Fields within an Interframe Space 530
25.3-5 Layout of a Bit 534
25.4-1 TWAI Overview Diagram 534
25.5-1 Acceptance Filter 543
25.5-2 Single Filter Mode 543
25.5-3 Dual Filter Mode 545
25.5-4 Error State Transition 546
25.5-5 Positions of Arbitration Lost Bits 548

26.3-1 SDIO Slave Block Diagram 563

26.3-2 SDIO Bus Packet Transmission 563
26.3-3 CMD53 Content 564
26.3-4 SDIO Slave DMA Linked List Structure 564

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26.3-5 SDIO Slave Linked List 565

26.3-6 Packet Sending Procedure (Initiated by Slave) 566
26.3-7 Packet Receiving Procedure (Initiated by Host) 567
26.3-8 Loading Receiving Buffer 568
26.3-9 Sampling Timing Diagram 568
26.3-10 Output Timing Diagram 569

27.2-1 SD/MMC Controller Topology 596

27.3-1 SD/MMC Controller External Interface Signals 597
27.4-1 SDIO Host Block Diagram 598
27.4-2 Command Path State Machine 599
27.4-3 Data Transmit State Machine 600
27.4-4 Data Receive State Machine 600
27.7-1 Descriptor Chain 602
27.8-1 The Structure of a Linked List 603
27.10-1 SD/MMC Timing in HS Mode 606
27.11-1 Clock Phase Selection 607

28.2-1 LED_PWM Architecture 628

28.2-2 LED_PWM High-speed Channel Diagram 629
28.2-3 LED_PWM Divider 629
28.2-4 LED PWM Output Signal Diagram 631
28.2-5 Output Signal Diagram of Fading Duty Cycle 631

29.2-1 MCPWM Module Overview 647

29.3-1 Prescaler Submodule 648
29.3-2 Timer Submodule 649
29.3-3 Operator Submodule 650
29.3-4 Fault Detection Submodule 651
29.3-5 Capture Submodule 652
29.3-6 Count-Up Mode Waveform 653
29.3-7 Count-Down Mode Waveforms 653
29.3-8 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 654
29.3-9 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 654
29.3-10 UTEP and UTEZ Generation in Count-Up Mode 655
29.3-11 DTEP and DTEZ Generation in Count-Down Mode 655
29.3-12 DTEP and UTEZ Generation in Count-Up-Down Mode 656
29.3-13 Submodules Inside the PWM Operator 657
29.3-14 Symmetrical Waveform in Count-Up-Down Mode 661
29.3-15 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High 662
29.3-16 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 663
29.3-17 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Active High 664
29.3-18 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Complementary 665
29.3-19 Example of an NCI Software-Force Event on PWMxA 666

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29.3-20 Example of a CNTU Software-Force Event on PWMxB 667

29.3-21 Options for Setting up the Dead Time Generator Submodule 668
29.3-22 Active High Complementary (AHC) Dead Time Waveforms 670
29.3-23 Active Low Complementary (ALC) Dead Time Waveforms 670
29.3-24 Active High (AH) Dead Time Waveforms 671
29.3-25 Active Low (AL) Dead Time Waveforms 671
29.3-26 Example of Waveforms Showing PWM Carrier Action 672
29.3-27 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule673
29.3-28 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 674

30.2-1 RMT Architecture 727

30.2-2 Data Structure 727

31.2-1 Touch Sensor 736

31.2-2 Touch Sensor Structure 738
31.2-3 Touch Sensor Operating Flow 738
31.2-4 Touch FSM Structure 739
31.3-1 SAR ADC Depiction 740
31.3-2 SAR ADC Outline of Function 741
31.3-3 RTC SAR ADC Outline of Function 742
31.3-4 Diagram of DIG SAR ADC Controllers 743
31.4-1 Diagram of DAC Function 745
31.4-2 Cosine Waveform (CW) Generator 746

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Part I

Microprocessor and Master

This part covers the essential processing elements of the system, diving into the microprocessor architecture
of the ultra-low-power processor. Details include controllers for Direct Memory Access (DMA).

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Chapter 1

ULP Coprocessor (ULP)

1.1 Introduction
The ULP coprocessor is an ultra-low-power processor that remains powered on during the Deep-sleep mode
of the main SoC. Hence, the developer can store in the RTC memory a program for the ULP coprocessor to
access peripheral devices, internal sensors and RTC registers during deep sleep. This is useful for designing
applications where the CPU needs to be woken up by an external event, or timer, or a combination of these,
while maintaining minimal power consumption.

1.2 Features
• Contains up to 8 KB of SRAM for instructions and data

• Uses RTC_FAST_CLK, which is 8 MHz

• Works both in normal and deep sleep

• Is able to wake up the digital core or send an interrupt to the CPU

• Can access peripheral devices, internal sensors and RTC registers

• Contains four 16-bit general-purpose registers (R0, R1, R2, R3) for manipulating data and accessing
memory

• Includes one 8-bit Stage_cnt register which can be manipulated by ALU and used in JUMP instructions

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APB Bus

bridge
RTC CNTL REG

RTC Memory RTC IO REG

Arbiter
I2C CTRL SARADC REG

RTC I2C REG

TSENS CTRL
ULP
RTC Timer
Coprocessor
SAR CTRL

ESP32 RTC

Figure 1.2-1. ULP Coprocessor Diagram

1.3 Functional Description

The ULP coprocessor is a programmable FSM (Finite State Machine) that can work during deep sleep. Like
general-purpose CPUs, ULP coprocessor also has some instructions which can be useful for a relatively
complex logic, and also some special commands for RTC controllers/peripherals. The 8 KB of SRAM RTC slow
memory can be accessed by both the ULP coprocessor and the CPU; hence, it is usually used to store
instructions and share data between the ULP coprocessor and the CPU.

The ULP coprocessor can be started by software or a periodically-triggered timer. The operation of the ULP
coprocessor is ended by executing the HALT instruction. Meanwhile, it can access almost every module in
RTC domain, either through built-in instructions or RTC registers. In many cases the ULP coprocessor can be a
good supplement to, or replacement of, the CPU, especially for power-sensitive applications. Figure 1.2-1
shows the overall layout of a ULP coprocessor.

1.4 Instruction Set

The ULP coprocessor provides the following instructions:

• Perform arithmetic and logic operations - ALU

• Load and store data - LD, ST, REG_RD and REG_WR

• Jump to a certain address - JUMP

• Manage program execution - WAIT/HALT

• Control sleep period of ULP coprocessor - SLEEP

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• Wake up/communicate with SoC - WAKE

• Take measurements - ADC

• Communicate using I2C - I2C_RD/I2C_WR

The ULP coprocessor’s instruction format is shown in Figure 1.4-1.

31 28 27 0

OpCode Operands

Figure 1.4-1. The ULP Coprocessor Instruction Format

An instruction, which has one OpCode, can perform various different operations, depending on the setting of
Operands bits. A good example is the ALU instruction, which is able to perform 10 arithmetic and logic
operations; or the JUMP instruction, which may be conditional or unconditional, absolute or relative.

Each instruction has a fixed width of 32 bits. A series of instructions can make a program be executed by the
ULP coprocessor. The execution flow inside the program uses 32-bit addressing. The program is stored in a
dedicated region called Slow Memory (RTC_SLOW_MEM), which is visible to the main CPUs as one that has
an address range of 0x5000_0000 to 0x5000_1FFF (8 KB).

The OpCode in this chapter is represented by 4’dx, where 4 stands for 4-bit width, ’d is a decimal symbol, x
stands for the value of OpCode (x: 0 ~ 15).

1.4.1 ALU - Perform Arithmetic/Logic Operations

The ALU (Arithmetic and Logic Unit) performs arithmetic and logic operations on values stored in ULP
coprocessor registers, and on immediate values stored in the instruction itself.
The following operations are supported:

• Arithmetic: ADD and SUB

• Logic: bitwise logical AND and bitwise logical OR

• Bit shifting: LSH and RSH

• Moving data to register: MOVE

• Stage count register manipulation: STAGE_RST, STAGE_INC and STAGE_DEC

The ALU instruction, which has one OpCode, can perform various different arithmetic and logic operations,
depending on the setting of the instruction’s bits [27:21] accordingly.

1.4.1.1 Operations Among Registers

31 28 27 25 24 21 5 4 3 2 1 0

4’d7 3’b0 ALU_sel Rsrc2 Rsrc1 Rdst

Figure 1.4-2. Instruction Type — ALU for Operations Among Registers

When bits [27:25] of the instruction in Figure 1.4-2 are set to 3’b0, ALU performs operations, using the ULP
coprocessor register R[0-3]. The types of operations depend on the setting of the instruction’s bits [24:21]
presented in Table 1.4-1.

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Operand Description - see Figure 1.4-2

ALU_sel Type of ALU operation
Rdst Register R[0-3], destination
Rsrc1 Register R[0-3], source
Rsrc2 Register R[0-3], source

ALU_sel Instruction Operation Description

0 ADD Rdst = Rsrc1 + Rsrc2 Add to register
1 SUB Rdst = Rsrc1 - Rsrc2 Subtract from register
2 AND Rdst = Rsrc1 & Rsrc2 Bitwise logical AND of two operands
3 OR Rdst = Rsrc1 | Rsrc2 Bitwise logical OR of two operands
4 MOVE Rdst = Rsrc1 Move to register
5 LSH Rdst = Rsrc1 << Rsrc2 Bit shifting Left
6 RSH Rdst = Rsrc1 >> Rsrc2 Bit shifting Right

Table 1.4-1. ALU Operations Among Registers

Note:

• ADD/SUB operations can be used to set/clear the overflow flag in ALU.

• All ALU operations can be used to set/clear the zero flag in ALU.

1.4.1.2 Operations with Immediate Value

31 28 27 25 24 21 19 4 3 2 1 0

4’d7 3’b1 ALU_sel Imm Rsrc1 Rdst

Figure 1.4-3. Instruction Type — ALU for Operations with Immediate Value

When bits [27:25] of the instruction in Figure 1.4-3 are set to 3’b1, ALU performs operations, using register
R[0-3] and the immediate value stored in [19:4]. The types of operations depend on the setting of the
instruction’s bits [24:21] presented in Table 1.4-2.

Operand Description - see Figure 1.4-3

ALU_sel Type of ALU operation
Rdst Register R[0-3], destination
Rsrc1 Register R[0-3], source
Imm 16-bit signed value

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ALU_sel Instruction Operation Description

0 ADD Rdst = Rsrc1 + Imm Add to register
1 SUB Rdst = Rsrc1 - Imm Subtract from register
2 AND Rdst = Rsrc1 & Imm Bitwise logical AND of two operands
3 OR Rdst = Rsrc1 | Imm Bitwise logical OR of two operands
4 MOVE Rdst = Imm Move to register
5 LSH Rdst = Rsrc1 << Imm Bit shifting left
6 RSH Rdst = Rsrc1 >> Imm Bit shifting right

Table 1.4-2. ALU Operations with Immediate Value

Note:

• ADD/SUB operations can be used to set/clear the overflow flag in ALU.

• All ALU operations can be used to set/clear the zero flag in ALU.

1.4.1.3 Operations with Stage Count Register

31 28 27 25 24 21 11 4

4’d7 3’b2 ALU_sel Imm

Figure 1.4-4. Instruction Type — ALU for Operations with Stage Count Register

ALU is also able to increment/decrement by a given value, or reset the 8-bit register Stage_cnt. To do so, bits
[27:25] of instruction in Figure 1.4-4 should be set to 3’b2. The type of operation depends on the setting of
the instruction’s bits [24:21] presented in Table 1.4-3. The Stage_cnt is a separate register and is not a part of
the instruction in Figure 1.4-4.

Operand Description - see Figure 1.4-4

ALU_sel Type of ALU operation
Stage_cnt Stage count register, a separate register [7:0] used to store variables, such as loop index
Imm 8-bit value

ALU_sel Instruction Operation Description

0 STAGE_INC Stage_cnt = Stage_cnt + Imm Increment stage count register
1 STAGE_DEC Stage_cnt = Stage_cnt - Imm Decrement stage count register
2 STAGE_RST Stage_cnt = 0 Reset stage count register

Table 1.4-3. ALU Operations with Stage Count Register

1.4.2 ST – Store Data in Memory

31 28 27 25 20 10 3 2 1 0

4’d6 3’b100 4’b0 Offset 6’b0 Rdst Rsrc

Figure 1.4-5. Instruction Type — ST

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Operand Description - see Figure 1.4-5

Offset 10-bit signed value, offset expressed in 32-bit words
Rsrc Register R[0-3], 16-bit value to store
Rdst Register R[0-3], address of the destination, expressed in 32-bit words
Description
The instruction stores the 16-bit value of Rsrc in the lower half-word of memory with address Rdst + Offset.
The upper half-word is written with the current program counter (PC) (expressed in words and shifted to the
left by 5 bits) OR’d with Rdst (0..3):

Mem [ Rdst + Offset ]{31:0} = {PC[10:0], 3’b0, Rdst, Rsrc[15:0]}

The application can use the higher 16 bits to determine which instruction in the ULP program has written any
particular word into memory.

Note:

• This instruction can only access 32-bit memory words.

• Data from Rsrc is always stored in the lower 16 bits of a memory word. Differently put, it is not possible to
store Rsrc in the upper 16 bits of memory.

• The ”Mem” written is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP coprocessor,
corresponds to address 0x50000000, as seen by the main CPUs.

1.4.3 LD – Load Data from Memory

31 28 20 10 3 2 1 0

4’d13 Offset Rsrc Rdst

Figure 1.4-6. Instruction Type — LD

Operand Description - see Figure 1.4-6

Offset 10-bit signed value, offset expressed in 32-bit words
Rsrc Register R[0-3], address of destination memory, expressed in 32-bit words
Rdst Register R[0-3], destination
Description
The instruction loads the lower 16-bit half-word from memory with address Rsrc + offset into the destination
register Rdst:

Rdst[15:0] = Mem[ Rsrc + Offset ][15:0]

Note:

• This instruction can only access 32-bit memory words.

• In any case, it is always the lower 16 bits of a memory word that are loaded. Differently put, it is not
possible to read the upper 16 bits.

• The ”Mem” loaded is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP coprocessor,
corresponds to address 0x50000000, as seen by the main CPUs.

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1.4.4 JUMP – Jump to an Absolute Address

31 28 27 25 24 22 21 12 2 1 0

Sel
4’d8 3’b0 Type ImmAddr Rdst

Figure 1.4-7. Instruction Type — JUMP

Operand Description - see Figure 1.4-7

Rdst Register R[0-3], address to jump to
ImmAddr 11-bit address, expressed in 32-bit words
Sel Selects the address to jump to:
0 - jump to the address contained in ImmAddr
1 - jump to the address contained in Rdst
Type Jump type:
0 - make an unconditional jump
1 - jump only if the last ALU operation has set the zero flag
2 - jump only if the last ALU operation has set the overflow flag
Description
The instruction prompts a jump to the specified address. The jump can be either unconditional or based on
the ALU flag.

Note:
All jump addresses are expressed in 32-bit words.

1.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0)

31 28 27 25 24 17 16 15 0
Cond

4’d8 3’b1 Step Threshold

Figure 1.4-8. Instruction Type — JUMPR

Operand Description - see Figure 1.4-8

Step Relative shift from current position, expressed in 32-bit words:
if Step[7] = 0 then PC = PC + Step[6:0]
if Step[7] = 1 then PC = PC - Step[6:0]
Threshold Threshold value for condition (see Cond below) to jump
Cond Condition to jump:
0 - jump if R0 < Threshold
1 - jump if R0 >= Threshold
Description
The instruction prompts a jump to a relative address, if the above-mentioned condition is true. The condition
itself is the result of comparing the R0 register value and the Threshold value.

Note:
All jump addresses are expressed in 32-bit words.

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1.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count

Register)
31 28 27 25 24 17 16 15 7 0

4’d8 3’b2 Step Cond Threshold

Figure 1.4-9. Instruction Type — JUMP

Operand Description - see Figure 1.4-9

Step Relative shift from current position, expressed in 32-bit words:
if Step[7] = 0, then PC = PC + Step[6:0]
if Step[7] = 1, then PC = PC - Step[6:0]
Threshold Threshold value for condition (see Cond below) to jump
Cond Condition of jump:
1X - jump if Stage_cnt <= Threshold
00 - jump if Stage_cnt < Threshold
01 - jump if Stage_cnt >= Threshold
Note:

• A description of how to set the stage count register is provided in section 1.4.1.3.

• All jump addresses are expressed in 32-bit words.

Description
The instruction prompts a jump to a relative address if the above-mentioned condition is true. The condition
itself is the result of comparing the value of Stage_cnt (stage count register) and the Threshold value.

1.4.7 HALT – End the Program

31 28 0

4’d11

Figure 1.4-10. Instruction Type — HALT

Description
The instruction ends the operation of the processor and puts it into power-down mode.

Note:
After executing this instruction, the ULP coprocessor timer gets started.

1.4.8 WAKE – Wake up the Chip

31 28 27 25 0
1’b1

4’d9 3’b0

Figure 1.4-11. Instruction Type — WAKE

Description

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This instruction sends an interrupt from the ULP coprocessor to the RTC controller.

• If the SoC is in Deep-sleep mode, and the ULP wake-up is enabled, the above-mentioned interrupt will
wake up the SoC.

• If the SoC is not in Deep-sleep mode, and the ULP interrupt bit (RTC_CNTL_ULP_CP_INT_ENA) is set in
register RTC_CNTL_INT_ENA_REG, a RTC interrupt will be triggered.

1.4.9 Sleep – Set the ULP Timer’s Wake-up Period

31 28 27 25 2 0

4’d9 3’b1 sleep_reg

Figure 1.4-12. Instruction Type — SLEEP

Operand Description - see Figure 1.4-12

sleep_reg Selects one of five SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) as the wake-up period
of the ULP coprocessor
Description
The instruction selects which one of the SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) register values is to be
used by the ULP timer as the wake-up period. By default, the value of SENS_ULP_CP_SLEEP_CYC0_REG is
used.

1.4.10 WAIT – Wait for a Number of Cycles

31 28 15 0

4’d4 Cycles

Figure 1.4-13. Instruction Type — WAIT

Operand Description - see Figure 1.4-13

Cycles the number of cycles to wait between sleeps
Description
The instruction will delay the ULP coprocessor from getting into sleep for a certain number of Cycles.

1.4.11 ADC – Take Measurement with ADC

31 28 6 5 2 1 0
Sel

4’d5 Sar Mux Rdst

Figure 1.4-14. Instruction Type — ADC

Operand Description - see Figure 1.4-14

Rdst Destination Register R[0-3], results will be stored in this register.
Sel Selected ADC: 0 = SAR ADC1, 1 = SAR ADC2, see Table 1.4-4.
Sar Mux SARADC Pad [Sar_Mux - 1] is enabled, see Table 1.4-4.

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Table 1.4-4. Input Signals Measured Using the ADC Instruction

Pad Name/Signal/GPIO Sar_Mux Processed by /Sel

SENSOR_VP (GPIO36) 1
SENSOR_CAPP (GPIO37) 2
SENSOR_CAPN (GPIO38) 3
SENSOR_VN (GPIO39) 4
SAR ADC1/Sel = 0
32K_XP (GPIO33) 5
32K_XN (GPIO32) 6
VDET_1 (GPIO34) 7
VDET_2 (GPIO35) 8
GPIO4 1
GPIO0 2
GPIO2 3
MTDO (GPIO15) 4
MTCK (GPIO13) 5
SAR ADC2/Sel = 1
MTDI (GPIO12) 6
MTMS (GPIO14) 7
GPIO27 8
GPIO25 9
GPIO26 10

Description
The instruction prompts the taking of measurements with the use of ADC. Pads/signals available for ADC
measurement are provided in Table 1.4-4.

1.4.12 I2C_RD/I2C_WR – Read/Write I2C

31 28 27 25 22 21 19 18 16 15 8 7 0
R/W

4’d3 I2C Sel High Low Data Sub-addr

Figure 1.4-15. Instruction Type — I2C

Operand Description - see Figure 1.4-15

Sub-addr Slave register address
Data Data to write in I2C_WR operation (not used in I2C_RD operation)
Low High part of bit mask
High Low part of bit mask
I2C Sel Select register n of SENS_I2C_SLAVE_ADDRn (n: 0-7), which contains the I2C slave address.
R/W I2C communication direction:
1 - I2C write
0 - I2C read
Description
Communicate (read/write) with external I2C slave devices. Details on using the RTC I2C peripheral are
provided in section 1.6.

Note:

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When working in master mode, RTC_I2C samples the SDA input on the negative edge of SCL.

1.4.13 REG_RD – Read from Peripheral Register

31 28 27 23 22 18 9 0

4’d2 High Low Addr

Figure 1.4-16. Instruction Type — REG_RD

Operand Description - see Figure 1.4-16

Addr Register address, expressed in 32-bit words
High Register end bit number
Low Register start bit number
Description
The instruction prompts a read of up to 16 bits from a peripheral register into a general-purpose register
R0:

R0 = REG[Addr][High:Low]
In case of more than 16 bits being requested, i.e. High - Low + 1 > 16, then the instruction will return
[Low+15:Low].

Note:

• This instruction can access registers in RTC_CNTL, RTC_IO, SENS and RTC_I2C peripherals. The address
of the register, as seen from the ULP coprocessor, can be calculated from the address of the same
register on the DPORT bus, as follows:
addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE)/4

• The addr_ulp is expressed in 32-bit words (not in bytes), and value 0 maps onto the
DR_REG_RTCCNTL_BASE (as seen from the main CPUs). Thus, 10 bits of address cover a 4096-byte
range of peripheral register space, including regions DR_REG_RTCCNTL_BASE, DR_REG_RTCIO_BASE,
DR_REG_SENS_BASE and DR_REG_RTC_I2C_BASE.

1.4.14 REG_WR – Write to Peripheral Register

31 28 27 23 22 18 17 10 9 0

4’d1 High Low Data Addr

Figure 1.4-17. Instruction Type — REG_WR

Operand Description - see Figure 1.4-17

Addr Register address, expressed in 32-bit words
High Register end bit number
Low Register start bit number
Data Value to write, 8 bits
Description
The instruction prompts the writing of up to 8 bits from an immediate data value into a peripheral register.

REG[Addr][High:Low] = Data

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If more than 8 bits are requested, i.e. High - Low + 1 > 8, then the instruction will pad with zeros the bits above
the eighth bit.

Note:
See notes regarding addr_ulp in section 1.4.13 above.

1.5 ULP Program Execution

The ULP coprocessor is designed to operate independently of the main CPUs, while they are either in deep
sleep or running.

In a typical power-saving scenario, the ULP coprocessor operates while the main CPUs are in deep sleep. To
save power even further, the ULP coprocessor can get into sleep mode, as well. In such a scenario, there is a
specific hardware timer in place to wake up the ULP coprocessor, since there is no software program running
at the same time. This timer should be configured in advance by setting and then selecting one of the
SENS_ULP_CP_SLEEP_CYCn_REG registers that contain the expiration period. This can be done either by the
main program, or the ULP program with the REG_WR and SLEEP instructions. Then, the ULP timer should be
enabled by setting bit RTC_CNTL_ULP_CP_SLP_TIMER_EN in the RTC_CNTL_STATE0_REG register.

Figure 1.5-1. Control of ULP Program Execution

The ULP coprocessor puts itself into sleep mode by executing the HALT instruction. This also triggers the ULP
timer to start counting RTC_SLOW_CLK ticks which, by default, originate from an internal 150 kHz RC oscillator.
Once the timer expires, the ULP coprocessor is powered up and runs a program with the program counter

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(PC) which is stored in register SENS_PC_INIT. The relationship between the described signals and registers is
shown in Figure 1.5-1.

On reset or power-up the above-mentioned ULP program may start up only after the expiration of
SENS_ULP_CP_SLEEP_CYC0_REG, which is the default selection period of the ULP timer.

A sample operation sequence of the ULP program is shown in Figure 1.5-2, where the following steps are
executed:

1. Software enables the ULP timer by using bit RTC_CNTL_ULP_CP_SLP_TIMER_EN.

2. The ULP timer expires and the ULP coprocessor starts running the program at PC = SENS_PC_INIT.

3. The ULP program executes the HALT instruction; the ULP coprocessor is halted and the timer gets
restarted.

4. The ULP program executes the SLEEP instruction to change the sleep timer period register.

5. The ULP program, or software, disables the ULP timer by using bit RTC_CNTL_ULP_CP_SLP_TIMER_EN.

Figure 1.5-2. Sample of a ULP Operation Sequence

The specific timing of the wakeup, program execution and sleep sequence is governed by the ULP FSM as
follows:

1. On the ULP timer expiration the FSM wakes up the ULP and this process takes two clock cycles.

2. Then, before executing the program, the FSM waits for the number of cycles configured in
RTC_CNTL_ULPCP_TOUCH_START_WAIT field of the RTC_CNTL_TIMER2_REG register. This time is spent
waiting for the 8 MHz clock to get stable.

3. The ULP program is executed.

4. After calling HALT instruction, the program is stopped. The FSM requires additional two clock cycles to
put the ULP to sleep.

1.6 RTC_I2C Controller

The ULP coprocessor can use a separate I2C controller, located in the RTC domain, to communicate with
external I2C slave devices. RTC_I2C has a limited feature set, compared to I2C0/I2C1 peripherals.

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1.6.1 Configuring RTC_I2C

Before the ULP coprocessor can use the I2C instruction, certain parameters of the RTC_I2C need to be
configured. This can be done by the program running on one of the main CPUs, or by the ULP coprocessor
itself. Configuration is performed by writing certain timing parameters into the RTC_I2C registers:

1. Set the low and high SCL half-periods by using RTC_I2C_SCL_LOW_PERIOD_REG and
RTC_I2C_SCL_HIGH_PERIOD_REG in RTC_FAST_CLK cycles (e.g. RTC_I2C_SCL_LOW_PERIOD=40,
RTC_I2C_SCL_HIGH_PERIOD=40 for 100 kHz frequency).

2. Set the number of cycles between the SDA switch and the falling edge of SCL by using
RTC_I2C_SDA_DUTY_REG in RTC_FAST_CLK (e.g. RTC_I2C_SDA_DUTY=16).

3. Set the waiting time after the START condition by using RTC_I2C_SCL_START_PERIOD_REG (e.g.
RTC_I2C_SCL_START_PERIOD=30).

4. Set the waiting time before the END condition by using RTC_I2C_SCL_STOP_PERIOD_REG (e.g.
RTC_I2C_SCL_STOP_PERIOD=44).

5. Set the transaction timeout by using RTC_I2C_TIMEOUT_REG (e.g. RTC_I2C_TIMEOUT=200).

6. Enable the master mode (set the RTC_I2C_MS_MODE bit in RTC_I2C_CTRL_REG).

7. Write the address(es) of external slave(s) to SENS_I2C_SLAVE_ADDRn (n: 0-7). Up to eight slave
addresses can be pre-programmed this way. One of these addresses can then be selected for each
transaction as part of the ULP I2C instruction.

Once RTC_I2C is configured, instructions ULP I2C_RD and I2C_WR can be used.

1.6.2 Using RTC_I2C

The ULP coprocessor supports two instructions (with a single OpCode) for using RTC_I2C: I2C_RD (read) and
I2C_WR (write).

1.6.2.1 I2C_RD - Read a Single Byte

The I2C_RD instruction performs the following I2C transaction (see Figure 1.6-1):

1. Master generates a START condition.

2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from
SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_RD instruction.

3. Slave generates ACK.

4. Master sends slave register address (given as an argument to the I2C_RD instruction).

5. Slave generates ACK.

6. Master generates a repeated START condition.

7. Master sends slave address, with r/w bit set to 1 (“read”).

8. Slave sends one byte of data.

9. Master generates NACK.

10. Master generates a STOP condition.

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1 2 3 4 5 6 7 8 9 10

RSTRT
START

NACK

STOP
Master Slave Address W Reg Address Slave Address R

ACK

ACK
Slave Data

Figure 1.6-1. I2C Read Operation

Note:
The RTC_I2C peripheral samples the SDA signals on the falling edge of SCL. If the slave changes SDA in less
than 0.38 microseconds, the master will receive incorrect data.

The byte received from the slave is stored into the R0 register.

1.6.2.2 I2C_WR - Write a Single Byte

The I2C_WR instruction performs the following I2C transaction (see Figure 1.6-2):

1. Master generates a START condition.

2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from
SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_WR instruction.

3. Slave generates ACK.

4. Master sends slave register address (given as an argument to the I2C_WR instruction).

5. Slave generates ACK.

6. Master generates a repeated START condition.

7. Master sends slave address, with r/w bit set to 0 (“write”).

8. Master sends one byte of data.

9. Slave generates ACK.

10. Master generates a STOP condition.

1 2 3 4 5 6 7 8 9 10
RSTRT
START

STOP

Master Slave Address W Reg Address Slave Address W Data

ACK

ACK

ACK

Slave

Figure 1.6-2. I2C Write Operation

1.6.2.3 Detecting Error Conditions

ULP I2C_RD and I2C_WR instructions will not report error conditions, such as a NACK from a slave, via ULP
registers. Instead, applications can query specific bits in the RTC_I2C_INT_ST_REG register to determine if the
transaction was successful. To enable checking for specific communication events, their corresponding bits
should be set in register RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific
communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using
RTC_I2C_INT_CLR_REG.

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1.6.2.4 Connecting I2C Signals

SDA and SCL signals can be mapped onto two out of the four GPIO pins, which are identified in Table
RTC_MUX Pin Summary in Chapter IO_MUX and GPIO Matrix, using the RTCIO_SAR_I2C_IO_REG
register.

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1.7 Register Summary

1.7.1 SENS_ULP Address Space

Name Description Address Access

ULP Timer cycles select
SENS_ULP_CP_SLEEP_CYC0_REG Timer cycles setting 0 0x3FF48818 R/W
SENS_ULP_CP_SLEEP_CYC1_REG Timer cycles setting 1 0x3FF4881C R/W
SENS_ULP_CP_SLEEP_CYC2_REG Timer cycles setting 2 0x3FF48820 R/W
SENS_ULP_CP_SLEEP_CYC3_REG Timer cycles setting 3 0x3FF48824 R/W
SENS_ULP_CP_SLEEP_CYC4_REG Timer cycles setting 4 0x3FF48828 R/W
RTC I2C slave address select
SENS_SAR_SLAVE_ADDR1_REG I2C addresses 0 and 1 0x3FF4883C R/W
SENS_SAR_SLAVE_ADDR2_REG I2C addresses 2 and 3 0x3FF48840 R/W
SENS_SAR_SLAVE_ADDR3_REG I2C addresses 4 and 5 0x3FF48844 R/W
SENS_SAR_SLAVE_ADDR4_REG I2C addresses 6 and 7, I2C control 0x3FF48848 R/W
RTC I2C control
SENS_SAR_I2C_CTRL_REG I2C control registers 0x3FF48850 R/W

1.7.2 RTC_I2C Address Space

Name Description Address Access

RTC I2C control registers
RTC_I2C_CTRL_REG Transmission setting 0x3FF48C04 R/W
RTC_I2C_DEBUG_STATUS_REG Debug status 0x3FF48C08 R/W
RTC_I2C_TIMEOUT_REG Timeout setting 0x3FF48C0C R/W
RTC_I2C_SLAVE_ADDR_REG Local slave address setting 0x3FF48C10 R/W
RTC I2C signal setting registers
Configures the SDA hold time after a neg-
RTC_I2C_SDA_DUTY_REG 0x3FF48C30 R/W
ative SCL edge
RTC_I2C_SCL_LOW_PERIOD_REG Configures the low level width of SCL 0x3FF48C00 R/W
RTC_I2C_SCL_HIGH_PERIOD_REG Configures the high level width of SCL 0x3FF48C38 R/W
Configures the delay between the SDA and
RTC_I2C_SCL_START_PERIOD_REG 0x3FF48C40 R/W
SCL negative edge for a start condition
Configures the delay between the SDA and
RTC_I2C_SCL_STOP_PERIOD_REG 0x3FF48C44 R/W
SCL positive edge for a stop condition
RTC I2C interrupt registers - listed only for debugging
RTC_I2C_INT_CLR_REG Clear status of I2C communication events 0x3FF48C24 R/W
Enable capture of I2C communication sta-
RTC_I2C_INT_EN_REG 0x3FF48C28 R/W
tus events
Status of captured I2C communication
RTC_I2C_INT_ST_REG 0x3FF48C2C R/O
events

Note:

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Interrupts from RTC_I2C are not connected. The interrupt registers above are listed only for debugging
purposes.

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1.8 Registers

1.8.1 SENS_ULP Address Space

The addresses in parenthesis besides register names are the register addresses relative to (the RTC base
address + 0x0800). The RTC base address is provided in Table 3.3-6 Peripheral Address Mapping in Chapter
3 System and Memory. The absolute register addresses are listed in Section 1.7.1 SENS_ULP Address
Space.

Register 1.1. SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) (0x18+0x4*n)

31 0

20 Reset

SENS_ULP_CP_SLEEP_CYCn_REG ULP timer cycles setting n; the ULP coprocessor can select one
of such registers by using the SLEEP instruction. (R/W)

Register 1.2. SENS_SAR_START_FORCE_REG (0x002c)

P
TO
T_
AR
RC OP
ST
E_
FO T_T
P_ AR
_C ST
LP P_
T
NI

_U _C
I
C_

NS LP
)

NS d)

)
ed

ed
SE rve
SE _U
_P
rv

rv
NS
se

se

se
(re

(re

(re
SE

31 22 21 11 10 9 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SENS_PC_INIT ULP PC entry address. (R/W)

SENS_ULP_CP_START_TOP Set this bit to start the ULP coprocessor; it is active only when
SENS_ULP_CP_FORCE_START_TOP = 1. (R/W)

SENS_ULP_CP_FORCE_START_TOP 1: ULP coprocessor is started by

SENS_ULP_CP_START_TOP; 0: ULP coprocessor is started by timer. (R/W)

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Register 1.3. SENS_SAR_SLAVE_ADDR1_REG (0x003c)

R0

R1
DD

DD
_A

_A
E

E
AV

AV
L

L
_S

_S
)

2C

2C
ed

_I

_I
rv

NS

NS
se
(re

SE

SE
31 22 21 11 10 0

0 0 0 0 0 0 0 0 0 0 0x000 0x000 Reset

SENS_I2C_SLAVE_ADDR0 I2C slave address 0. (R/W)

SENS_I2C_SLAVE_ADDR1 I2C slave address 1. (R/W)

Register 1.4. SENS_SAR_SLAVE_ADDR2_REG (0x0040)

R2

R3
DD

DD
_A

_A
E

E
AV

AV
L

SL
_S

C_
)

2C
ed

2
_I

_I
rv

NS

NS
se
(re

SE

SE
31 22 21 11 10 0

0 0 0 0 0 0 0 0 0 0 0x000 0x000 Reset

SENS_I2C_SLAVE_ADDR2 I2C slave address 2. (R/W)

SENS_I2C_SLAVE_ADDR3 I2C slave address 3. (R/W)

Register 1.5. SENS_SAR_SLAVE_ADDR3_REG (0x0044)

5
R4

R
DD

DD
_A

_A
E

E
AV

AV
L

L
_S

_S
)

2C

2C
ed

_I
rv

S_

NS
se

N
(re

SE

SE

31 22 21 11 10 0

0 0 0 0 0 0 0 0 0 0 0x000 0x000 Reset

SENS_I2C_SLAVE_ADDR4 I2C slave address 4. (R/W)

SENS_I2C_SLAVE_ADDR5 I2C slave address 5. (R/W)

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Register 1.6. SENS_SAR_SLAVE_ADDR4_REG (0x0048)

R6

R7
DD

DD
_A

_A
TA

E
E

AV

AV
ON

DA

L
_D

_R

_S

_S
NS d)
2C

2C

2C

2C
SE rve
_I

_I

_I

_I
NS

NS

NS
se
(re

SE

SE

SE
31 30 29 22 21 11 10 0

0 0 0x000 0x000 0x000 Reset

SENS_I2C_DONE Indicate I2C done. (RO)

SENS_I2C_RDATA I2C read data. (RO)

SENS_I2C_SLAVE_ADDR6 I2C slave address 6. (R/W)

SENS_I2C_SLAVE_ADDR7 I2C slave address 7. (R/W)

Register 1.7. SENS_SAR_I2C_CTRL_REG (0x0050)

C E
RT OR
TA _F
_S RT

RL
2C TA

T
_C
_I _S
AR 2C

2C
_S _I

I
R_
NS AR
NS )
ed

A
SE _S

_S
rv

NS
se
(re

SE

SE

31 30 29 28 27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SENS_SAR_I2C_START_FORCE 1: I2C started by SW, 0: I2C started by FSM. (R/W)

SENS_SAR_I2C_START Start I2C; active only when SENS_SAR_I2C_START_FORCE = 1. (R/W)

SENS_SAR_I2C_CTRL I2C control data; active only when SENS_SAR_I2C_START_FORCE = 1. (R/W)

1.8.2 RTC_I2C Address Space

The addresses in parenthesis besides register names are the register addresses relative to (the RTC base
address + 0x0C00). The RTC base address is provided in Table 3.3-6 Peripheral Address Mapping in Chapter
3 System and Memory. The absolute register addresses are listed in Section 1.7.2 RTC_I2C Address
Space.

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Register 1.8. RTC_I2C_SCL_LOW_PERIOD_REG (0x000)

OD
RI
E
_P
OW
_L
CL
_S
)
ed

2C
rv

I
se

C_
(re

RT
31 19 18 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SCL_LOW_PERIOD Number of RTC_FAST_CLK cycles when SCL == 0. (R/W)

Register 1.9. RTC_I2C_CTRL_REG (0x004)

T
E_ T
OU
RC OU
(re C_ ANS FIR T
se MS _S ST
OD RT
I2 R B_ RS

FO E_
_M TA
C_ C_T LS FI

A_ RC
E
RT _I2 TX_ SB_

SD FO
C_ L_
C C_ L
RT _I2 RX_

I2 SC
)

RT ed)
C C_

C_ C_
ed

RT _I2

RT I2
rv

rv
se

C_
C
(re

RT
31 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_RX_LSB_FIRST Receive LSB first. (R/W)

RTC_I2C_TX_LSB_FIRST Send LSB first. (R/W)

RTC_I2C_TRANS_START Force to generate a start condition. (R/W)

RTC_I2C_MS_MODE Master (1), or slave (0). (R/W)

RTC_I2C_SCL_FORCE_OUT SCL is push-pull (1) or open-drain (0). (R/W)

RTC_I2C_SDA_FORCE_OUT SDA is push-pull (1) or open-drain (0). (R/W)

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Register 1.10. RTC_I2C_DEBUG_STATUS_REG (0x008)

CH
AT
C C_ B_ SY M
RT _I2 AR BU DR_
RT _I2 BU E_A S
E

C C_ V AN

AC E_ T
AT
E

K_ RW
C_ C_ ED T
C C_ S_ D

C_ AV U
AT

RT _I2 TIM LOS

ST

RT _I2 SLA _TR

L
ST

VA
_
N_
L_

C C_ E
RT _I2 BYT
AI
SC

I2 L
M

S
)

d)
C_

C_

C C_
ed

ve
I2

I2

RT _I2
rv

r
se

se
C_

C_

C
(re

(re
RT

RT

RT
31 30 28 27 25 24 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SCL_STATE State of SCL machine. (R/W)

RTC_I2C_MAIN_STATE State of the main machine. (R/W)

RTC_I2C_BYTE_TRANS 8-bit transmit done. (R/W)

RTC_I2C_SLAVE_ADDR_MATCH Indicates whether the addresses are matched, when in slave

mode. (R/W)

RTC_I2C_BUS_BUSY Operation is in progress. (R/W)

RTC_I2C_ARB_LOST Indicates the loss of I2C bus control, when in master mode. (R/W)

RTC_I2C_TIMED_OUT Transfer has timed out. (R/W)

RTC_I2C_SLAVE_RW Indicates the value of the received R/W bit, when in slave mode. (R/W)

RTC_I2C_ACK_VAL The value of ACK signal on the bus. (R/W)

Register 1.11. RTC_I2C_TIMEOUT_REG (0x00c)

U T
EO
IM
_T
)
ed

2C
rv

I
se

C_
(re

RT

31 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_TIMEOUT Maximum number of RTC_FAST_CLK cycles that the transmission can take.
(R/W)

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Register 1.12. RTC_I2C_SLAVE_ADDR_REG (0x010)

T
BI
0
_1
DR

R
DD
AD

_A
E_

E
AV

AV
L

L
_S

_S
d)
2C

2C
ver
I

I
se
C_

C_
(re
RT

RT
31 30 15 14 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SLAVE_ADDR_10BIT Set if local slave address is 10-bit. (R/W)

RTC_I2C_SLAVE_ADDR Local slave address. (R/W)

Register 1.13. RTC_I2C_INT_CLR_REG (0x024)

LR

R
ET R _C

CL
PL L T

T_
M T_C _IN

IN
AN LO MP LR
CO IN TE

E_
TR _ O _C
S_ ST_ LE
E_ ION _C NT
AV AT NS _I
I2 AR ER MP LR
SL TR RA TE
C_ C_ ST O _C
C_ BI _T LE
RT _I2 MA S_C INT
C C_ N T_
RT _I2 TRA OU
C C_ E_
RT _I2 TIM
)

)
C C_
ed

ed
RT _I2
rv

rv
se

se
C
(re

(re
RT

31 9 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_TIME_OUT_INT_CLR Clear interrupt upon timeout. (R/W)

RTC_I2C_TRANS_COMPLETE_INT_CLR Clear interrupt upon detecting a stop pattern. (R/W)

RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR Clear interrupt upon completion of transaction,

when in master mode. (R/W)

RTC_I2C_ARBITRATION_LOST_INT_CLR Clear interrupt upon losing control of the bus, when in

master mode. (R/W)

RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR Clear interrupt upon completion of transaction,

when in slave mode. (R/W)

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Register 1.14. RTC_I2C_INT_EN_REG (0x028)

_E NA
NA
NT E
ST _IN A
_I T_
LO MP EN
N_ O T_
IO _C IN
AT AN E_
BI _T PLE A
AR TER M EN
TR R T
C_ S O _
I2 MA _C INT
C_ C_ NS T_
RT _I2 TRA OU
C C_ E_
RT _I2 TIM
d)

)
C C_

ed
ve

RT _I2

rv
r
se

se
C
(re

(re
RT
31 9 8 7 6 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_TIME_OUT_INT_ENA Enable interrupt upon timeout. (R/W)

RTC_I2C_TRANS_COMPLETE_INT_ENA Enable interrupt upon detecting a stop pattern. (R/W)

RTC_I2C_MASTER_TRAN_COMP_INT_ENA Enable interrupt upon completion of transaction, when

in master mode. (R/W)

RTC_I2C_ARBITRATION_LOST_INT_ENA Enable interrupt upon losing control of the bus, when in

master mode. (R/W)

Register 1.15. RTC_I2C_INT_ST_REG (0x02c)

_S T
NT S
_I T_

T
LO MP ST
ST _IN
N_ O T_
IO _C IN
AT AN E_
AR TER M ST
TR R T
BI _T PLE
C_ S O _
I2 MA _C INT
C_ C_ NS T_
RT _I2 TRA OU
C C_ E_
RT _I2 TIM
)

)
C C_
ed

ed
RT _I2
rv

rv
se

se
C
(re

(re
RT

31 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_TIME_OUT_INT_ST Detected timeout. (R/O)

RTC_I2C_TRANS_COMPLETE_INT_ST Detected stop pattern on I2C bus. (R/O)

RTC_I2C_MASTER_TRAN_COMP_INT_ST Transaction completed, when in master mode. (R/O)

RTC_I2C_ARBITRATION_LOST_INT_ST Bus control lost, when in master mode. (R/O)

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Register 1.16. RTC_I2C_SDA_DUTY_REG (0x030)

TY
_ DU
DA
_S
d)

2C
ver

I
se

C_
(re

RT
31 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SDA_DUTY Number of RTC_FAST_CLK cycles between the SDA switch and the falling
edge of SCL. (R/W)

Register 1.17. RTC_I2C_SCL_HIGH_PERIOD_REG (0x038)

OD
RI
PE
_
GH
HI
C L_
_S
)
ed

2C
rv

I
se

C_
(re

31 20 19 RT 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SCL_HIGH_PERIOD Number of RTC_FAST_CLK cycles when SCL == 1. (R/W)

Register 1.18. RTC_I2C_SCL_START_PERIOD_REG (0x040)

D
IO
ER
_P
A RT
ST
C L_
_S
)
ed

2C
rv

I
se

C_
(re

RT

31 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SCL_START_PERIOD Number of RTC_FAST_CLK cycles to wait before generating a start

condition. (R/W)

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Register 1.19. RTC_I2C_SCL_STOP_PERIOD_REG (0x044)

D
IO
ER
_P
OP
ST
C L_
_S
)
ed

2C
rv

I
se

C_
(re

RT
31 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_I2C_SCL_STOP_PERIOD Number of RTC_FAST_CLK cycles to wait before generating a stop

condition. (R/W)

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Chapter 2

DMA Controller (DMA)

2.1 Overview
Direct Memory Access (DMA) is used for high-speed data transfer between peripherals and memory, as well
as from memory to memory. Data can be quickly moved with DMA without any CPU intervention, thus allowing
for more efficient use of the cores when processing data.

In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1,
SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.

2.2 Features
The DMA controllers in the ESP32 feature:

• AHB bus architecture

• Support for full-duplex and half-duplex data transfers

• Programmable data transfer length in bytes

• Support for 4-beat burst transfer

• 328 KB DMA address space

• All high-speed communication modules powered by DMA

2.3 Functional Description

All modules that require high-speed data transfer in bulk contain a DMA controller. DMA addressing uses the
same data bus as the CPU to read/write to the internal RAM.

Each DMA controller features different functions. However, the architecture of the DMA engine
(DMA_ENGINE) is the same in all DMA controllers.

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2.3.1 DMA Engine Architecture

Figure 2.3-1. DMA Engine Architecture

The DMA Engine accesses SRAM over the AHB BUS. In Figure 2.3-1, the RAM represents the internal SRAM
banks available on ESP32. Further details on the SRAM addressing range can be found in Chapter 3 System
and Memory. Software can use a DMA Engine by assigning a linked list to define the DMA operational
parameters.

The DMA Engine transmits the data from the RAM to a peripheral, according to the contents of the out_link
descriptor. Also, the DMA Engine stores the data received from a peripheral into a specified RAM location,
according to the contents of the in_link descriptor.

2.3.2 Linked List

Figure 2.3-2. Linked List Structure

The DMA descriptor’s linked lists (out_link and in_link) have the same structure. As shown in Figure 2.3-2, a
linked-list descriptor consists of three words. The meaning of each field is as follows:

• owner (DW0) [31]: The allowed operator of the buffer corresponding to the current linked list.
1’b0: the allowed operator is the CPU;
1’b1: the allowed operator is the DMA controller.

• eof (DW0) [30]: End-Of-File character.

1’b0: the linked-list item does not mark the end of the linked list;
1’b1: the linked-list item is at the end of the linked list.

• reserved (DW0) [29:24]: Reserved bits.

Software should not write 1’s in this space.

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• length (DW0) [23:12]: The number of valid bytes in the buffer corresponding to the current linked list.
The field value indicates the number of bytes to be transferred to/from the buffer denoted by word DW1.

• size (DW0) [11:0]: The size of the buffer corresponding to the current linked list.
NOTE: The size must be word-aligned.

• buffer address pointer (DW1): Buffer address pointer. This is the address of the data buffer.
NOTE: The buffer address must be word-aligned.

• next descriptor address (DW2): The address pointer of the next linked-list item. The value is 0, if the
current linked-list item is the last on the list (eof=1).

When receiving data, if the data transfer length is smaller than the specified buffer size, DMA will not use the
remaining space. This enables the DMA engine to be used for transferring an arbitrary number of data
bytes.

2.4 UART DMA (UDMA)

The ESP32 has three UART interfaces that share two UDMA (UART DMA) controllers. The UHCI_UARTx_CE (x
is 0, 1, or 2) is used for selecting the UART controller to use the UDMA.

Figure 2.4-1. Data Transfer in UDMA Mode

Figure 2.4-1 shows the data transfer in UDMA mode. Before the DMA Engine receives data, software must
initialize the receive-linked-list. UHCI_INLINK_ADDR is used to point to the first in_link descriptor. The register
must be programmed with the lower 20 bits of the address of the initial linked-list item. After
UHCI_INLINK_START is set, the Universal Host Controller Interface (UHCI) will transmit the data received by
UART to the Decoder. After being parsed, the data will be stored in the RAM as specified by the
receive-linked-list descriptor.

Before DMA transmits data, software must initialize the transmit-linked-list and the data to be transferred.
UHCI_
OUTLINK_ADDR is used to point to the first out_link descriptor. The register must be programmed with the
lower 20 bits of the address of the initial transmit-linked-list item. After UHCI_OUTLINK_START is set, the DMA
Engine will read data from the RAM location specified by the linked-list descriptor and then transfer the data
through the Encoder. The DMA Engine will then shift the data out serially through the UART transmitter.

The UART DMA follows a format of (separator + data + separator). The Encoder is used for adding separators
before and after data, as well as using special-character sequences to replace data that are the same as
separators. The Decoder is used for removing separators before and after data, as well as replacing the
special-character sequences with separators. There can be multiple consecutive separators marking the

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beginning or end of data. These separators can be configured through UHCI_SEPER_CH, with the default
values being 0xC0. Data that are the same as separators can be replaced with UHCI_ESC_SEQ0_CHAR0
(0xDB by default) and UHCI_ESC_SEQ0_CHAR1 (0xDD by default). After the transmission process is complete,
a UHCI_OUT_TOTAL_EOF_INT interrupt will be generated. After the reception procedure is complete, a
UHCI_IN_
SUC_EOF_INT interrupt will be generated.

Note:
Please note that the buffer address pointer field in in_link descriptors should be word-aligned, and the size field in the
last in_link descriptor should be at least 4 bytes larger than the length of received data.

2.5 SPI DMA Interface

Figure 2.5-1. SPI DMA

ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from
Figure 2.5-1, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be
used by any one SPI controller at any given time.

The ESP32 SPI DMA Engine also uses a linked list to receive/transmit data. Burst transmission is supported.
The data size for a single transfer must be four bytes aligned. Consecutive data transfer is also
supported.

SPI1_DMA_CHAN_SEL[1:0], SPI2_DMA_CHAN_SEL[1:0] and SPI3_DMA_CHAN_SEL[1:0] in

DPORT_SPI_DMA_
CHAN_SEL_REG must be configured to enable the SPI DMA interface for a specific SPI controller. Each SPI
controller corresponds to one domain which has two bits with values 0, 1 and 2. Value 3 is reserved and must
not be configured for operation.

Considering SPI1 as an example,

if SPI SPI1_DMA_CHAN_SEL[1:0] = 0, then SPI1 does not use any DMA channel;
if SPI1_DMA_CHAN_SEL[1:0] = 1, then SPI1 enables DMA channel1;
if SPI1_DMA_CHAN_SEL[1:0] = 2, then SPI1 enables DMA channel2.

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The SPI_OUTLINK_START bit in SPI_DMA_OUT_LINK_REG and the SPI_INLINK_START bit in

SPI_DMA_IN_LINK_REG are used for enabling the DMA Engine. The two bits are self-cleared by hardware.
When SPI_OUTLINK_START is set to 1, the DMA Engine starts processing the outbound linked list descriptor
and prepares to transmit data. When SPI_INLINK_START is set to 1, then the DMA Engine starts processing the
inbound linked-list descriptor and gets prepared to receive data.

Software should configure the SPI DMA as follows:

1. Reset the DMA state machine and FIFO parameters;

2. Configure the DMA-related registers for operation;

3. Configure the SPI-controller-related registers accordingly;

4. Set SPI_USR to enable DMA operation.

2.6 I2S DMA Interface

The ESP32 integrates two I2S modules, I2S0 and I2S1, each of which is powered by a DMA channel. The
REG_I2S_DSCR_EN bit in I2S_FIFO_CONF_REG is used for enabling the DMA operation. ESP32 I2S DMA uses
the standard linked-list descriptor to configure DMA operations for data transfer. Burst transfer is supported.
However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.
REG_I2S_RX_EOF_NUM[31:0] bit in I2S_RXEOF_NUM_REG is used for configuring the data size of a single
transfer operation, in multiples of one word.

I2S_OUTLINK_START bit in I2S_OUT_LINK_REG and I2S_INLINK_START bit in I2S_IN_LINK_REG are used for
enabling the DMA Engine and are self-cleared by hardware. When I2S_OUTLINK_START is set to 1, the DMA
Engine starts processing the outbound linked-list descriptor and gets prepared to send data. When
I2S_INLINK_START is set to 1, the DMA Engine starts processing the inbound linked-list descriptor and gets
prepared to receive data.

Software should configure the I2S DMA as follows:

1. Configure I2S-controller-related registers;

2. Reset the DMA state machine and FIFO parameters;

3. Configure DMA-related registers for operation;

4. In I2S master mode, set I2S_TX_START bit or I2S_RX_START bit to initiate an I2S operation;
In I2S slave mode, set I2S_TX_START bit or I2S_RX_START bit and wait for data transfer to be initiated by
the host device.

For more information on I2S DMA interrupts, please see Section DMA Interrupts, in Chapter 22 I2S Controller
(I2S).

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 GoBack

Part II

Memory Organization
This part provides insights into the system’s memory structure, discussing the organization and mapping of
RAM, ROM, eFuse, and external memories, offering a framework for understanding memory-related
subsystems.

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Chapter 3

System and Memory

3.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.

With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they
use the same addresses to access the same memory. Multiple peripherals in the system can access
embedded memory via DMA.

The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most
purposes the two CPUs are interchangeable.

3.2 Features
• Address Space

– Symmetric address mapping

– 4 GB (32-bit) address space for both data bus and instruction bus

– 1296 KB embedded memory address space

– 19704 KB external memory address space

– 512 KB peripheral address space

– Some embedded and external memory regions can be accessed by either data bus or instruction
bus

– 328 KB DMA address space

• Embedded Memory

– 448 KB Internal ROM

– 520 KB Internal SRAM

– 8 KB RTC FAST Memory

– 8 KB RTC SLOW Memory

• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.

– Supports up to 16 MB off-Chip SPI Flash.

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– Supports up to 8 MB off-Chip SPI SRAM.

• Peripherals

– 41 peripherals

• DMA

– 13 modules are capable of DMA operation

The block diagram in Figure 3.2-1 illustrates the system structure, and the block diagram in Figure 3.2-2
illustrates the address map structure.

Figure 3.2-1. System Structure

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Figure 3.2-2. System Address Mapping

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3.3 Functional Description

3.3.1 Address Mapping

Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are
symmetric between the two CPUs.

Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.

The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and the most significant bytes of the
32-bit word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or
non-aligned byte, half-word and word read-and-write operations. The CPU can read and write data through the
instruction bus, but only in a word aligned manner; non-word-aligned access will cause a CPU
exception.

Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table
3.3-1 illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.

Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.

Table 3.3-1. Address Mapping

Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Mem-
ory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Mem-
ory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
Data / Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Mem-
ory
0x5000_2000 0xFFFF_FFFF Reserved

3.3.2 Embedded Memory

The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST
memory (8 KB) and RTC SLOW memory (8 KB).

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The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The
520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and
Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.

Table 3.3-2 lists all embedded memories and their address ranges on the data and instruction buses.

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Table 3.3-2. Embedded Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data Instruc-
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
tion

3.3.2.1 Internal ROM 0

The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range
0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.

The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order
to access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~
0x400B_7FFF any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF).
This can be done on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or
DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU, respectively.

3.3.2.2 Internal ROM 1

The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.

3.3.2.3 Internal SRAM 0

The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses

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0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.

3.3.2.4 Internal SRAM 1

The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses
0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the
instruction bus.

The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via
the data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word

The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is
not reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.

Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more
information.

3.3.2.5 Internal SRAM 2

The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses
0x3FFA_E000 ~ 0x3FFD_FFFF on the data bus.

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3.3.2.6 DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1
and an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.

In the ESP32, 13 peripherals are equipped with DMA. Table 3.3-3 lists these peripherals.

Table 3.3-3. Module with DMA

UART0 UART1 UART2

SPI1 SPI2 SPI3
I2S0 I2S1
SDIO Slave SDMMC
EMAC
BT WIFI

3.3.2.7 RTC FAST Memory

RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on
the instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.

The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.

3.3.2.8 RTC SLOW Memory

RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction
bus.

3.3.3 External Memory

The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 3.3-4 provides a list of
external memories that can be accessed by either CPU at a range of addresses on the data and instruction
buses. When a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s
address to an external physical memory address (in the external memory’s address space), according to the
MMU settings. Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB
External SRAM.

Table 3.3-4. External Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read

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Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read

3.3.4 Cache
As shown in Figure 3.3-1, each of the two CPUs in ESP32 has 32 KB of cache featuring a block size of 32
bytes for accessing external storage. PRO CPU uses bit PRO_CACHE_ENABLE in register
DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while APP CPU uses bit APP_CACHE_ENABLE in
register DPORT_APP_CACHE_CTRL_REG to enable the same function.

Figure 3.3-1. Cache Block Diagram

ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or
APP CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select
POOL0 or POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the
Cache function, POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory,
while they can also be used by the instruction bus. This is depicted in table 3.3-5 below.

Table 3.3-5. Cache memory mode

CACHE_MUX_MODE POOL0 POOL1

0 PRO CPU APP CPU
1 PRO CPU/APP CPU -
2 - PRO CPU/APP CPU
3 APP CPU PRO CPU

As described in table 3.3-5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot
enable the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only

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be used as the cache memory, and cannot be used by the instruction bus as well.

ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.
Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be ”PRO” or ”APP”,
indicating that the cache flush operation has been completed.

For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and
External Memory.

3.3.5 Peripherals
The ESP32 has 41 peripherals. Table 3.3-6 specifically describes the peripherals and their respective address
ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single
exception; this being the PID Controller.

Table 3.3-6. Peripheral Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0

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Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB eFuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB MCPWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
Data 0x3FF6_B000 0x3FF6_BFFF 4KB TWAI
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB MCPWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB Reserved
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB Reserved
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved

Notice:

• Peripherals accessed by the CPU via 0x3FF40000 ~ 0x3FF7FFFF address space (DPORT address) can
also be accessed via 0x60000000 ~ 0x6003FFFF (AHB address). (0x3FF40000 + n) address and
(0x60000000 + n) address access the same content, where n = 0 ~ 0x3FFFF.

• The CPU can access peripherals via DPORT address more efficiently than via AHB address. However,
DPORT address is characterized by speculative reads, which means it cannot guarantee that each read
is valid. In addition, DPORT address will upset the order of r/w operations on the bus to improve
performance, which may cause programs that have strict requirements on the r/w order to crash. On the
other hand, using AHB address to read FIFO registers will cause unpredictable errors. To address above
issues please strictly follow the instructions documented in ESP32 ECO and Workarounds for Bugs,
specifically sections 3.3, 3.10, 3.16, and 3.17.

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3.3.5.1 Asymmetric PID Controller Peripheral

There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart. Each
CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.

3.3.5.2 Non-Contiguous Peripheral Memory Ranges

The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.

3.3.5.3 Memory Speed

The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.

Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.

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Chapter 4

Memory Management and Protection Units (MMU, MPU)

4.1 Introduction
Every peripheral and memory section in the ESP32 is accessed through either an MMU (Memory
Management Unit) or an MPU (Memory Protection Unit). An MPU can allow or disallow the access of an
application to a memory range or peripheral, depending on what kind of permission the OS has given to that
particular application. An MMU can perform the same operation, as well as a virtual-to-physical memory
address translation. This can be used to map an internal or external memory range to a certain virtual memory
area. These mappings can be application-specific. Therefore, each application can be adjusted and have the
memory configuration that is necessary for it to run properly. To differentiate between the OS and applications,
there are eight Process Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each
application, or OS, is equipped with their own sets of mappings and rights.

4.2 Features
• Eight processes in each of the PRO_CPU and APP_CPU

• MPU/MMU management of on-chip memories, off-chip memories, and peripherals, based on process ID

• On-chip memory management by MPU/MMU

• Off-chip memory management by MMU

• Peripheral management by MPU

4.3 Functional Description

4.3.1 PID Controller

In the ESP32, a PID controller acts as an indicator that signals the MMU/MPU the owner PID of the code that
is currently running. The intention is that the OS updates the PID in the PID controller every time it switches
context to another application. The PID controller can detect interrupts and automatically switch PIDs to that
of the OS, if so configured.

There are two peripheral PID controllers in the system, one for each of the two CPUs in the ESP32. Having a
PID controller per CPU allows running different processes on different CPUs, if so desired.

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4.3.2 MPU/MMU
The MPU and MMU manage on-chip memories, off-chip memories, and peripherals. To do this they are based
on the process of accessing the peripheral or memory region. More specifically, when a code tries to access
a MMU/MPU-protected memory region or peripheral, the MMU or MPU will receive the PID from the PID
generator that is associated with the CPU on which the process is running.

For on-chip memory and peripherals, the decisions the MMU and MPU make are only based on this PID,
whereas the specific CPU the code is running on is not taken into account. Subsequently, the MMU/MPU
configuration for the internal memory and peripherals allows entries only for the eight different PIDs. In
contrast, the MMU moderating access to the external memory takes not only the PID into account, but also
the CPU the request is coming from. This means that MMUs have configuration options for every PID when
running on the APP_CPU, as well as every PID when running on the PRO_CPU. While, in practice, accesses
from both CPUs will be configured to have the same result for a specific process, doing so is not a hardware
requirement.

The decision an MPU can make, based on this information, is to allow or deny a process to access the
memory region or peripheral. An MMU has the same function, but additionally it redirects the virtual memory
access, which the process acquired, into a physical memory access that can possibly reach out an entirely
different physical memory region. This way, MMU-governed memory can be remapped on a
process-by-process basis.

4.3.2.1 Embedded Memory

The on-chip memory is governed by fixed-function MPUs, configurable MPUs, and MMUs:

Table 4.3-1. MPU and MMU Structure for Internal Memory

Address range
Name Size Governed by
From To
ROM0 384 KB 0x4000_0000 0x4005_FFFF Static MPU
ROM1 64 KB 0x3FF9_0000 0x3FF9_FFFF Static MPU
64 KB 0x4007_0000 0x4007_FFFF Static MPU
SRAM0
128 KB 0x4008_0000 0x4009_FFFF SRAM0 MMU
128 KB 0x3FFE_0000 0x3FFF_FFFF Static MPU
SRAM1 (aliases) 128 KB 0x400A_0000 0x400B_FFFF Static MPU
32 KB 0x4000_0000 0x4000_7FFF Static MPU
72 KB 0x3FFA_E000 0x3FFB_FFFF Static MPU
SRAM2
128 KB 0x3FFC_0000 0x3FFD_FFFF SRAM2 MMU
8 KB 0x3FF8_0000 0x3FF8_1FFF RTC FAST MPU
RTC FAST (aliases)
8 KB 0x400C_0000 0x400C_1FFF RTC FAST MPU
RTC SLOW 8 KB 0x5000_0000 0x5000_1FFF RTC SLOW MPU

Static MPUs

ROM0, ROM1, the lower 64 KB of SRAM0, SRAM1 and the lower 72 KB of SRAM2 are governed by a static
MPU. The behaviour of these MPUs are hardwired and cannot be configured by software. They moderate
access to the memory region solely through the PID of the current process. When the PID of the process is 0

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or 1, the memory can be read (and written when it is RAM) using the addresses specified in Table 4.3-1. When
it is 2 ~ 7, the memory cannot be accessed.

RTC FAST & RTC SLOW MPU

The 8 KB RTC FAST Memory as well as the 8 KB of RTC SLOW Memory are governed by two configurable
MPUs. The MPUs can be configured to allow or deny access to each individual PID, using the
RTC_CNTL_RTC_PID_
CONFIG_REG and DPORT_AHBLITE_MPU_TABLE_RTC_REG registers. Setting a bit in these registers will allow
the corresponding PID to read or write from the memory; clearing the bit disallows access. Access for PID 0
and 1 to RTC SLOW memory cannot be configured and is always enabled. Table 4.3-2 and 4.3-3 define the
bit-to-PID mappings of the registers.

Table 4.3-2. MPU for RTC FAST Memory

Boundary address Authority

Size PID
Low High
RTC_CNTL_RTC_PID_CONFIG bit
8 KB 0x3FF8_0000 0x3FF8_1FFF 01234567
8 KB 0x400C_0000 0x400C_1FFF 01234567

Table 4.3-3. MPU for RTC SLOW Memory

Boundary address Authority

Size PID
Low High PID = 0/1
DPORT_AHBLITE_MPU_TABLE_RTC_REG bit
234567
8 KB 0x5000_0000 0x5000_1FFF Read/Write
012345

Register RTC_CNTL_RTC_PID_CONFIG_REG is part of the RTC peripheral and can only be modified by
processes with a PID of 0; register DPORT_AHBLITE_MPU_TABLE_RTC_REG is a Dport register and can be
changed by processes with a PID of 0 or 1.

SRAM0 and SRAM2 upper 128 KB MMUs

Both the upper 128 KB of SRAM0 and the upper 128 KB of SRAM2 are governed by an MMU. Not only can
these MMUs allow or deny access to the memory they govern (just like the MPUs do), but they are also
capable of translating the address a CPU reads from or writes to (which is a virtual address) to a possibly
different address in memory (the physical address).

In order to accomplish this, the internal RAM MMUs divide the memory range they govern into 16 pages. The
page size is configurable as 8 KB, 4 KB and 2 KB. When the page size is 8 KB, the 16 pages span the entire 128
KB memory region; when the page size is 4 KB or 2 KB, a non-MMU-covered region of 64 or 96 KB,
respectively, will exist at the end of the memory space. Similar to the virtual and physical addresses, it is also
possible to imagine the pages as having a virtual and physical component. The MMU can convert an address
within a virtual page to an address within a physical page.

For PID 0 and 1, this mapping is 1-to-1, meaning that a read from or write to a certain virtual page will always be

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converted to a read from or write to the exact same physical page. This allows an operating system, running
under PID 0 and/or 1, to always have access to the entire physical memory range.

For PID 2 to 7, however, every virtual page can be reconfigured, on a per-PID basis, to map to a different
physical page. This way, reads and writes to an offset within a virtual page get translated into reads and writes
to the same offset within a different physical page. This is illustrated in Figure 4.3-1: the CPU (running a
process with a PID between 2 to 7) tries to access memory address 0x3FFC_2345. This address is within the
virtual Page 1 memory region, at offset 0x0345. The MMU is instructed that for this particular PID, it should
translate an access to virtual page 1 into physical Page 2. This causes the memory access to be redirected to
the same offset as the virtual memory access, yet in Page 2, which results in the effective access of physical
memory address 0x3FFC_4345. The page size in this example is 8 KB.

CPU VIRTUAL MMU PHYSICAL

3FFC_0000 3FFC_0000
PAGE 0 PAGE 0
3FFC_2000 3FFC_2000
3FFC_2345 PAGE 1 PAGE 1
3FFC_4000 3FFC_4000
3FFC_4345
PAGE 2 PAGE 2
3FFC_6000 3FFC_6000

3FFD_E000 3FFD_E000
PAGE 15 PAGE 15
3FFE_0000 3FFE_0000

Figure 4.3-1. MMU Access Example

Table 4.3-4. Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2

DPORT_IMMU_PAGE_MODE DPORT_DMMU_PAGE_MODE Page size

0 0 8 KB
1 1 4 KB
2 2 2 KB

Non-MMU Governed Memory

For the MMU-managed region of SRAM0 and SRAM2, the page size is configurable as 8 KB, 4 KB and 2 KB.
The configuration is done by setting the DPORT_IMMU_PAGE_MODE (for SRAM0) and
DPORT_DMMU_PAGE_MODE (for SRAM2) bits in registers DPORT_IMMU_PAGE_MODE_REG and
DPORT_DMMU_PAGE_MODE_REG, as detailed in Table 4.3-4. Because the number of pages for either region
is fixed at 16, the total amount of memory covered by these pages is 128 KB when 8 KB pages are selected, 64
KB when 4 KB pages are selected, and 32 KB when 2 KB pages are selected. This implies that for 8 KB pages,
the entire MMU-managed range is used, but for the other page sizes there will be a part of the 128 KB memory
that will not be governed by the MMU settings. Concretely, for a page size of 4 KB, these regions are
0x4009_0000 to 0x4009_FFFF and 0x3FFD_0000 to 0x3FFD_FFFF; for a page size of 2 KB, the regions are
0x4008_8000 to 0x4009_FFFF and 0x3FFC_8000 to 0x3FFD_FFFF. These ranges are readable and writable
by processes with a PID of 0 or 1; processes with other PIDs cannot access this memory.

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The layout of the pages in memory space is linear, namely, an SRAM0 MMU page n covers address space
0x40080000 + (pagesize×n) to 0x40080000 + (pagesize×(n + 1) − 1); similarily, an SRAM2 MMU page n covers
0x3F F C0000 + (pagesize×n) to 0x3F F C0000 + (pagesize×(n + 1) − 1). Tables 4.3-5 and 4.3-6 show the
resulting addresses in full.

Table 4.3-5. Page Boundaries for SRAM0 MMU

8 KB Pages 4 KB Pages 2 KB Pages

Page
Bottom Top Bottom Top Bottom Top
0 40080000 40081FFF 40080000 40080FFF 40080000 400807FF
1 40082000 40083FFF 40081000 40081FFF 40080800 40080FFF
2 40084000 40085FFF 40082000 40082FFF 40081000 400817FF
3 40086000 40087FFF 40083000 40083FFF 40081800 40081FFF
4 40088000 40089FFF 40084000 40084FFF 40082000 400827FF
5 4008A000 4008BFFF 40085000 40085FFF 40082800 40082FFF
6 4008C000 4008DFFF 40086000 40086FFF 40083000 400837FF
7 4008E000 4008FFFF 40087000 40087FFF 40083800 40083FFF
8 40090000 40091FFF 40088000 40088FFF 40084000 400847FF
9 40092000 40093FFF 40089000 40089FFF 40084800 40084FFF
10 40094000 40095FFF 4008A000 4008AFFF 40085000 400857FF
11 40096000 40097FFF 4008B000 4008BFFF 40085800 40085FFF
12 40098000 40099FFF 4008C000 4008CFFF 40086000 400867FF
13 4009A000 4009BFFF 4008D000 4008DFFF 40086800 40086FFF
14 4009C000 4009DFFF 4008E000 4008EFFF 40087000 400877FF
15 4009E000 4009FFFF 4008F000 4008FFFF 40087800 40087FFF
Rest - - 40090000 4009FFFF 4008800 4009FFFF

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Table 4.3-6. Page Boundaries for SRAM2 MMU

8 KB Pages 4 KB Pages 2 KB Pages

Page
Bottom Top Bottom Top Bottom Top
0 3FFC0000 3FFC1FFF 3FFC0000 3FFC0FFF 3FFC0000 3FFC07FF
1 3FFC2000 3FFC3FFF 3FFC1000 3FFC1FFF 3FFC0800 3FFC0FFF
2 3FFC4000 3FFC5FFF 3FFC2000 3FFC2FFF 3FFC1000 3FFC17FF
3 3FFC6000 3FFC7FFF 3FFC3000 3FFC3FFF 3FFC1800 3FFC1FFF
4 3FFC8000 3FFC9FFF 3FFC4000 3FFC4FFF 3FFC2000 3FFC27FF
5 3FFCA000 3FFCBFFF 3FFC5000 3FFC5FFF 3FFC2800 3FFC2FFF
6 3FFCC000 3FFCDFFF 3FFC6000 3FFC6FFF 3FFC3000 3FFC37FF
7 3FFCE000 3FFCFFFF 3FFC7000 3FFC7FFF 3FFC3800 3FFC3FFF
8 3FFD0000 3FFD1FFF 3FFC8000 3FFC8FFF 3FFC4000 3FFC47FF
9 3FFD2000 3FFD3FFF 3FFC9000 3FFC9FFF 3FFC4800 3FFC4FFF
10 3FFD4000 3FFD5FFF 3FFCA000 3FFCAFFF 3FFC5000 3FFC57FF
11 3FFD6000 3FFD7FFF 3FFCB000 3FFCBFFF 3FFC5800 3FFC5FFF
12 3FFD8000 3FFD9FFF 3FFCC000 3FFCCFFF 3FFC6000 3FFC67FF
13 3FFDA000 3FFDBFFF 3FFCD000 3FFCDFFF 3FFC6800 3FFC6FFF
14 3FFDC000 3FFDDFFF 3FFCE000 3FFCEFFF 3FFC7000 3FFC77FF
15 3FFDE000 3FFDFFFF 3FFCF000 3FFCFFFF 3FFC7800 3FFC7FFF
Rest - - 3FFD0000 3FFDFFFF 3FFC8000 3FFDFFFF

MMU Mapping

For each of the SRAM0 and SRAM2 MMUs, access rights and virtual to physical page mapping are done by a
set of 16 registers. In contrast to most of the other MMUs, each register controls a physical page, not a virtual
one. These registers control which of the PIDs have access to the physical memory, as well as which virtual
page maps to this physical page. The bits in the register are described in Table 4.3-7. Keep in mind that these
registers only govern accesses from processes with PID 2 to 7; PID 0 and 1 always have full read and write
access to all pages and no virtual-to-physical mapping is done. In other words, if a process with a PID of 0 or 1
accesses virtual page x, the access will always go to physical page x, regardless of these register settings.
These registers, as well as the page size selection registers DPORT_IMMU_PAGE_MODE_REG and
DPORT_DMMU_PAGE_MODE_REG, are only writable from a process with PID 0 or 1.

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Table 4.3-7. DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG

[6:4] Access rights for PID 2 ~ 7 [3:0] Address authority

0 None of PIDs 2 ~ 7 have access. 0x00 Virtual page 0 accesses this physical page.
1 All of PIDs 2 ~ 7 have access. 0x01 Virtual page 1 accesses this physical page.
2 Only PID 2 has access. 0x02 Virtual page 2 accesses this physical page.
3 Only PID 3 has access. 0x03 Virtual page 3 accesses this physical page.
4 Only PID 4 has access. 0x04 Virtual page 4 accesses this physical page.
5 Only PID 5 has access. 0x05 Virtual page 5 accesses this physical page.
6 Only PID 6 has access. 0x06 Virtual page 6 accesses this physical page.
7 Only PID 7 has access. 0x07 Virtual page 7 accesses this physical page.
0x08 Virtual page 8 accesses this physical page.
0x09 Virtual page 9 accesses this physical page.
0x10 Virtual page 10 accesses this physical page.
0x11 Virtual page 11 accesses this physical page.
0x12 Virtual page 12 accesses this physical page.
0x13 Virtual page 13 accesses this physical page.
0x14 Virtual page 14 accesses this physical page.
0x15 Virtual page 15 accesses this physical page.

Differences Between SRAM0 and SRAM2 MMU

The memory governed by the SRAM0 MMU is accessed through the processors I-bus, while the processor
accesses the memory governed by the SRAM2 MMU through the D-bus. Thus, the normal envisioned use is
for the code to be stored in the SRAM0 MMU pages and data in the MMU pages of SRAM2. In general,
applications running under a PID of 2 to 7 are not expected to modify their own code, because for these PIDs
access to the MMU pages of SRAM0 is read-only. These applications must, however, be able to modify their
data section, so that they are allowed to read as well as write MMU pages located in SRAM2. As stated before,
processes running under PID 0 or 1 always have full read-and-write access to both memory ranges.

DMA MPU

Applications may want to configure the DMA to send data straight from or to the peripherals they can control.
With access to DMA, a malicious process may also be able to copy data from or to a region it cannot normally
access. In order to be secure against that scenario, there is a DMA MPU which can be used to disallow DMA
transfers from memory regions with sensitive data in them.

For each 8 KB region in the SRAM1 and SRAM2 regions, there is a bit in the DPORT_AHB_MPU_TABLE_n_REG
registers which tells the MPU to either allow or disallow DMA access to this region. The DMA MPU uses only
these bits to decide if a DMA transfer can be started; the PID of the process is not a factor. This means that
when the OS wants to restrict its processes in a heterogenous fashion, it will need to re-load these registers
with the values applicable to the process to be run on every context switch.

The register bits that govern access to the 8 KB regions are detailed in Table 4.3-8. When a register bit is set,
DMA can read/write the corresponding 8 KB memory range. When the bit is cleared, access to that memory
range is denied.

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Table 4.3-8. MPU for DMA

Boundary address Authority

Size
Low High Register Bit
Internal SRAM 2
8 KB 0x3FFA_E000 0x3FFA_FFFF DPORT_AHB_MPU_TABLE_0_REG 0
8 KB 0x3FFB_0000 0x3FFB_1FFF DPORT_AHB_MPU_TABLE_0_REG 1
8 KB 0x3FFB_2000 0x3FFB_3FFF DPORT_AHB_MPU_TABLE_0_REG 2
8 KB 0x3FFB_4000 0x3FFB_5FFF DPORT_AHB_MPU_TABLE_0_REG 3
8 KB 0x3FFB_6000 0x3FFB_7FFF DPORT_AHB_MPU_TABLE_0_REG 4
8 KB 0x3FFB_8000 0x3FFB_9FFF DPORT_AHB_MPU_TABLE_0_REG 5
8 KB 0x3FFB_A000 0x3FFB_BFFF DPORT_AHB_MPU_TABLE_0_REG 6
8 KB 0x3FFB_C000 0x3FFB_DFFF DPORT_AHB_MPU_TABLE_0_REG 7
8 KB 0x3FFB_E000 0x3FFB_FFFF DPORT_AHB_MPU_TABLE_0_REG 8
8 KB 0x3FFC_0000 0x3FFC_1FFF DPORT_AHB_MPU_TABLE_0_REG 9
8 KB 0x3FFC_2000 0x3FFC_3FFF DPORT_AHB_MPU_TABLE_0_REG 10
8 KB 0x3FFC_4000 0x3FFC_5FFF DPORT_AHB_MPU_TABLE_0_REG 11
8 KB 0x3FFC_6000 0x3FFC_7FFF DPORT_AHB_MPU_TABLE_0_REG 12
8 KB 0x3FFC_8000 0x3FFC_9FFF DPORT_AHB_MPU_TABLE_0_REG 13
8 KB 0x3FFC_A000 0x3FFC_BFFF DPORT_AHB_MPU_TABLE_0_REG 14
8 KB 0x3FFC_C000 0x3FFC_DFFF DPORT_AHB_MPU_TABLE_0_REG 15
8 KB 0x3FFC_E000 0x3FFC_FFFF DPORT_AHB_MPU_TABLE_0_REG 16
8 KB 0x3FFD_0000 0x3FFD_1FFF DPORT_AHB_MPU_TABLE_0_REG 17
8 KB 0x3FFD_2000 0x3FFD_3FFF DPORT_AHB_MPU_TABLE_0_REG 18
8 KB 0x3FFD_4000 0x3FFD_5FFF DPORT_AHB_MPU_TABLE_0_REG 19
8 KB 0x3FFD_6000 0x3FFD_7FFF DPORT_AHB_MPU_TABLE_0_REG 20
8 KB 0x3FFD_8000 0x3FFD_9FFF DPORT_AHB_MPU_TABLE_0_REG 21
8 KB 0x3FFD_A000 0x3FFD_BFFF DPORT_AHB_MPU_TABLE_0_REG 22
8 KB 0x3FFD_C000 0x3FFD_DFFF DPORT_AHB_MPU_TABLE_0_REG 23
8 KB 0x3FFD_E000 0x3FFD_FFFF DPORT_AHB_MPU_TABLE_0_REG 24
Internal SRAM 1
8 KB 0x3FFE_0000 0x3FFE_1FFF DPORT_AHB_MPU_TABLE_0_REG 25
8 KB 0x3FFE_2000 0x3FFE_3FFF DPORT_AHB_MPU_TABLE_0_REG 26
8 KB 0x3FFE_4000 0x3FFE_5FFF DPORT_AHB_MPU_TABLE_0_REG 27
8 KB 0x3FFE_6000 0x3FFE_7FFF DPORT_AHB_MPU_TABLE_0_REG 28
8 KB 0x3FFE_8000 0x3FFE_9FFF DPORT_AHB_MPU_TABLE_0_REG 29
8 KB 0x3FFE_A000 0x3FFE_BFFF DPORT_AHB_MPU_TABLE_0_REG 30
8 KB 0x3FFE_C000 0x3FFE_DFFF DPORT_AHB_MPU_TABLE_0_REG 31
8 KB 0x3FFE_E000 0x3FFE_FFFF DPORT_AHB_MPU_TABLE_1_REG 0
8 KB 0x3FFF_0000 0x3FFF_1FFF DPORT_AHB_MPU_TABLE_1_REG 1
8 KB 0x3FFF_2000 0x3FFF_3FFF DPORT_AHB_MPU_TABLE_1_REG 2
8 KB 0x3FFF_4000 0x3FFF_5FFF DPORT_AHB_MPU_TABLE_1_REG 3
8 KB 0x3FFF_6000 0x3FFF_7FFF DPORT_AHB_MPU_TABLE_1_REG 4
8 KB 0x3FFF_8000 0x3FFF_9FFF DPORT_AHB_MPU_TABLE_1_REG 5
8 KB 0x3FFF_A000 0x3FFF_BFFF DPORT_AHB_MPU_TABLE_1_REG 6

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Boundary address Authority

Size
Low High Register Bit
8 KB 0x3FFF_C000 0x3FFF_DFFF DPORT_AHB_MPU_TABLE_1_REG 7
8 KB 0x3FFF_E000 0x3FFF_FFFF DPORT_AHB_MPU_TABLE_1_REG 8

Registers DPROT_AHB_MPU_TABLE_0_REG and DPROT_AHB_MPU_TABLE_1_REG are located in the DPort

address space. Only processes with a PID of 0 or 1 can modify these two registers.

Note:
In hardware, there are three instruction buses corresponding to V Addr1 , V Addr2 and V Addr3 , respectively. These
three buses can initiate load or fetch accesses simultaneously, but only one access is true. If more than one unmasked
instruction buses are present, then bit8 of all MMU entries should be set to zero. Otherwise, when an invalid MMU
entry is used by an access, the cache will be stalled even if there is no program at this access.

4.3.2.2 External Memory

Accesses to the external flash and external SPI RAM are done through a cache and are also handled by an
MMU. This Cache MMU can apply different mappings, depending on the PID of the process as well as the
CPU the process is running on. The MMU does this in a way that is similar to the internal memory MMU, that
is, for every page of virtual memory, it has a register detailing which physical page this virtual page should map
to. There are differences between the MMUs governing the internal memory and the Cache MMU, though.
First of all, the Cache MMU has a fixed page size (which is 64 KB for external flash and 32 KB for external RAM)
and secondly, instead of specifying access rights in the MMU entries, the Cache MMU has explicit mapping
tables for each PID and processor core. The MMU mapping configuration registers will be referred to as
’entries’ in the rest of this chapter. These registers are only accessible from processes with a PID of 0 or 1;
processes with a PID of 2 to 7 will have to delegate to one of the above-mentioned processes to change their
MMU settings.

The MMU entries, as stated before, are used for mapping a virtual memory page access to a physical memory
page access. The MMU controls five regions of virtual address space, detailed in Table 4.3-9. V Addr1 to
V Addr4 are used for accessing external flash, whereas V AddrRAM is used for accessing external RAM. Note
that V Addr4 is a subset of V Addr0 .

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Table 4.3-9. Virtual Address for External Memory

Boundary address
Name Size Page quantity
Low High
VAddr0 4 MB 0x3F40_0000 0x3F7F_FFFF 64
VAddr1 4 MB 0x4000_0000 0x403F_FFFF 64*
VAddr2 4 MB 0x4040_0000 0x407F_FFFF 64
VAddr3 4 MB 0x4080_0000 0x40BF_FFFF 64
VAddr4 1 MB 0x3F40_0000 0x3F4F_FFFF 16
V AddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF 128

* The configuration entries for address range 0x4000_0000 ~ 0x403F_FFFF are implemented and doc-
umented as if it were a full 4 MB address range, but it is not accessible as such. Instead, the address range
0x4000_0000 ~ 0x400C_1FFF accesses on-chip memory. This means that some of the configuration entries
for V Addr1 will not be used.

External Flash

For flash, the relationships among entry numbers, virtual memory ranges, and PIDs are detailed in Tables
4.3-10 and 4.3-11, which for every memory region and PID combination specify the first MMU entry governing
the mapping. This number refers to the MMU entry governing the very first page; the entire region is
described by the amount of pages specified in the ’count’ column.

These two tables are essentially the same, with the sole difference being that the APP_CPU entry numbers are
2048 higher than the corresponding PRO_CPU numbers. Note that memory regions V Addr0 and V Addr1 are
only accessible using PID 0 and 1, while V Addr1 can only be accessed by PID 2 ~ 7.

Table 4.3-10. MMU Entry Numbers for PRO_CPU

First MMU entry for PID

VAddr Count
0/1 2 3 4 5 6 7
VAddr0 64 0 - - - - - -
VAddr1 64 64 - - - - - -
VAddr2 64 128 256 384 512 640 768 896
VAddr3 64 192 320 448 576 704 832 960
VAddr4 16 - 1056 1072 1088 1104 1120 1136

Table 4.3-11. MMU Entry Numbers for APP_CPU

First MMU entry for PID

VAddr Count
0/1 2 3 4 5 6 7
VAddr0 64 2048 - - - - - -
VAddr1 64 2112 - - - - - -
VAddr2 64 2176 2304 2432 2560 2688 2816 2944
VAddr3 64 2240 2368 2496 2624 2752 2880 3008
VAddr4 16 - 3104 3120 3136 3152 3168 3184

As these tables show, virtual address VAddr1 can only be used by processes with a PID of 0 or 1. There is a

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special mode to allow processes with a PID of 2 to 7 to read the External Flash via address VAddr1 . When the
DPORT_PRO_SINGLE_IRAM_ENA bit of register DPORT_PRO_CACHE_CTRL_REG is 1, the MMU enters this
special mode for PRO_CPU memory accesses. Similarily, when the DPORT_APP_SINGLE_IRAM_ENA bit of
register DPORT_APP_CACHE_CTRL_REG is 1, the APP_CPU accesses memory using this special mode. In this
mode, the process and virtual address page supported by each configuration entry of MMU are different. For
details please see Table 4.3-12 and 4.3-13. As shown in these tables, in this special mode VAddr2 and VAddr3
cannot be used to access External Flash.

Table 4.3-12. MMU Entry Numbers for PRO_CPU (Special Mode)

First MMU entry for PID

VAddr Count
0/1 2 3 4 5 6 7
VAddr0 64 0 - - - - - -
VAddr1 64 64 256 384 512 640 768 896
VAddr2 64 - - - - - - -
VAddr3 64 - - - - - - -
VAddr4 16 - 1056 1072 1088 1104 1120 1136

Table 4.3-13. MMU Entry Numbers for APP_CPU (Special Mode)

First MMU entry for PID

VAddr Count
0/1 2 3 4 5 6 7
VAddr0 64 2048 - - - - - -
VAddr1 64 2112 2304 2432 2560 2688 2816 2944
VAddr2 64 - - - - - - -
VAddr3 64 - - - - - - -
VAddr4 16 - 3104 3120 3136 3152 3168 3184

Every configuration entry of MMU maps a virtual address page of a CPU process to a physical address page.
An entry is 32 bits wide. Of these, bits 0~7 indicate the physical page the virtual page is mapped to. Bit 8
should be cleared to indicate that the MMU entry is valid; entries with this bit set will not map any physical
address to the virtual address. Bits 10 to 32 are unused and should be written as zero. Because there are
eight address bits in an MMU entry, and the page size for external flash is 64 KB, a maximum of 256 × 64 KB =
16 MB of external flash is supported.

Examples

Example 1. A PRO_CPU process, with a PID of 1, needs to read external flash address 0x07_2375 via virtual
address 0x3F70_2375. The MMU is not in the special mode.

• According to Table 4.3-9, virtual address 0x3F70_2375 resides in the 0x30’th page of .VAddr0
• According to Table 4.3-10, the MMU entry for VAddr0 for PID 0/1 for the PRO_CPU starts at 0.
• The modified MMU entry is 0 + 0x30 = 0x30.
• Address 0x07_2375 resides in the 7’th 64 KB-sized page.
• MMU entry 0x30 needs to be set to 7 and marked as valid by setting the 8’th bit to 0. Thus, 0x007 is
written to MMU entry 0x30.

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Example 2. An APP_CPU process, with a PID of 4, needs to read external flash address 0x44_048C via virtual
address 0x4044_048C. The MMU is not in special mode.

• According to Table 4.3-9, virtual address 0x4044_048C resides in the 0x4’th page of VAddr2 .
• According to Table 4.3-11, the MMU entry for VAddr2 for PID 4 for the APP_CPU starts at 2560.
• The modified MMU entry is 2560 + 0x4 = 2564.
• Address 0x44_048C resides in the 0x44’th 64 KB-sized page.
• MMU entry 2564 needs to be set to 0x44 and marked as valid by setting the 8’th bit to 0. Thus, 0x044 is
written to MMU entry 2564.

External RAM

Processes running on PRO_CPU and APP_CPU can read and write External SRAM via the Cache at virtual
address range V AddrRAM , which is 0x3F80_0000 ~ 0x3FBF_FFFF. As with the flash MMU, the address space
and the physical memory are divided into pages. For the External RAM MMU, the page size is 32 KB and the
MMU is able to map 256 physical pages into the virtual address space, allowing for 32 KB × 256 = 8 MB of
physical external RAM to be mapped.

The mapping of virtual pages into this memory range depends on the mode this MMU is in: Low-High mode,
Even-Odd mode, or Normal mode. In all cases, the DPORT_PRO_DRAM_HL bit and DPORT_PRO_DRAM_SPLIT
bit in register DPORT_PRO_CACHE_CTRL_REG, the DPORT_APP_DRAM_HL bit and DPORT_APP_DRAM_SPLIT
bit in register DPORT_APP_CACHE_CTRL_REG determine the virtual address mode for External SRAM. For
details, please see Table 4.3-14. If a different mapping for the PRO_CPU and APP_CPU is required, the Normal
Mode should be selected, as it is the only mode that can provide this. If it is allowable for the PRO_CPU and
the APP_CPU to share the same mapping, using either High-Low or Even-Odd mode can give a speed gain
when both CPUs access memory frequently.

In case the APP_CPU cache is disabled, which renders the region of 0x4007_8000 to 0x4007_FFFF usable as
normal internal RAM, the usability of the various cache modes changes. Normal mode will allow PRO_CPU
access to external RAM to keep functioning, but the APP_CPU will be unable to access the external RAM.
High-Low mode allows both CPUs to use external RAM, but only for the 2 MB virtual memory addresses from
0x3F80_0000 to 0x3F9F_FFFF. It is not advised to use Even-Odd mode with the APP_CPU cache region
disabled.

Table 4.3-14. Virtual Address Mode for External SRAM

DPORT_PRO_DRAM_HL DPORT_PRO_DRAM_SPLIT
Mode
DPORT_APP_DRAM_HL DPORT_APP_DRAM_SPLIT
Low-High 1 0
Even-Odd 0 1
Normal 0 0

In normal mode, the virtual-to-physical page mapping can be different for both CPUs. Page mappings for
PRO_CPU are set using the MMU entries for L VAddrRAM , and page mappings for the APP_CPU can be
configured using the MMU entries for R VAddrRAM . In this mode, all 128 pages of both L VAddr and R VAddr are
fully used, allowing a maximum of 8 MB of memory to be mapped; 4 MB into PRO_CPU address space and a
possibly different 4 MB into the APP_CPU address space, as can be seen in Table 4.3-15.

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Table 4.3-15. Virtual Address for External SRAM ( Normal Mode )

PRO_CPU address
Virtual address Size
Low High
L
VAddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF
APP_CPU address
Virtual address Size
Low High
R
VAddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF

In Low-High mode, both the PRO_CPU and the APP_CPU use the same mapping entries. In this mode
L
VAddrRAM is used for the lower 2 MB of the virtual address space, while R VAddrRAM is used for the upper 2
MB. This also means that the upper 64 MMU entries for L VAddrRAM , as well as the lower 64 entries for
R
VAddrRAM , are unused. Table 4.3-16 details these address ranges.

Table 4.3-16. Virtual Address for External SRAM ( Low-High Mode )

PRO_CPU/APP_CPU address
Virtual address Size
Low High
L
VAddrRAM 2 MB 0x3F80_0000 0x3F9F_FFFF
R
VAddrRAM 2 MB 0x3FA0_0000 0x3FBF_FFFF

In Even-Odd memory, the VRAM is split into 32-byte chunks. The even chunks are resolved through the MMU
entries for L VAddrRAM , the odd chunks through the entries for R VAddrRAM . Generally, the MMU entries for
L
VAddrRAM and R VAddrRAM are set to the same values, so that the virtual pages map to a contiguous region of
physical memory. Table 4.3-17 details this mode.

Table 4.3-17. Virtual Address for External SRAM (Even–Odd Mode)

PRO_CPU/APP_CPU address
Virtual address Size
Low High
L
VAddrRAM 32 Bytes 0x3F80_0000 0x3F80_001F
R
VAddrRAM 32 Bytes 0x3F80_0020 0x3F80_003F
L
VAddrRAM 32 Bytes 0x3F80_0040 0x3F80_005F
R
VAddrRAM 32 Bytes 0x3F80_0060 0x3F80_007F
...
L
VAddrRAM 32 Bytes 0x3FBF_FFC0 0x3FBF_FFDF
R
VAddrRAM 32 Bytes 0x3FBF_FFE0 0x3FBF_FFFF

The bit configuration of the External RAM MMU entries is the same as for the flash memory: the entries are
32-bit registers, with the lower nine bits being used. Bits 0~7 contain the physical page the entry should map
its associate virtual page address to, while bit 8 is cleared when the entry is valid and set when it is not. Table
4.3-18 details the first MMU entry number for L VAddrRAM and R VAddrRAM for all PIDs.

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Table 4.3-18. MMU Entry Numbers for External RAM

First MMU entry for PID

VAddr Count
0/1 2 3 4 5 6 7
L
VAddrRAM 128 1152 1280 1408 1536 1664 1792 1920
R
VAddrRAM 128 3200 3328 3456 3584 3712 3840 3968

Examples

Example 1. A PRO_CPU process, with a PID of 7, needs to read or write external RAM address 0x7F_A375 via
virtual address 0x3FA7_2375. The MMU is in Low-High mode.

• According to Table 4.3-9, virtual address 0x3FA7_2375 resides in the 0x4E’th 32-KB-page of VAddrRAM .
• According to Table 4.3-16, virtual address 0x3FA7_2375 is governed by R VAddrRAM .
• According to Table 4.3-18, the MMU entry for R VAddrRAM for PID 7 for the PRO_CPU starts at 3968.
• The modified MMU entry is 3968 + 0x4E = 4046.
• Address 0x7F_A375 resides in the 255’th 32 KB-sized page.
• MMU entry 4046 needs to be set to 255 and marked as valid by clearing the 8’th bit. Thus, 0x0FF is
written to MMU entry 4046.

Example 2. An APP_CPU process, with a PID of 5, needs to read or write external RAM address 0x55_5805 up
to 0x55_5823 starting at virtual address 0x3F85_5805. The MMU is in Even-Odd mode.

• According to Table 4.3-9, virtual address 0x3F85_5805 resides in the 0x0A’th 32-KB-page of VAddrRAM .
• According to Table 4.3-17, the range to be read/written spans both a 32-byte region in R VAddrRAM and
L
VAddrRAM .
• According to Table 4.3-18, the MMU entry for L VAddrRAM for PID 5 starts at 1664.
• According to Table 4.3-18, the MMU entry for R VAddrRAM for PID 5 starts at 3712.
• The modified MMU entries are 1664 + 0x0A = 1674 and 3712 + 0x0A = 3722.
• The addresses 0x55_5805 to 0x55_5823 reside in the 0xAA’th 32 KB-sized page.
• MMU entries 1674 and 3722 need to be set to 0xAA and marked as valid by setting the 8’th bit to 0.
Thus, 0x0AA is written to MMU entries 1674 and 3722. This mapping applies to both the PRO_CPU and
the APP_CPU.

Example 3. A PRO_CPU process, with a PID of 1, and an APP_CPU process whose PID is also 1, need to read or
write external RAM using virtual address 0x3F80_0876. The PRO_CPU needs this region to access physical
address 0x10_0876, while the APP_CPU wants to access physical address 0x20_0876 through this virtual
address. The MMU is in Normal mode.

• According to Table 4.3-9, virtual address 0x3F80_0876 resides in the 0’th 32-KB-page of VAddrRAM .
• According to Table 4.3-18, the MMU entry for PID 1 for the PRO_CPU starts at 1152.
• According to Table 4.3-18, the MMU entry for PID 1 for the APP_CPU starts at 3200.
• The MMU entries that are modified are 1152 + 0 = 1152 for the PRO_CPU and 3200 + 0 = 3200 for the
APP_CPU.
• Address 0x10_0876 resides in the 0x20’th 32 KB-sized page.
• Address 0x20_0876 resides in the 0x40’th 32 KB-sized page.
• For the PRO_CPU, MMU entry 1152 needs to be set to 0x20 and marked as valid by clearing the 8’th bit.
Thus, 0x020 is written to MMU entry 1152.

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• For the APP_CPU, MMU entry 3200 needs to be set to 0x40 and marked as valid by clearing the 8’th bit.
Thus, 0x040 is written to MMU entry 3200.
• Now, the PRO_CPU and the APP_CPU can access different physical memory regions through the same
virtual address.

4.3.2.3 Peripheral
The Peripheral MPU manages the 39 peripheral modules. This MMU can be configured per peripheral to only
allow access from a process with a certain PID. The registers to configure this are detailed in Table
4.3-19.

Table 4.3-19. MPU for Peripheral

Authority
Peripheral
PID = 0/1 PID = 2 ~ 7
DPort Register Access Forbidden
AES Accelerator Access Forbidden
RSA Accelerator Access Forbidden
SHA Accelerator Access Forbidden
Secure Boot Access Forbidden
Cache MMU Table Access Forbidden
PID Controller Access Forbidden
UART0 Access DPORT_AHBLITE_MPU_TABLE_UART_REG
SPI1 Access DPORT_AHBLITE_MPU_TABLE_SPI1_REG
SPI0 Access DPORT_AHBLITE_MPU_TABLE_SPI0_REG
GPIO Access DPORT_AHBLITE_MPU_TABLE_GPIO_REG
RTC Access DPORT_AHBLITE_MPU_TABLE_RTC_REG
IO MUX Access DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_HINF_REG
UDMA1 Access DPORT_AHBLITE_MPU_TABLE_UHCI1_REG
I2S0 Access DPORT_AHBLITE_MPU_TABLE_I2S0_REG
UART1 Access DPORT_AHBLITE_MPU_TABLE_UART1_REG
I2C0 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG
UDMA0 Access DPORT_AHBLITE_MPU_TABLE_UHCI0_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG
RMT Access DPORT_AHBLITE_MPU_TABLE_RMT_REG
PCNT Access DPORT_AHBLITE_MPU_TABLE_PCNT_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLC_REG
LED PWM Access DPORT_AHBLITE_MPU_TABLE_LEDC_REG
Efuse Controller Access DPORT_AHBLITE_MPU_TABLE_EFUSE_REG
Flash Encryption Access DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG
PWM0 Access DPORT_AHBLITE_MPU_TABLE_PWM0_REG
TIMG0 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG
TIMG1 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG
SPI2 Access DPORT_AHBLITE_MPU_TABLE_SPI2_REG
SPI3 Access DPORT_AHBLITE_MPU_TABLE_SPI3_REG

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Authority
Peripheral
PID = 0/1 PID = 2 ~ 7
SYSCON Access DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG
I2C1 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG
SDMMC Access DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG
EMAC Access DPORT_AHBLITE_MPU_TABLE_EMAC_REG
PWM1 Access DPORT_AHBLITE_MPU_TABLE_PWM1_REG
I2S1 Access DPORT_AHBLITE_MPU_TABLE_I2S1_REG
UART2 Access DPORT_AHBLITE_MPU_TABLE_UART2_REG
RNG Access DPORT_AHBLITE_MPU_TABLE_PWR_REG

Each bit of register DPORT_AHBLITE_MPU_TABLE_X_REG determines whether each process can access the
peripherals managed by the register. For details please see Table 4.3-20. When a bit of register
DPORT_AHBLITE_
MPU_TABLE_X_REG is 1, it means that a process with the corresponding PID can access the corresponding
peripheral of the register. Otherwise, the process cannot access the corresponding peripheral.

Table 4.3-20. DPORT_AHBLITE_MPU_TABLE_X_REG

PID 234567
DPORT_AHBLITE_MPU_TABLE_X_REG bit 012345

All the DPORT_AHBLITE_MPU_TABLE_X_REG registers are in peripheral DPort Register. Only processes with
PID 0/1 can modify these registers.

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Chapter 5

eFuse Controller

5.1 Introduction
The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of
non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to
0. Software can instruct the eFuse Controller to program each bit for each system parameter as needed.

Some of these system parameters can be read by software using the eFuse Controller. Some of the system
parameters are also directly used by hardware modules.

5.2 Features
• Configuration of 33 system parameters

• Optional write-protection

• Optional software-read-protection

5.3 Functional Description

5.3.1 Structure
Thirty-three system parameters with different bit width are stored in the eFuses. The name of each system
parameter and the corresponding bit width are shown in Table 5.3-1. Among those parameters,
efuse_wr_disable, efuse_rd_disable, BLK3_part_reserve and coding_scheme are directly used by the eFuse
Controller.

Table 5.3-1. System Parameters

Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
efuse_wr_disable 16 1 - controls the eFuse Controller
efuse_rd_disable 4 0 - controls the eFuse Controller
governs the flash encryption/
flash_crypt_cnt 2 -
7 decryption

WIFI_MAC_Address 56 3 - Wi-Fi MAC address and CRC

configures the SPI I/O to a
SPI_pad_config_hd 5 3 -
certain pad

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Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
XPD_SDIO_REG 1 5 - powers up the flash regulator
configures the flash regulator
SDIO_TIEH 1 5 - voltage: set to 1 for 3.3 V
and set to 0 for 1.8 V

determines whether
XPD_SDIO_REG
sdio_force 1 5 -
and SDIO_TIEH can
control the flash regulator
BLK3_part_reserve 2 10 3 controls the eFuse controller
configures the SPI I/O to a
SPI_pad_config_clk 5 6 -
certain pad
configures the SPI I/O to a
SPI_pad_config_q 5 6 -
certain pad
configures the SPI I/O to a
SPI_pad_config_d 5 6 -
certain pad
configures the SPI I/O to a
SPI_pad_config_cs0 5 6 -
certain pad
governs flash encryption/
flash_crypt_config 4 10 3
decryption
coding_scheme* 2 10 3 controls the eFuse Controller
disables the ROM BASIC
console_debug_disable 1 15 - debug console fallback
mode when set to 1
determines the status of
abstract_done_0 1 12 -
Secure Boot
determines the status of
abstract_done_1 1 13 -
Secure Boot
disables access to the
JTAG controllers so as to
JTAG_disable 1 14 -
effectively disable external
use of JTAG
governs flash encryption/
download_dis_encrypt 1 15 -
decryption
governs flash encryption/
download_dis_decrypt 1 15 -
decryption
disables cache when boot
download_dis_cache 1 15 -
mode is the Download Mode
determines whether BLOCK3
key_status 1 10 3
is deployed for user purposes

governs flash encryption/

BLOCK1* 256/192/128 7 0
decryption

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Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
BLOCK2* 256/192/128 8 1 key for Secure Boot
BLOCK3* 256/192/128 9 2 key for user purposes
disable_app_cpu 1 3 - disables APP CPU
disable_bt 1 3 - disables Bluetooth
pkg_version 4 3 - packaging version
disable_cache 1 3 - disables cache
CK8M Frequency 8 4 - RC_FAST_CLK frequency
stores the voltage level for
vol_level_hp_inv 2 3 - CPU to run at 240 MHz, or
for flash/PSRAM to run at 80
MHz
stores the difference be-
dig_vol_l6 4 11 - tween the digital regulator
voltage at level 6 and 1.2 V.
permanently disables Down-
load Boot mode when set to
uart_download_dis 1 2 -
1. Valid only for ESP32 ECO
V3.

5.3.1.1 System Parameter efuse_wr_disable

The system parameter efuse_wr_disable determines whether all of the system parameters are write-protected.
Since efuse_wr_disable is a system parameter as well, it also determines whether itself is
write-protected.

If a system parameter is not write-protected, its unprogrammed bits can be programmed from 0 to 1. The bits
previously programmed to 1 will remain 1. When a system parameter is write-protected, none of its bits can be
programmed: The unprogrammed bits will always remain 0 and the programmed bits will always remain 1.

The write-protection status of each system parameter corresponds to a bit in efuse_wr_disable. When the
corresponding bit is set to 0, the system parameter is not write-protected. When the corresponding bit is set
to 1, the system parameter is write-protected. If a system parameter is already write-protected, it will remain
write-protected. The column entitled “Program-Protection by efuse_wr_disable” in Table 5.3-1 lists the
corresponding bits that determine the write-protection status of each system parameter.

5.3.1.2 System Parameter efuse_rd_disable

Of the 33 system parameters, 27 are not constrained by software-read-protection. These are marked by “-” in
the column entitled “Software-Read-Protection by efuse_rd_disable” in Table 5.3-1. Those system parameters,
some of which are used by software and hardware modules at the same time, can be read by software via the
eFuse Controller at any time.

When not software-read-protected, the other six system parameters can both be read by software and used by
hardware modules. When they are software-read-protected, they can only be used by the hardware
modules.

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The column “Software-Read-Protection by efuse_rd_disable” in Table 5.3-1 lists the corresponding bits in
efuse_rd
_disable that determine the software read-protection status of the six system parameters. If a bit in the system
parameter efuse_rd_disable is 0, the system parameter controlled by the bit is not software-read-protected. If
a bit in the system parameter efuse_rd_disable is 1, the system parameter controlled by the bit is
software-read-protected. If a system parameter is software-read-protected, it will remain in this state.

5.3.1.3 System Parameter coding_scheme

As Table 5.3-1 shows, only three system parameters, BLOCK1, BLOCK2, and BLOCK3, have variable bit widths.
Their bit widths are controlled by another system parameter, coding_scheme. Despite their variable bit widths,
BLOCK1, BLOCK2, and BLOCK3 are assigned a fixed number of bits in eFuse. There is an encoding mapping
between these three system parameters and their corresponding stored values in eFuse. For details please
see Table 5.3-2.
Table 5.3-2. BLOCK1/2/3 Encoding

coding_scheme[1:0] Width of BLOCK1/2/3 Coding scheme Number of bits in eFuse

00/11 256 None 256
01 192 3/4 256
10 128 Repeat 256

The three coding schemes are explained as follows:

• BLOCKN represents any of the following three system parameters: BLOCK1, BLOCK2 or BLOCK3.

• BLOCKN [255 : 0], BLOCKN [191 : 0], and BLOCKN [127 : 0] represent each bit of the three system
parameters in the three encoding schemes.

• e BLOCKN[255 : 0] represents each corresponding bit of those system parameters in eFuse after being
encoded.

None
e
BLOCKN [255 : 0] = BLOCKN [255 : 0]
3/4

BLOCKNij [7 : 0] = BLOCKN [48i + 8j + 7 : 48i + 8j] i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5}

e
BLOCKNij [7 : 0] = eBLOCKN [64i + 8j + 7 : 64i + 8j] i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5, 6, 7}

For i ∈ {0, 1, 2, 3},



 j
j ∈ {0, 1, 2, 3, 4, 5}
BLOCKNi [7 : 0]








 BLOCKNi0 [7 : 0] ⊕ BLOCKNi1 [7 : 0]


BLOCKNij [7 : 0] = BLOCKNi2 [7 : 0] ⊕ BLOCKNi3 [7 : 0]



 BLOCKNi4 [7 : 0] ⊕ BLOCKNi5 [7 : 0]

 j=6





 P5 P7

 (l + 1) BLOCKNil [k], j=7
l=0 k=0

⊕ denotes bitwise XOR

X
and + denote addition

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Repeat
e
BLOCKN [255 : 128] = eBLOCKN [127 : 0] = BLOCKN [127 : 0]

5.3.1.4 BLK3_part_reserve
System parameters coding_scheme, BLOCK1, BLOCK2, and BLOCK3 are controlled by the parameter
BLK3_part_reserve.

When the value of BLK3_part_reserve is 0, coding_scheme, BLOCK1, BLOCK2, and BLOCK3 can be set to any
value.

When the value of BLK3_part_reserve is 1, coding_scheme, BLOCK1, BLOCK2 and BLOCK3 are controlled by
3/4 coding scheme. Meanwhile, BLOCK3[143 : 96], namely, e BLOCK3[191 : 128] is unavailable.

5.3.2 Programming of System Parameters

The programming of variable-length system parameters BLOCK1, BLOCK2, and BLOCK3 is different from that of
the fixed-length system parameters. We program the e BLOCKN[255 : 0] value of encoded system parameters
BLOCK1, BLOCK2, and BLOCK3 instead of directly programming the system parameters. The bit width of
e
BLOCKN[255 : 0] is always 256. Fixed-length system parameters, in contrast, are programmed without
encoding them first.

Each bit of the 30 fixed-length system parameters and the three encoded variable-length system parameters
corresponds to a program register bit, as shown in Table 5.3-3. The register bits will be used when
programming system parameters.

Table 5.3-3. Program Registers

System parameter Register

Name Width Bit Name Bit
efuse_wr_disable 16 [15:0] [15:0]
efuse_rd_disable 4 [3:0] EFUSE_BLK0_WDATA0_REG [19:16]
flash_crypt_cnt
7 [6:0] [26:20]
uart_download_dis 1 [0] [27]
[31:0] EFUSE_BLK0_WDATA1_REG [31:0]
WIFI_MAC_Address 56
[55:32] EFUSE_BLK0_WDATA2_REG [23:0]
disable_app_cpu 1 [0] [0]
disable_bt 1 [0] [1]
pkg_version 4 [3:0] [2], [11:9]
disable_cache 1 [0] EFUSE_BLK0_WDATA3_REG [3]
SPI_pad_config_hd 5 [4:0] [8:4]
BLK3_part_reserve 1 [0] [14]
CK8M Frequency 8 [7:0] [7:0]
XPD_SDIO_REG 1 [0] [14]
EFUSE_BLK0_WDATA4_REG
SDIO_TIEH 1 [0] [15]
sdio_force 1 [0] [16]
SPI_pad_config_clk 5 [4:0] [4:0]
SPI_pad_config_q 5 [4:0] [9:5]

EFUSE_BLK0_WDATA5_REG
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System parameter Register

Name Width Bit Name Bit
SPI_pad_config_d 5 [4:0] [14:10]
SPI_pad_config_cs0 5 [4:0] [19:15]
vol_level_hp_inv 2 [1:0] [23:22]
dig_vol_l6 4 [3:0] [27:24]
flash_crypt_config 4 [3:0] [31:28]
coding_scheme 2 [1:0] [1:0]
console_debug_disable 1 [0] [2]
abstract_done_0 1 [0] [4]
abstract_done_1 1 [0] [5]
JTAG_disable 1 [0] EFUSE_BLK0_WDATA6_REG [6]
download_dis_encrypt 1 [0] [7]
download_dis_decrypt 1 [0] [8]
download_dis_cache 1 [0] [9]
key_status 1 [0] [10]
BLOCK1 256/192/128 [31:0] EFUSE_BLK1_WDATA0_REG [31:0]
[63:32] EFUSE_BLK1_WDATA1_REG [31:0]
[95:64] EFUSE_BLK1_WDATA2_REG [31:0]
[127:96] EFUSE_BLK1_WDATA3_REG [31:0]
[159:128] EFUSE_BLK1_WDATA4_REG [31:0]
[191:160] EFUSE_BLK1_WDATA5_REG [31:0]
[223:192] EFUSE_BLK1_WDATA6_REG [31:0]
[255:224] EFUSE_BLK1_WDATA7_REG [31:0]
[31:0] EFUSE_BLK2_WDATA0_REG [31:0]
[63:32] EFUSE_BLK2_WDATA1_REG [31:0]
[95:64] EFUSE_BLK2_WDATA2_REG [31:0]
[127:96] EFUSE_BLK2_WDATA3_REG [31:0]
BLOCK2 256/192/128
[159:128] EFUSE_BLK2_WDATA4_REG [31:0]
[191:160] EFUSE_BLK2_WDATA5_REG [31:0]
[223:192] EFUSE_BLK2_WDATA6_REG [31:0]
[255:224] EFUSE_BLK2_WDATA7_REG [31:0]
[31:0] EFUSE_BLK3_WDATA0_REG [31:0]
[63:32] EFUSE_BLK3_WDATA1_REG [31:0]
[95:64] EFUSE_BLK3_WDATA2_REG [31:0]
[127:96] EFUSE_BLK3_WDATA3_REG [31:0]
BLOCK3 256/192/128
[159:128] EFUSE_BLK3_WDATA4_REG [31:0]
[191:160] EFUSE_BLK3_WDATA5_REG [31:0]
[223:192] EFUSE_BLK3_WDATA6_REG [31:0]
[255:224] EFUSE_BLK3_WDATA7_REG [31:0]

The process of programming system parameters is as follows:

1. Configure EFUSE_CLK_SEL0 bit, EFUSE_CLK_SEL1 bit of register EFUSE_CLK, and

EFUSE_DAC_CLK_DIV bit of register EFUSE_DAC_CONF.

2. Set the corresponding register bit of the system parameter bit to be programmed to 1.

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3. Write 0x5A5A into register EFUSE_CONF.

4. Write 0x2 into register EFUSE_CMD.

5. Poll register EFUSE_CMD until it is 0x0, or wait for a program-done interrupt.

6. Write 0x5AA5 into register EFUSE_CONF.

7. Write 0x1 into register EFUSE_CMD.

8. Poll register EFUSE_CMD until it is 0x0, or wait for a read-done interrupt.

9. Set the corresponding register bit of the programmed bit to 0.

The configuration values of the EFUSE_CLK_SEL0 bit, EFUSE_CLK_SEL1 bit of register EFUSE_CLK, and the
EFUSE_DAC_CLK_DIV bit of register EFUSE_DAC_CONF are based on the current APB_CLK frequency, as is
shown in Table 5.3-4.

Table 5.3-4. Timing Configuration

APB_CLK Frequency
Register Configuration Value
26 MHz 40 MHz 80 MHz
EFUSE_CLK_SEL0[7:0] 250 160 80
EFUSE_CLK
EFUSE_CLK_SEL1[7:0] 255 255 128
EFUSE_DAC_CONF EFUSE_DAC_CLK_DIV[7:0] 52 80 100

The two methods to identify the generation of program/read-done interrupts are as follows:

Method One:

1. Poll bit 1/0 in register EFUSE_INT_RAW until bit 1/0 is 1, which represents the generation of an
program/read-done interrupt.

2. Set the bit 1/0 in register EFUSE_INT_CLR to 1 to clear the program/read-done interrupts.

Method Two:

1. Set bit 1/0 in register EFUSE_INT_ENA to 1 to enable eFuse Controller to post a program/read-done
interrupt.

2. Configure Interrupt Matrix to enable the CPU to respond to an EFUSE_INT interrupt.

3. A program/read-done interrupt is generated.

4. Read bit 1/0 in register EFUSE_INT_ST to identify the generation of the program/read-done interrupt.

5. Set bit 1/0 in register EFUSE_INT_CLR to 1 to clear the program/read-done interrupt.

The programming of different system parameters and even the programming of different bits of the same
system parameter can be completed separately in multiple programmings. It is, however, recommended that
users minimize programming cycles, and program all the bits that need to be programmed in a system
parameter in one programming action. In addition, after all system parameters controlled by a certain bit of
efuse_wr_disable are programmed, that bit should be immediately programmed. The programming of system
parameters controlled by a certain bit of efuse_wr_disable, and the programming of that bit can even be
completed at the same time. Repeated programming of programmed bits is strictly forbidden.

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5.3.3 Software Reading of System Parameters

Each bit of the 30 fixed-length system parameters and the three variable-length system parameters
corresponds to a software-read register bit, as shown in Table 5.3-5. Software can use the value of each
system parameter by reading the value in the corresponding register.

The bit width of system parameters BLOCK1, BLOCK2, and BLOCK3 is variable. Although 256 register bits have
been assigned to each of the three parameters, as shown in Table 5.3-5, some of the 256 register bits are
useless in the 3/4 coding and the Repeat coding scheme. In the None coding scheme, the corresponding
register bit of each bit of BLOCKN [255 : 0] is used. In the 3/4 coding scheme, only the corresponding
register bits of BLOCKN [191 : 0] are useful. In Repeat coding scheme, only the corresponding bits of
BLOCKN [127 : 0] are useful. In different coding schemes, the values of useless register bits read by
software are invalid. The values of useful register bits read by software are the system parameters BLOCK1,
BLOCK2, and BLOCK3 themselves instead of their values after being encoded.

Table 5.3-5. Software Read Registers

System parameter Register

Name Bit Width Bit Name Bit
efuse_wr_disable 16 [15:0] [15:0]
efuse_rd_disable 4 [3:0] [19:16]
EFUSE_BLK0_RDATA0_REG
flash_crypt_cnt
7 [6:0] [26:20]
uart_download_dis 1 [0] [27]
[31:0] EFUSE_BLK0_RDATA1_REG [31:0]
WIFI_MAC_Address 56
[55:32] EFUSE_BLK0_RDATA2_REG [23:0]
disable_app_cpu 1 [0] [0]
disable_bt 1 [0] [1]
pkg_version 4 [3:0] [2], [11:9]
disable_cache 1 [0] EFUSE_BLK0_RDATA3_REG [3]
SPI_pad_config_hd 5 [4:0] [8:4]
BLK3_part_reserve 1 [0] [14]
CK8M Frequency 8 [7:0] [7:0]
XPD_SDIO_REG 1 [0] [14]
EFUSE_BLK0_RDATA4_REG
SDIO_TIEH 1 [0] [15]
sdio_force 1 [0] [16]
SPI_pad_config_clk 5 [4:0] [4:0]
SPI_pad_config_q 5 [4:0] [9:5]
SPI_pad_config_d 5 [4:0] [14:10]
SPI_pad_config_cs0 5 [4:0] EFUSE_BLK0_RDATA5_REG [19:15]
vol_level_hp_inv 2 [1:0] [23:22]
dig_vol_l6 4 [3:0] [27:24]
flash_crypt_config 4 [3:0] [31:28]
coding_scheme 2 [1:0] [1:0]
console_debug_disable 1 [0] [2]
abstract_done_0 1 [0] [4]
abstract_done_1 1 [0] [5]
EFUSE_BLK0_RDATA6_REG

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System parameter Register

Name Bit Width Bit Name Bit
JTAG_disable 1 [0] [6]
download_dis_encrypt 1 [0] [7]
download_dis_decrypt 1 [0] [8]
download_dis_cache 1 [0] [9]
key_status 1 [0] [10]

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System parameter Register

Name Bit Width Bit Name Bit
[31:0] EFUSE_BLK1_RDATA0_REG [31:0]
[63:32] EFUSE_BLK1_RDATA1_REG [31:0]
[95:64] EFUSE_BLK1_RDATA2_REG [31:0]
[127:96] EFUSE_BLK1_RDATA3_REG [31:0]
BLOCK1 256/192/128
[159:128] EFUSE_BLK1_RDATA4_REG [31:0]
[191:160] EFUSE_BLK1_RDATA5_REG [31:0]
[223:192] EFUSE_BLK1_RDATA6_REG [31:0]
[255:224] EFUSE_BLK1_RDATA7_REG [31:0]
BLOCK2 256/192/128 [31:0] EFUSE_BLK2_RDATA0_REG [31:0]
[63:32] EFUSE_BLK2_RDATA1_REG [31:0]
[95:64] EFUSE_BLK2_RDATA2_REG [31:0]
[127:96] EFUSE_BLK2_RDATA3_REG [31:0]
[159:128] EFUSE_BLK2_RDATA4_REG [31:0]
[191:160] EFUSE_BLK2_RDATA5_REG [31:0]
[223:192] EFUSE_BLK2_RDATA6_REG [31:0]
[255:224] EFUSE_BLK2_RDATA7_REG [31:0]
[31:0] EFUSE_BLK3_RDATA0_REG [31:0]
[63:32] EFUSE_BLK3_RDATA1_REG [31:0]
[95:64] EFUSE_BLK3_RDATA2_REG [31:0]
[127:96] EFUSE_BLK3_RDATA3_REG [31:0]
BLOCK3 256/192/128
[159:128] EFUSE_BLK3_RDATA4_REG [31:0]
[191:160] EFUSE_BLK3_RDATA5_REG [31:0]
[223:192] EFUSE_BLK3_RDATA6_REG [31:0]
[255:224] EFUSE_BLK3_RDATA7_REG [31:0]

5.3.4 The Use of System Parameters by Hardware Modules

Hardware modules are directly hardwired to the ESP32 in order to use the system parameters. Software cannot
change this behaviour. Hardware modules use the decoded values of system parameters BLOCK1, BLOCK2,
and BLOCK3, not their encoded values.

5.3.5 Interrupts
• EFUSE_PGM_DONE_INT: Triggered when eFuse programming has finished.

• EFUSE_READ_DONE_INT: Triggered when eFuse reading has finished.

5.4 Register Summary

The addresses in this section are relative to the eFuse Controller base address provided in Table 3.3-6
Peripheral Address Mapping in Chapter 3 System and Memory.

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Name Description Address Access

eFuse data read registers
EFUSE_BLK0_RDATA0_REG Returns data word 0 in eFuse BLOCK 0 0x3FF5A000 RO
EFUSE_BLK0_RDATA1_REG Returns data word 1 in eFuse BLOCK 0 0x3FF5A004 RO
EFUSE_BLK0_RDATA2_REG Returns data word 2 in eFuse BLOCK 0 0x3FF5A008 RO
EFUSE_BLK0_RDATA3_REG Returns data word 3 in eFuse BLOCK 0 0x3FF5A00C RO
EFUSE_BLK0_RDATA4_REG Returns data word 4 in eFuse BLOCK 0 0x3FF5A010 RO
EFUSE_BLK0_RDATA5_REG Returns data word 5 in eFuse BLOCK 0 0x3FF5A014 RO
EFUSE_BLK0_RDATA6_REG Returns data word 6 in eFuse BLOCK 0 0x3FF5A018 RO
EFUSE_BLK1_RDATA0_REG Returns data word 0 in eFuse BLOCK 1 0x3FF5A038 RO
EFUSE_BLK1_RDATA1_REG Returns data word 1 in eFuse BLOCK 1 0x3FF5A03C RO
EFUSE_BLK1_RDATA2_REG Returns data word 2 in eFuse BLOCK 1 0x3FF5A040 RO
EFUSE_BLK1_RDATA3_REG Returns data word 3 in eFuse BLOCK 1 0x3FF5A044 RO
EFUSE_BLK1_RDATA4_REG Returns data word 4 in eFuse BLOCK 1 0x3FF5A048 RO
EFUSE_BLK1_RDATA5_REG Returns data word 5 in eFuse BLOCK 1 0x3FF5A04C RO
EFUSE_BLK1_RDATA6_REG Returns data word 6 in eFuse BLOCK 1 0x3FF5A050 RO
EFUSE_BLK1_RDATA7_REG Returns data word 7 in eFuse BLOCK 1 0x3FF5A054 RO
EFUSE_BLK2_RDATA0_REG Returns data word 0 in eFuse BLOCK 2 0x3FF5A058 RO
EFUSE_BLK2_RDATA1_REG Returns data word 1 in eFuse BLOCK 2 0x3FF5A05C RO
EFUSE_BLK2_RDATA2_REG Returns data word 2 in eFuse BLOCK 2 0x3FF5A060 RO
EFUSE_BLK2_RDATA3_REG Returns data word 3 in eFuse BLOCK 2 0x3FF5A064 RO
EFUSE_BLK2_RDATA4_REG Returns data word 4 in eFuse BLOCK 2 0x3FF5A068 RO
EFUSE_BLK2_RDATA5_REG Returns data word 5 in eFuse BLOCK 2 0x3FF5A06C RO
EFUSE_BLK2_RDATA6_REG Returns data word 6 in eFuse BLOCK 2 0x3FF5A070 RO
EFUSE_BLK2_RDATA7_REG Returns data word 7 in eFuse BLOCK 2 0x3FF5A074 RO
EFUSE_BLK3_RDATA0_REG Returns data word 0 in eFuse BLOCK 3 0x3FF5A078 RO
EFUSE_BLK3_RDATA1_REG Returns data word 1 in eFuse BLOCK 3 0x3FF5A07C RO
EFUSE_BLK3_RDATA2_REG Returns data word 2 in eFuse BLOCK 3 0x3FF5A080 RO
EFUSE_BLK3_RDATA3_REG Returns data word 3 in eFuse BLOCK 3 0x3FF5A084 RO
EFUSE_BLK3_RDATA4_REG Returns data word 4 in eFuse BLOCK 3 0x3FF5A088 RO
EFUSE_BLK3_RDATA5_REG Returns data word 5 in eFuse BLOCK 3 0x3FF5A08C RO
EFUSE_BLK3_RDATA6_REG Returns data word 6 in eFuse BLOCK 3 0x3FF5A090 RO
EFUSE_BLK3_RDATA7_REG Returns data word 7 in eFuse BLOCK 3 0x3FF5A094 RO
eFuse data write registers
EFUSE_BLK0_WDATA0_REG Writes data to word 0 in eFuse BLOCK 0 0x3FF5A01c R/W
EFUSE_BLK0_WDATA1_REG Writes data to word 1 in eFuse BLOCK 0 0x3FF5A020 R/W
EFUSE_BLK0_WDATA2_REG Writes data to word 2 in eFuse BLOCK 0 0x3FF5A024 R/W
EFUSE_BLK0_WDATA3_REG Writes data to word 3 in eFuse BLOCK 0 0x3FF5A028 R/W
EFUSE_BLK0_WDATA4_REG Writes data to word 4 in eFuse BLOCK 0 0x3FF5A02c R/W
EFUSE_BLK0_WDATA5_REG Writes data to word 5 in eFuse BLOCK 0 0x3FF5A030 R/W
EFUSE_BLK0_WDATA6_REG Writes data to word 6 in eFuse BLOCK 0 0x3FF5A034 R/W
EFUSE_BLK1_WDATA0_REG Writes data to word 0 in eFuse BLOCK 1 0x3FF5A098 R/W
EFUSE_BLK1_WDATA1_REG Writes data to word 1 in eFuse BLOCK 1 0x3FF5A09c R/W
EFUSE_BLK1_WDATA2_REG Writes data to word 2 in eFuse BLOCK 1 0x3FF5A0a0 R/W

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Name Description Address Access

EFUSE_BLK1_WDATA3_REG Writes data to word 3 in eFuse BLOCK 1 0x3FF5A0a4 R/W
EFUSE_BLK1_WDATA4_REG Writes data to word 4 in eFuse BLOCK 1 0x3FF5A0a8 R/W
EFUSE_BLK1_WDATA5_REG Writes data to word 5 in eFuse BLOCK 1 0x3FF5A0ac R/W
EFUSE_BLK1_WDATA6_REG Writes data to word 6 in eFuse BLOCK 1 0x3FF5A0b0 R/W
EFUSE_BLK1_WDATA7_REG Writes data to word 7 in eFuse BLOCK 1 0x3FF5A0b4 R/W
EFUSE_BLK2_WDATA0_REG Writes data to word 0 in eFuse BLOCK 2 0x3FF5A0b8 R/W
EFUSE_BLK2_WDATA1_REG Writes data to word 1 in eFuse BLOCK 2 0x3FF5A0bc R/W
EFUSE_BLK2_WDATA2_REG Writes data to word 2 in eFuse BLOCK 2 0x3FF5A0c0 R/W
EFUSE_BLK2_WDATA3_REG Writes data to word 3 in eFuse BLOCK 2 0x3FF5A0c4 R/W
EFUSE_BLK2_WDATA4_REG Writes data to word 4 in eFuse BLOCK 2 0x3FF5A0c8 R/W
EFUSE_BLK2_WDATA5_REG Writes data to word 5 in eFuse BLOCK 2 0x3FF5A0cc R/W
EFUSE_BLK2_WDATA6_REG Writes data to word 6 in eFuse BLOCK 2 0x3FF5A0d0 R/W
EFUSE_BLK2_WDATA7_REG Writes data to word 7 in eFuse BLOCK 2 0x3FF5A0d4 R/W
EFUSE_BLK3_WDATA0_REG Writes data to word 0 in eFuse BLOCK 3 0x3FF5A0d8 R/W
EFUSE_BLK3_WDATA1_REG Writes data to word 1 in eFuse BLOCK 3 0x3FF5A0dc R/W
EFUSE_BLK3_WDATA2_REG Writes data to word 2 in eFuse BLOCK 3 0x3FF5A0e0 R/W
EFUSE_BLK3_WDATA3_REG Writes data to word 3 in eFuse BLOCK 3 0x3FF5A0e4 R/W
EFUSE_BLK3_WDATA4_REG Writes data to word 4 in eFuse BLOCK 3 0x3FF5A0e8 R/W
EFUSE_BLK3_WDATA5_REG Writes data to word 5 in eFuse BLOCK 3 0x3FF5A0ec R/W
EFUSE_BLK3_WDATA6_REG Writes data to word 6 in eFuse BLOCK 3 0x3FF5A0f0 R/W
EFUSE_BLK3_WDATA7_REG Writes data to word 7 in eFuse BLOCK 3 0x3FF5A0f4 R/W
Control registers
EFUSE_CLK_REG Timing configuration register 0x3FF5A0F8 R/W
EFUSE_CONF_REG Opcode register 0x3FF5A0FC R/W
EFUSE_CMD_REG Read/write command register 0x3FF5A104 R/W
Interrupt registers
EFUSE_INT_RAW_REG Raw interrupt status 0x3FF5A108 RO
EFUSE_INT_ST_REG Masked interrupt status 0x3FF5A10C RO
EFUSE_INT_ENA_REG Interrupt enable bits 0x3FF5A110 R/W
EFUSE_INT_CLR_REG Interrupt clear bits 0x3FF5A114 WO
Misc registers
EFUSE_DAC_CONF_REG Efuse timing configuration 0x3FF5A118 R/W
EFUSE_DEC_STATUS_REG Status of 3/4 coding scheme 0x3FF5A11C RO

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5.5 Registers
The addresses in this section are relative to the eFuse Controller base address provided in Table 3.3-6
Peripheral Address Mapping in Chapter 3 System and Memory.

Register 5.1. EFUSE_BLK0_RDATA0_REG (0x000)

D IS

T
D_

CN
OA

S
T_

DI
I
NL

_D
P

R_
RY
OW

RD

W
_C

E_

E_
_D

SH

US

US
RT

LA
A

F
_U

_E

_E
_F
RD

RD

RD

RD
d)
ve

E_

E_

E_

E_
r

US

US

US

US
se
(re

EF

EF

EF

EF
31 28 27 26 20 19 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_UART_DOWNLOAD_DIS This bit returns the value of uart_download_dis. Valid only for
ESP32 . (RO)

EFUSE_RD_FLASH_CRYPT_CNT This field returns the value of flash_crypt_cnt. (RO)

EFUSE_RD_EFUSE_RD_DIS This field returns the value of efuse_rd_disable. (RO)

EFUSE_RD_EFUSE_WR_DIS This field returns the value of efuse_wr_disable. (RO)

Register 5.2. EFUSE_BLK0_RDATA1_REG (0x004)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_BLK0_RDATA1_REG This field returns the value of the lower 32 bits of WIFI_MAC_Address.
(RO)

Register 5.3. EFUSE_BLK0_RDATA2_REG (0x008)

H
IG
_H
RC
_C
AC
M
I_
IF
W
D_
)
ed

_R
rv

E
US
se
(re

EF

31 24 23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_WIFI_MAC_CRC_HIGH This field returns the value of the higher 24 bits of

WIFI_MAC_Address. (RO)

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Register 5.4. EFUSE_BLK0_RDATA3_REG (0x00c)

U
CP
HE
D

P_
_H

HI ER KG AC

AP
DI BT
IG

_C P_V _P _C
NF

R_ S_
S_
G

RD HI ER IS
PK

VE DI
CO

E_ _C _V D
R_

P_ _
D_

US RD HI ER
E

PA
_V

EF E_ _C P_V
IP

P
I_

US RD HI
CH

SP

EF E_ _C
D_

D_

US RD
)
ed

_R
E_

EF E_
rv

SE
US

US
se

U
(re

EF

EF

EF
31 12 11 9 8 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_CHIP_VER_PKG These are the first three identification bits of chip packaging version
among the four identification bits. (RO)

EFUSE_RD_SPI_PAD_CONFIG_HD This field returns the value of SPI_pad_config_hd. (RO)

EFUSE_RD_CHIP_VER_DIS_CACHE Disables cache. (RO)

EFUSE_RD_CHIP_VER_PKG This is the fourth identification bit of chip packaging version among the
four identification bits. (RO)

EFUSE_RD_CHIP_VER_DIS_BT Disables Bluetooth. (RO)

EFUSE_RD_CHIP_VER_DIS_APP_CPU Disables APP CPU. (RO)

Register 5.5. EFUSE_BLK0_RDATA4_REG (0x010)

Q
PD TIE E

RE
_X O_ RC
_S H
O

_F
RD DI FO

DI

8M
E_ _S O_

K
US RD DI

_C
EF SE_ _S

RD
U RD
)

)
ed

ed

E_
EF SE_
rv

rv

S
FU
se

se
U
(re

(re

ES
EF

31 17 16 15 14 13 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_SDIO_FORCE This field returns the value of sdio_force. (RO)

EFUSE_RD_SDIO_TIEH This field returns the value of SDIO_TIEH. (RO)

EFUSE_RD_XPD_SDIO This field returns the value of XPD_SDIO_REG. (RO)

ESFUSE_RD_CK8M_FREQ RC_FAST_CLK frequency. (RO)

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Register 5.6. EFUSE_BLK0_RDATA5_REG (0x014)

IG

LK
CS
NF

_D

_C
NV

G_

G_
CO

IG

IG
_I

I
HP

NF

NF

NF

NF
T_
P

CO

CO

CO

CO
L_
6
RY

_L

VE

D_

D_

D_

D_
_C

OL

LE

PA

PA

PA

PA
H

_V

L_
AS

I_

I_

I_

I_
IG

SP

P
O
FL

_D

_S

_S

_S
_V
D_

D_
RD

RD

RD

RD

RD
d)
R

R
ve
E_

E_

E_

E_

E_

E_

E_
r
US

US

US

US

US

US

US
se
(re
EF

EF

EF

EF

EF

EF

EF
31 28 27 24 23 22 21 20 19 15 14 10 9 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_FLASH_CRYPT_CONFIG This field returns the value of flash_crypt_config. (RO)

EFUSE_RD_DIG_VOL_L6 This field stores the difference between the digital regulator voltage at
level 6 and 1.2 V. (RO)

EFUSE_RD_VOL_LEVEL_HP_INV This field stores the voltage level for CPU to run at 240 MHz, or
for flash/PSRAM to run at 80 MHz. 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)

EFUSE_RD_SPI_PAD_CONFIG_CS0 This field returns the value of SPI_pad_config_cs0. (RO)

EFUSE_RD_SPI_PAD_CONFIG_D This field returns the value of SPI_pad_config_d. (RO)

EFUSE_RD_SPI_PAD_CONFIG_Q This field returns the value of SPI_pad_config_q. (RO)

EFUSE_RD_SPI_PAD_CONFIG_CLK This field returns the value of SPI_pad_config_clk. (RO)

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Register 5.7. EFUSE_BLK0_RDATA6_REG (0x018)

E
BL
SA
T
EF rve _A S_D _JT ENC YPT
YP

DI
(re SE_ _A AB _DL DEC E

US d) BS O AG R

G_
U RD IS LE _ H
se RD B LE _ R
EF SE_ _D AB _DL CAC

E
G_ BU

M
HE
0
U RD IS LE _

E
ON _1
E_

OD E_D
EF SE_ _D AB _DL
EF SE_ _D AB US

SC
_D NE
U RD IS TAT
U RD IS LE

_C OL
IN
EF E_ _D _S

RD NS
US RD EY

O
_C
EF SE_ _K
U RD

RD
d)
ve

EF SE_

E_

E_
r

US
se

U
(re

EF

EF
31 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_RD_KEY_STATUS This field returns the value of key_status. (RO)

EFUSE_RD_DISABLE_DL_CACHE This field returns the value of download_dis_cache. (RO)

EFUSE_RD_DISABLE_DL_DECRYPT This field returns the value of download_dis_decrypt. (RO)

EFUSE_RD_DISABLE_DL_ENCRYPT This field returns the value of download_dis_encrypt. (RO)

EFUSE_RD_DISABLE_JTAG This field returns the value of JTAG_disable. (RO)

EFUSE_RD_ABS_DONE_1 This field returns the value of abstract_done_1. (RO)

EFUSE_RD_ABS_DONE_0 This field returns the value of abstract_done_0. (RO)

EFUSE_RD_CONSOLE_DEBUG_DISABLE This field returns the value of console_debug_disable.

(RO)

EFUSE_RD_CODING_SCHEME This field returns the value of coding_scheme. (RO)

Register 5.8. EFUSE_BLK0_WDATA0_REG (0x01c)

D IS

T
D_

CN
OA

T_
NL

YP
OW

CR
H_
D

S
IS

DI
T_

D
AS

R_
D_
AR
)

FL
ed

_W
_U

_R
E_
rv

E
US

US

US

US
se
(re

EF

EF

EF

EF

31 28 27 26 20 19 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_UART_DOWNLOAD_DIS This bit programs the value of uart_download_dis. Valid only for
ESP32 ECO V3. (R/W)

EFUSE_FLASH_CRYPT_CNT This field programs the value of flash_crypt_cnt. (R/W)

EFUSE_RD_DIS This field programs the value of efuse_rd_disable. (R/W)

EFUSE_WR_DIS This field programs the value of efuse_wr_disable. (R/W)

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Register 5.9. EFUSE_BLK0_WDATA1_REG (0x020)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_BLK0_WDATA1_REG This field programs the value of lower 32 bits of WIFI_MAC_Address.

(R/W)

Register 5.10. EFUSE_BLK0_WDATA2_REG (0x024)

H
H IG
R C_
_C
AC
M
I_
IF
)
ed

W
E_
rv

US
se
(re

EF
31 24 23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_WIFI_MAC_CRC_HIGH This field programs the value of higher 24 bits of

WIFI_MAC_Address. (R/W)

Register 5.11. EFUSE_BLK0_WDATA3_REG (0x028)

PU
E

_C
D

IP R_ G CH
_H

PP
IS T
CH _VE PK CA
IG

_D _B
_A
NF

E_ IP R_ S_
KG

ER IS
US CH VE DI
CO

_V D
P
R_

EF E_ IP_ R_
D_
VE

US CH VE
PA
P_

EF E_ IP_
I_
HI

US CH
SP
)
ed

_C

E_

EF SE_
rv

E
US

US
se

U
(re

EF

EF

EF

31 12 11 9 8 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_CHIP_VER_PKG These are the first three bits among the four bits to program chip packaging
version. (R/W)

EFUSE_SPI_PAD_CONFIG_HD This field programs the value of SPI_pad_config_hd. (R/W)

EFUSE_CHIP_VER_DIS_CACHE This field is programmed to disable cache. (R/W)

EFUSE_CHIP_VER_PKG This is the fourth bit among the four bits to program chip packaging version.
(R/W)

EFUSE_CHIP_VER_DIS_BT This field is programmed to disable Bluetooth. (R/W)

EFUSE_CHIP_VER_DIS_APP_CPU This field is programmed to disable APP CPU. (R/W)

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Register 5.12. EFUSE_BLK0_WDATA4_REG (0x02c)

EQ
XP _T CE

R
D_ IEH
E_ IO OR

IO

_F
SD
US SD _F

M
K8
EF SE_ IO
U SD

_C
)

)
ed

ed
EF SE_

SE
rv

rv

FU
se

se
U
(re

(re

ES
EF
31 17 16 15 14 13 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_SDIO_FORCE This field programs the value of SDIO_TIEH. (R/W)

EFUSE_SDIO_TIEH This field programs the value of SDIO_TIEH. (R/W)

EFUSE_XPD_SDIO This field programs the value of XPD_SDIO_REG. (R/W)

ESFUSE_CK8M_FREQ This field programs the frequency of RC_FAST_CLK. (R/W)

Register 5.13. EFUSE_BLK0_WDATA5_REG (0x030)

IG

LK
S
NF

_D

_Q
_C

_C
NV
CO

IG

IG

IG

IG
I
P_

NF

NF

NF

NF
T_

_H
P

CO

CO

CO

CO
6
RY

EL
_L

D_

D_

D_

D_
_C

EV
L
VO

PA

PA

PA

PA
SH

_L
G_

I_

I_

I_

I_
LA

SP

SP

SP

SP
VO

)
DI

ed
F
E_

E_

E_

E_

E_

E_

E_
rv
US

US

US

US

US

US

US
se
(re
EF

EF

EF

EF

EF

EF

EF
31 28 27 24 23 22 21 20 19 15 14 10 9 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_FLASH_CRYPT_CONFIG This field programs the value of flash_crypt_config. (R/W)

EFUSE_DIG_VOL_L6 This field stores the difference between the digital regulator voltage at level 6
and 1.2 V. (R/W)

EFUSE_VOL_LEVEL_HP_INV These bits store the voltage level for CPU to run at 240 MHz, or for
flash/PSRAM to run at 80 MHz. 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)

EFUSE_SPI_PAD_CONFIG_CS0 This field programs the value of SPI_pad_config_cs0. (R/W)

EFUSE_SPI_PAD_CONFIG_D This field programs the value of SPI_pad_config_d. (R/W)

EFUSE_SPI_PAD_CONFIG_Q This field programs the value of SPI_pad_config_q. (R/W)

EFUSE_SPI_PAD_CONFIG_CLK This field programs the value of SPI_pad_config_clk. (R/W)

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Register 5.14. EFUSE_BLK0_WDATA6_REG (0x034)

E
BL
EM ISA
T
se AB D TA C T
EF rve S_ ONE G RYP
(re SE_ S_ E_J _EN RYP

CH _D
EF SE_ ISA E_D _DE HE

_S UG
U AB BL L C
U D BL L C

E
EF SE_ ISA E_D _CA

B
_0

DI _DE
US d) DO _1
U D BL L
U D BL S
EF SE_ ISA E_D

NE
EF SE_ ISA ATU

CO LE
NG
U D ST

E_ SO
EF E_ Y_

US ON
US KE
)
ed

C
EF SE_

E_
rv
se

U
(re

EF

EF
31 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_KEY_STATUS This field programs the value of key_status. (R/W)

EFUSE_DISABLE_DL_CACHE This field programs the value of download_dis_cache. (R/W)

EFUSE_DISABLE_DL_DECRYPT This field programs the value of download_dis_decrypt. (R/W)

EFUSE_DISABLE_DL_ENCRYPT This field programs the value of download_dis_encrypt. (R/W)

EFUSE_DISABLE_JTAG This field programs the value of JTAG_disable. (R/W)

EFUSE_ABS_DONE_1 This field programs the value of abstract_done_1. (R/W)

EFUSE_ABS_DONE_0 This field programs the value of abstract_done_0. (R/W)

EFUSE_CONSOLE_DEBUG_DISABLE This field programs the value of console_debug_disable.

(R/W)

EFUSE_CODING_SCHEME This field programs the value of coding_scheme. (R/W)

Register 5.15. EFUSE_BLK1_RDATAn_REG (n: 0-7) (0x38+4*n)

31 0

0x000000000 Reset

EFUSE_BLK1_RDATAn_REG This field returns the value of word n in BLOCK1. (RO)

Register 5.16. EFUSE_BLK2_RDATAn_REG (n: 0-7) (0x58+4*n)

31 0

0x000000000 Reset

EFUSE_BLK2_RDATAn_REG This field returns the value of word n in BLOCK2. (RO)

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Register 5.17. EFUSE_BLK3_RDATAn_REG (n: 0-7) (0x78+4*n)

31 0

0x000000000 Reset

EFUSE_BLK3_RDATAn_REG This field returns the value of word n in BLOCK3. (RO)

Register 5.18. EFUSE_BLK1_WDATAn_REG (n: 0-7) (0x98+4*n)

31 0

0x000000000 Reset

EFUSE_BLK1_WDATAn_REG This field programs the value of word n in of BLOCK1. (R/W)

Register 5.19. EFUSE_BLK2_WDATAn_REG (n: 0-7) (0xB8+4*n)

31 0

0x000000000 Reset

EFUSE_BLK2_WDATAn_REG This field programs the value of word n in of BLOCK2. (R/W)

Register 5.20. EFUSE_BLK3_WDATAn_REG (n: 0-7) (0xD8+4*n)

31 0

0x000000000 Reset

EFUSE_BLK3_WDATAn_REG This field programs the value of word n in of BLOCK3. (R/W)

Register 5.21. EFUSE_CLK_REG (0x0f8)

0
L1

L
E

SE
_S

K_
LK

L
)
ed

_C

_C
rv

E
US

US
se
(re

EF

EF

31 16 15 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x040 0x052 Reset

EFUSE_CLK_SEL1 eFuse clock configuration field. (R/W)

EFUSE_CLK_SEL0 eFuse clock configuration field. (R/W)

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Register 5.22. EFUSE_CONF_REG (0x0fc)

DE
CO
P_
d)

_O
ve

E
r

US
se
(re

EF
31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset

EFUSE_OP_CODE eFuse operation code register. (R/W)

Register 5.23. EFUSE_CMD_REG (0x104)

D
AD MD
M
_C
RE _C
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_PGM_CMD Set this to 1 to start a program operation. Reverts to 0 when the program oper-
ation is done. (R/W)

EFUSE_READ_CMD Set this to 1 to start a read operation. Reverts to 0 when the read operation is
done. (R/W)

Register 5.24. EFUSE_INT_RAW_REG (0x108)

W
IN AW
RA
E_ T_R
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_PGM_DONE_INT_RAW The raw interrupt status bit for the EFUSE_PGM_DONE_INT inter-
rupt. (RO)

EFUSE_READ_DONE_INT_RAW The raw interrupt status bit for the EFUSE_READ_DONE_INT inter-
rupt. (RO)

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Register 5.25. EFUSE_INT_ST_REG (0x10c)

ST
IN T
E_ T_S
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_PGM_DONE_INT_ST The masked interrupt status bit for the EFUSE_PGM_DONE_INT inter-
rupt. (RO)

EFUSE_READ_DONE_INT_ST The masked interrupt status bit for the EFUSE_READ_DONE_INT in-
terrupt. (RO)

Register 5.26. EFUSE_INT_ENA_REG (0x110)

A
IN NA
EN
E_ T_E
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_PGM_DONE_INT_ENA The interrupt enable bit for the EFUSE_PGM_DONE_INT interrupt.

(R/W)

EFUSE_READ_DONE_INT_ENA The interrupt enable bit for the EFUSE_READ_DONE_INT interrupt.

(R/W)

Register 5.27. EFUSE_INT_CLR_REG (0x114)

R
IN LR
CL
E_ T_C
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_PGM_DONE_INT_CLR Set this bit to clear the EFUSE_PGM_DONE_INT interrupt. (WO)

EFUSE_READ_DONE_INT_CLR Set this bit to clear the EFUSE_READ_DONE_INT interrupt. (WO)

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Register 5.28. EFUSE_DAC_CONF_REG (0x118)

V
DI
K_
CL
C_
DA
)
ed

E_
rv

US
se
(re

EF
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 Reset

EFUSE_DAC_CLK_DIV eFuse timing configuration register. (R/W)

Register 5.29. EFUSE_DEC_STATUS_REG (0x11c)

S
NG
NI
AR
_W
EC
)
ed

_D
rv

E
US
se
(re

EF
31 12 11 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_DEC_WARNINGS If a bit is set in this register, it means some errors were corrected while
decoding the 3/4 encoding scheme. (RO)

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Part III

System Component
Encompassing a range of system-level functionalities, this part describes components related to clocks, GPIO,
timers, watchdogs, interrupt handling, low-power management, and various system registers.

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Chapter 6

IO MUX and GPIO Matrix (GPIO, IO MUX)

6.1 Overview
The ESP32 chip features 34 physical GPIO pins. Each pin can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. The IO MUX ¹, RTC IO MUX and the GPIO matrix are responsible for
routing signals from the peripherals to GPIO pins. Together these systems provide highly configurable
I/O.

Note that the I/O GPIO pins are 0-19, 21-23, 25-27, 32-39, while the output GPIOs are 0-19, 21-23, 25-27,
32-33. GPIO pins 34-39 are input-only.

GPIO20 serves as a valid input and output only on ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to
ESP32-PICO Series Datasheet for more information.

This chapter describes the signal selection and connection between the digital pins (FUN_SEL, IE, OE, WPU,
WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE,
etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO MUX.

Figure 6.1-1. IO MUX, RTC IO MUX and GPIO Matrix Overview

1. The IO MUX contains one register per GPIO pin. Each pin can be configured to perform a “GPIO” function
¹MUX: Multiplexer. The ESP32 chip integrates multiple peripherals that require communication with the outside world. To keep the chip
package size reasonably small, the number of available pins has to be limited. So the only way to route all the incoming and outgoing
signals is through pin multiplexing. Pin muxing is controlled via software programmable registers such as IO_MUX_x_REG.

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(when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed
digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency
digital performance. In this case, the IO MUX is used to connect these pins directly to the peripheral.)

See Section 6.10 for a list of IO MUX functions for each I/O pin.

2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pins.

• For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pin as the input
source.

• For output from the chip: The output signal of each of the 34 GPIO pins can be from one of the 176
peripheral output signals.

See Section 6.9 for a list of GPIO Matrix peripheral signals.

3. RTC IO MUX is used to connect GPIO pins to their low-power and analog functions. Only a subset of
GPIO pins have these optional “RTC” functions.

See Section 6.11 for a list of RTC IO MUX functions.

Figure 6.1-2 shows the internal structure of a pad, which is an electrical interface between the chip logic and
the GPIO pin. The structure is applicable to all 31 GPIO pins and can be controlled using IE, OE, WPU, and WPD
signals.

Figure 6.1-2. Internal Structure of a Pad

• IE: input enable

• OE: output enable

• WPU: internal weak pull-up resistor

• WPD: internal weak pull-down resistor

• Bonding pad: a terminal point of the chip logic used to make a physical connection from the chip die to
GPIO pin in the chip package

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6.2 Peripheral Input via GPIO Matrix

6.2.1 Summary
To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral
signal’s input index (0-18, 23-36, 39-58, 61-90, 95-124, 140-155, 164-181, 190-195, 198-206) from one of the 34
GPIOs (0-19, 21-23, 25-27, 32-39).

The input signal is read from the GPIO pin through the IO MUX. The IO MUX must be configured to set the
chosen pin to “GPIO” function. This causes the GPIO pin input signal to be routed into the GPIO Matrix, which
in turn routes it to the selected peripheral input.

6.2.2 Functional Description

Figure 6.2-1 shows the logic for input selection via GPIO Matrix.

Figure 6.2-1. Peripheral Input via IO MUX, GPIO Matrix

To read GPIO pin X into peripheral signal Y, follow the steps below:

1. Configure the GPIO_FUNCy_IN_SEL_CFG register corresponding to peripheral signal Y in the GPIO

Matrix:

• Set GPIO_SIGy_IN_SEL to enable peripheral signal input via GPIO matrix.

• Set the GPIO_FUNCy_IN_SEL field in this register, corresponding to the GPIO pin X to read from.

2. Configure the GPIO_FUNCx_OUT_SEL_CFG register and clear the GPIO_ENABLE_DATA[x] field

corresponding to GPIO pin X in the GPIO Matrix:

• Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s
output state to be determined always by the GPIO_ENABLE_DATA[x] field.

• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or

GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pin.

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3. Configure the IO MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pin X as follows:

• Set the function field (MCU_SEL) to the IO MUX function corresponding to GPIO X (this is Function
2—numeric value 2—for all pins).

• Enable the input by setting the FUN_IE bit.

• Set or clear the FUN_WPU and FUN_WPD bits, as desired, to enable/disable internal
pull-up/pull-down resistors.

Notes:

• One input pin can be connected to multiple input_signals.

• The input signal can be inverted with GPIO_FUNCy_IN_INV_SEL.

• It is possible to have a peripheral read a constantly low or constantly high input value without connecting
this input to a pin. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a
GPIO number:

– When GPIO_FUNCy_IN_SEL is 0x30, input_signal_x is always 0.

– When GPIO_FUNCy_IN_SEL is 0x38, input_signal_x is always 1.

For example, to connect RMT peripheral channel 0 input signal (RMT_SIG_IN0_IDX, signal index 83) to GPIO
15, please follow the steps below. Note that GPIO 15 is also named the MTDO pin:

1. Set the GPIO_FUNC83_IN_SEL_CFG register field GPIO_FUNC83_IN_SEL value to 15.

2. As this is an input-only signal, set GPIO_FUNC15_OEN_SEL bit in GPIO_FUNC15_OUT_SEL_CFG_REG.

3. Clear bit 15 of GPIO_ENABLE_REG (field GPIO_ENABLE_DATA[15]).

4. Set the IO_MUX_GPIO15 register MCU_SEL field to 2 (GPIO function) and also set the FUN_IE bit (input
mode).

6.2.3 Simple GPIO Input

The GPIO_IN_REG/GPIO_IN1_REG register holds the input values of each GPIO pin.

The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular
peripheral signal. However, it is necessary to enable the input in the IO MUX by setting the FUN_IE bit in the
IO_MUX_x_REG register corresponding to pin X, as mentioned in Section 6.2.2.

6.3 Peripheral Output via GPIO Matrix

6.3.1 Summary
To output a signal from a peripheral via the GPIO Matrix, the GPIO Matrix is configured to route the peripheral
output signal (0-18, 23-37, 61-121, 140-125, 224-228) to one of the 28 GPIOs (0-19, 21-23, 25-27, 32-33).

The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO MUX, which is
configured to set the chosen pin to “GPIO” function. This causes the output GPIO signal to be connected to
the pin.

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Note:
The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from
another GPIO.

6.3.2 Functional Description

One of the 176 output signals can be selected to go through the GPIO matrix into the IO MUX and then to a pin.
Figure 6.3-1 illustrates the configuration.

In GPIO matrix In IO MUX

GPIO_FUNCx_OUT_SEL

signal0_out 0 MCU_SEL
signal1_out 1
signal2_out 2
signal3_out 3

0 (FUNC)
1 (FUNC)
GPIO X out I/O Pad x
2 (GPIO)
GPIOx_out
signal228_out 228

FUN_OE = 1
GPIO_OUT_DATA bit x 256 (0x100)
256sdfsdfasdfgas

Figure 6.3-1. Output via GPIO Matrix

To output peripheral signal Y to particular GPIO pin X, follow these steps:

1. Configure the GPIO_FUNCx_OUT_SEL_CFG register and GPIO_ENABLE_DATA[x] field corresponding to

GPIO X in the GPIO Matrix:

• Set the GPIO_FUNCx_OUT_SEL field in GPIO_FUNCx_OUT_SEL_CFG to the numeric index (Y) of

desired peripheral output signal Y.

• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in the
GPIO_FUNCx_OUT_SEL_CFG register and the GPIO_ENABLE_DATA[x] field in the
GPIO_ENABLE_REG register corresponding to GPIO pin X. To have the output enable signal decided
by internal logic, clear the GPIO_FUNCx_OEN_SEL bit instead.

• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or

GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pin.

2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register corresponding
to GPIO pin X. For push/pull mode (default), clear this bit.

3. Configure the IO MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pin X as follows:

• Set the function field (MCU_SEL) to the IO MUX function corresponding to GPIO X (this is Function
2—numeric value 2—for all pins).

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• Set the FUN_DRV field to the desired value for output strength (0-3). The higher the drive strength,
the more current can be sourced/sunk from the pin.

• If using open drain mode, set/clear the FUN_WPU and FUN_WPD bits to enable/disable the internal
pull-up/down resistors.

Notes:

• The output signal from a single peripheral can be sent to multiple pins simultaneously.

• Only the 28 GPIOs can be used as outputs.

• The output signal can be inverted by setting the GPIO_FUNCx_OUT_INV_SEL bit.

6.3.3 Simple GPIO Output

The GPIO Matrix can also be used for simple GPIO output – setting a bit in the GPIO_OUT_DATA register will
write to the corresponding GPIO pin.

To configure a pin as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a
special peripheral index value (0x100).

6.4 Direct I/O via IO MUX

6.4.1 Summary
Some high speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better
high-frequency digital performance. In this case, the IO MUX is used to connect these pins directly to the
peripheral.

Selecting this option is less flexible than using the GPIO Matrix, as the IO MUX register for each GPIO pin can
only select from a limited number of functions. However, better high-frequency digital performance will be
maintained.

6.4.2 Functional Description

Two registers must be configured in order to bypass the GPIO Matrix for peripheral I/O:

1. IO MUX for the GPIO pin must be set to the required pin function. (Please refer to section 6.10 for a list of
pin functions.)

2. For inputs, the SIG_IN_SEL register must be cleared to route the input directly to the peripheral.

6.5 RTC IO MUX for Low Power and Analog I/O

6.5.1 Summary
18 GPIO pins have low power capabilities (RTC domain) and analog functions which are handled by the RTC
subsystem of ESP32. The IO MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is
used to redirect the I/O to the RTC subsystem.

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When configured as RTC GPIOs, the output pins can still retain the output level value when the chip is in
Deep-sleep mode, and the input pins can wake up the chip from Deep-sleep.

Section 6.11 has a list of RTC_MUX pins and their functions.

6.5.2 Analog Function Description

The RTC function and analog function of RTC_GPIOs can only be selected one at a time. For the RTC_GPIO8
to RTC_GPIO17 pins, their analog outputs can be directed to the IO MUX, controlled by the
RTC_IO_TOUCH_PADn/m_TO_GPIO bit. If the bit is set to 1, the analog output is enabled, allowing the signal to
be routed to IO MUX through analog function. On the other hand, if the bit is set to 0, the input signal from the
pin is output to IO MUX through digital function.

6.6 Light-sleep Mode Pin Functions

Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO MUX
register for a GPIO pin is set to 1, a different set of registers is used to control the pin when the ESP32 is in
Light-sleep mode:

Table 6.6-1. IO_MUX Light-sleep Pin Function Registers

Normal Execution Light-sleep Mode

IO_MUX Function
OR SLP_SEL = 0 AND SLP_SEL = 1
Output Drive Strength FUN_DRV MCU_DRV
Pull-up Resistor FUN_WPU MCU_WPU
Pull-down Resistor FUN_WPD MCU_WPD
Output Enable (From GPIO Matrix _OEN field) MCU_OE

If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep
mode.

6.7 pin Hold Feature

Each IO pin (including the RTC pins) has an individual hold function controlled by a RTC register. When the pin
is set to hold, the state is latched at that moment and will not change no matter how the internal signals
change or how the IO MUX configuration or GPIO configuration is modified. Users can use the hold function
for the pins to retain the pin state through a core reset triggered by watchdog time-out or Deep-sleep
events.

The Hold state of each pin is controlled by the result of OR operation of the pin’s Hold enable signal and the
global Hold enable signal.

• Digital Pins (GPIO18 ~ GPIO19, GPIO21 ~ GPIO23, GPIO25 ~ GPIO27, GPIO32 ~ GPIO39)

– RTCIO_DIG_PAD_HOLD_REG[n], controls the Hold enable signal of each digital pin. See Table 6.13-1
for the bit mapping for the pins.

– RTC_CNTL_DG_PAD_FORCE_HOLD, controls the global Hold signal of all digital pins.

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To use this feature, follow the steps below:

– To maintain the pin’s input/output status in Deep-sleep, set RTCIO_DIG_PAD_HOLD_REG[n] (n = 0 ~

31) before power off. See Table 6.13-1 for the bit mapping for the pins. To disable the Hold function
of each pin after the chip is woken up, clear the bits above.

– Alternatively, set RTC_CNTL_DG_PAD_FORCE_HOLD to hold the values of all digital pins, or set
RTC_CNTL_DG_PAD_FORCE_UNHOLD to disable the hold function of all digital pins.

• RTC Pins (GPIO0 ~ GPIO17)

– RTC_CNTL_HOLD_FORCE_REG[n](n = 0 ~ 17), controls the Hold enable signal of each RTC pins
(GPIO0 ~ GPIO17).

– RTC_CNTL_DG_PAD_FORCE_HOLD, controls the global Hold signal of all RTC pins.

To use this feature, follow the steps below:

– To maintain the pin’s input/output status in Deep-sleep, set RTC_CNTL_HOLD_FORCE_REG[n]. n

ranges from 0 to 17, corresponding to GPIO0 ~ GPIO17, respectively. To disable the Hold function of
each pin after the chip is woken up, clear the bits above.

– Alternatively, set RTC_CNTL_DG_PAD_FORCE_HOLD to hold the values of all RTC pins, or set
RTC_CNTL_DG_PAD_FORCE_UNHOLD to disable the hold function of all RTC pins.

6.8 I/O Pin Power Supplies

Figure 6.8-1 and 6.8-2 show the IO pin power supplies.
VDD3P3_CPU
GPIO21

GPIO22

GPIO19
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39

38

37

VDDA 1 36 GPIO23

LNA_IN 2 35 GPIO18

VDD3P3 3 34 GPIO5

VDD3P3 4 33 SD_DATA_1

SENSOR_VP 5 32 SD_DATA_0

SENSOR_CAPP 6 ESP32 31 SD_CLK

SENSOR_CAPN 7 49 GND 30 SD_CMD

SENSOR_VN 8 29 SD_DATA_3

CHIP_PU 9 28 SD_DATA_2

VDET_1 10 27 GPIO17

VDET_2 11 26 VDD_SDIO

32K_XP 12 25 GPIO16
13

14

15

16

17

18

19

20

21

22

23

24

Analog pads
32K_XN

GPIO25

GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4

Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 6.8-1. ESP32 I/O Pin Power Sources (QFN 6*6, Top View)

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GPIO21

GPIO22
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39
VDDA 1 38 GPIO19

LNA_IN 2 37 VDD3P3_CPU

VDD3P3 3 36 GPIO23

VDD3P3 4 35 GPIO18

SENSOR_VP 5 34 GPIO5

SENSOR_CAPP 6 33 SD_DATA_1

SENSOR_CAPN 7 32 SD_DATA_0
ESP32
49 GND
SENSOR_VN 8 31 SD_CLK

CHIP_PU 9 30 SD_CMD

VDET_1 10 29 SD_DATA_3

VDET_2 11 28 SD_DATA_2

32K_XP 12 27 GPIO17

32K_XN 13 26 VDD_SDIO

GPIO25 14 25 GPIO16
15

16

17

18

19

20

21

22

23

24
Analog pads
GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4 Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 6.8-2. ESP32 I/O Pin Power Sources (QFN 5*5, Top View)

• Pins marked blue are RTC pins that have their individual analog function and can also act as normal
digital IO pins. For details, please see Section 6.11.

• Pins marked yellow and green have digital functions only.

• Pins marked green can be powered externally or internally via VDD_SDIO (see below).

6.8.1 VDD_SDIO Power Domain

VDD_SDIO can source or sink current, allowing this power domain to be powered externally or internally. To
power VDD_SDIO externally, apply the same power supply of VDD3P3_RTC to the VDD_SDIO pin.

Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be
configured to be either 1.8V or the same as VDD3P3_RTC, depending on the state of the MTDI pin at reset – a
high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the
efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the
VDD_SDIO by configuring register bits.

Espressif Systems 122 ESP32 TRM (Version 5.5)

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 Espressif Systems

Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

6.9 Peripheral Signal List
Table 6.9-1 shows the peripheral input/output signals via GPIO matrix.

Please pay attention to the configuration of the bit GPIO_FUNCn_OEN_SEL:

• GPIO_FUNCn_OEN_SEL = 1: the output enable is controlled by the corresponding bit n of GPIO_ENABLE_REG:

– GPIO_ENABLE_REG = 0: output is disabled.

– GPIO_ENABLE_REG = 1: output is enabled.

• GPIO_FUNCn_OEN_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the column “Output Enable of Output Signals” of Table
6.9-1. Note that the signals such as SPIQ_oe can be 1 (1’d1) or 0 (1’d0), depending on the configuration of corresponding peripherals. If it’s 1’d1 in column
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“Output Enable of Output Signals”, it indicates that once GPIO_FUNCn_OEN_SEL is cleared, the output signal is always enabled by default.

Note:
Signals are numbered consecutively, but not all signals are valid.
123

• Only the signals with a name assigned in the column “Input signal” in Table 6.9-1 are valid input signals.

• Only the signals with a name assigned in the column “Output signal” in Table 6.9-1 are valid output signals.

Table 6.9-1. GPIO_Matrix

Signal Same Input Signal Output Enable of

No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*
ESP32 TRM (Version 5.5)

0 SPICLK_in 0 yes SPICLK_out SPICLK_oe

1 SPIQ_in 0 yes SPIQ_out SPIQ_oe
2 SPID_in 0 yes SPID_out SPID_oe
3 SPIHD_in 0 yes SPIHD_out SPIHD_oe

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4 SPIWP_in 0 yes SPIWP_out SPIWP_oe
5 SPICS0_in 0 yes SPICS0_out SPICS0_oe
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

6 SPICS1_in 0 no SPICS1_out SPICS1_oe

7 SPICS2_in 0 no SPICS2_out SPICS2_oe
8 HSPICLK_in 0 yes HSPICLK_out HSPICLK_oe
9 HSPIQ_in 0 yes HSPIQ_out HSPIQ_oe
10 HSPID_in 0 yes HSPID_out HSPID_oe
11 HSPICS0_in 0 yes HSPICS0_out HSPICS0_oe
12 HSPIHD_in 0 yes HSPIHD_out HSPIHD_oe
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13 HSPIWP_in 0 yes HSPIWP_out HSPIWP_oe

14 U0RXD_in 0 yes U0TXD_out 1’d1
15 U0CTS_in 0 yes U0RTS_out 1’d1
16 U0DSR_in 0 no U0DTR_out 1’d1
124

17 U1RXD_in 0 yes U1TXD_out 1’d1

18 U1CTS_in 0 yes U1RTS_out 1’d1
23 I2S0O_BCK_in 0 no I2S0O_BCK_out 1’d1
24 I2S1O_BCK_in 0 no I2S1O_BCK_out 1’d1
25 I2S0O_WS_in 0 no I2S0O_WS_out 1’d1
26 I2S1O_WS_in 0 no I2S1O_WS_out 1’d1
27 I2S0I_BCK_in 0 no I2S0I_BCK_out 1’d1
28 I2S0I_WS_in 0 no I2S0I_WS_out 1’d1
ESP32 TRM (Version 5.5)

29 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out 1’d1

30 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out 1’d1
31 pwm0_sync0_in 0 no sdio_tohost_int_out 1’d1
32 pwm0_sync1_in 0 no pwm0_out0a 1’d1
33 pwm0_sync2_in 0 no pwm0_out0b 1’d1

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34 pwm0_f0_in 0 no pwm0_out1a 1’d1
35 pwm0_f1_in 0 no pwm0_out1b 1’d1
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

36 pwm0_f2_in 0 no pwm0_out2a 1’d1

37 — 0 no pwm0_out2b 1’d1
39 pcnt_sig_ch0_in0 0 no — 1’d1
40 pcnt_sig_ch1_in0 0 no — 1’d1
41 pcnt_ctrl_ch0_in0 0 no — 1’d1
42 pcnt_ctrl_ch1_in0 0 no — 1’d1
43 pcnt_sig_ch0_in1 0 no — 1’d1
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44 pcnt_sig_ch1_in1 0 no — 1’d1
45 pcnt_ctrl_ch0_in1 0 no — 1’d1
46 pcnt_ctrl_ch1_in1 0 no — 1’d1
47 pcnt_sig_ch0_in2 0 no — 1’d1
125

48 pcnt_sig_ch1_in2 0 no — 1’d1
49 pcnt_ctrl_ch0_in2 0 no — 1’d1
50 pcnt_ctrl_ch1_in2 0 no — 1’d1
51 pcnt_sig_ch0_in3 0 no — 1’d1
52 pcnt_sig_ch1_in3 0 no — 1’d1
53 pcnt_ctrl_ch0_in3 0 no — 1’d1
54 pcnt_ctrl_ch1_in3 0 no — 1’d1
55 pcnt_sig_ch0_in4 0 no — 1’d1
ESP32 TRM (Version 5.5)

56 pcnt_sig_ch1_in4 0 no — 1’d1
57 pcnt_ctrl_ch0_in4 0 no — 1’d1
58 pcnt_ctrl_ch1_in4 0 no — 1’d1
61 HSPICS1_in 0 no HSPICS1_out HSPICS1_oe
62 HSPICS2_in 0 no HSPICS2_out HSPICS2_oe

GoBack
63 VSPICLK_in 0 yes VSPICLK_out_mux VSPICLK_oe
64 VSPIQ_in 0 yes VSPIQ_out VSPIQ_oe
 Espressif Systems

Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

65 VSPID_in 0 yes VSPID_out VSPID_oe

66 VSPIHD_in 0 yes VSPIHD_out VSPIHD_oe
67 VSPIWP_in 0 yes VSPIWP_out VSPIWP_oe
68 VSPICS0_in 0 yes VSPICS0_out VSPICS0_oe
69 VSPICS1_in 0 no VSPICS1_out VSPICS1_oe
70 VSPICS2_in 0 no VSPICS2_out VSPICS2_oe
71 pcnt_sig_ch0_in5 0 no ledc_hs_sig_out0 1’d1
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72 pcnt_sig_ch1_in5 0 no ledc_hs_sig_out1 1’d1

73 pcnt_ctrl_ch0_in5 0 no ledc_hs_sig_out2 1’d1
74 pcnt_ctrl_ch1_in5 0 no ledc_hs_sig_out3 1’d1
75 pcnt_sig_ch0_in6 0 no ledc_hs_sig_out4 1’d1
126

76 pcnt_sig_ch1_in6 0 no ledc_hs_sig_out5 1’d1

77 pcnt_ctrl_ch0_in6 0 no ledc_hs_sig_out6 1’d1
78 pcnt_ctrl_ch1_in6 0 no ledc_hs_sig_out7 1’d1
79 pcnt_sig_ch0_in7 0 no ledc_ls_sig_out0 1’d1
80 pcnt_sig_ch1_in7 0 no ledc_ls_sig_out1 1’d1
81 pcnt_ctrl_ch0_in7 0 no ledc_ls_sig_out2 1’d1
82 pcnt_ctrl_ch1_in7 0 no ledc_ls_sig_out3 1’d1
83 rmt_sig_in0 0 no ledc_ls_sig_out4 1’d1
ESP32 TRM (Version 5.5)

84 rmt_sig_in1 0 no ledc_ls_sig_out5 1’d1

85 rmt_sig_in2 0 no ledc_ls_sig_out6 1’d1
86 rmt_sig_in3 0 no ledc_ls_sig_out7 1’d1
87 rmt_sig_in4 0 no rmt_sig_out0 1’d1
88 rmt_sig_in5 0 no rmt_sig_out1 1’d1

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89 rmt_sig_in6 0 no rmt_sig_out2 1’d1
90 rmt_sig_in7 0 no rmt_sig_out3 1’d1
 Espressif Systems

Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

91 — — — rmt_sig_out4 1’d1
92 — — — rmt_sig_out6 1’d1
94 twai_rx 1 no rmt_sig_out7 1’d1
95 I2CEXT1_SCL_in 1 no I2CEXT1_SCL_out 1’d1
96 I2CEXT1_SDA_in 1 no I2CEXT1_SDA_out 1’d1
97 host_card_detect_n_1 0 no host_ccmd_od_pullup_en_n 1’d1
98 host_card_detect_n_2 0 no host_rst_n_1 1’d1
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99 host_card_write_prt_1 0 no host_rst_n_2 1’d1

100 host_card_write_prt_2 0 no gpio_sd0_out 1’d1
101 host_card_int_n_1 0 no gpio_sd1_out 1’d1
102 host_card_int_n_2 0 no gpio_sd2_out 1’d1
127

103 pwm1_sync0_in 0 no gpio_sd3_out 1’d1

104 pwm1_sync1_in 0 no gpio_sd4_out 1’d1
105 pwm1_sync2_in 0 no gpio_sd5_out 1’d1
106 pwm1_f0_in 0 no gpio_sd6_out 1’d1
107 pwm1_f1_in 0 no gpio_sd7_out 1’d1
108 pwm1_f2_in 0 no pwm1_out0a 1’d1
109 pwm0_cap0_in 0 no pwm1_out0b 1’d1
110 pwm0_cap1_in 0 no pwm1_out1a 1’d1
ESP32 TRM (Version 5.5)

111 pwm0_cap2_in 0 no pwm1_out1b 1’d1

112 pwm1_cap0_in 0 no pwm1_out2a 1’d1
113 pwm1_cap1_in 0 no pwm1_out2b 1’d1
114 pwm1_cap2_in 0 no pwm2_out1h 1’d1
115 pwm2_flta 1 no pwm2_out1l 1’d1

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116 pwm2_fltb 1 no pwm2_out2h 1’d1
117 pwm2_cap1_in 0 no pwm2_out2l 1’d1
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

118 pwm2_cap2_in 0 no pwm2_out3h 1’d1

119 pwm2_cap3_in 0 no pwm2_out3l 1’d1
120 pwm3_flta 1 no pwm2_out4h 1’d1
121 pwm3_fltb 1 no pwm2_out4l 1’d1
122 pwm3_cap1_in 0 no — 1’d1
123 pwm3_cap2_in 0 no twai_tx 1’d1
124 pwm3_cap3_in 0 no twai_bus_off_on 1’d1
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125 — — — twai_clkout 1’d1

140 I2S0I_DATA_in0 0 no I2S0O_DATA_out0 1’d1
141 I2S0I_DATA_in1 0 no I2S0O_DATA_out1 1’d1
142 I2S0I_DATA_in2 0 no I2S0O_DATA_out2 1’d1
128

143 I2S0I_DATA_in3 0 no I2S0O_DATA_out3 1’d1

144 I2S0I_DATA_in4 0 no I2S0O_DATA_out4 1’d1
145 I2S0I_DATA_in5 0 no I2S0O_DATA_out5 1’d1
146 I2S0I_DATA_in6 0 no I2S0O_DATA_out6 1’d1
147 I2S0I_DATA_in7 0 no I2S0O_DATA_out7 1’d1
148 I2S0I_DATA_in8 0 no I2S0O_DATA_out8 1’d1
149 I2S0I_DATA_in9 0 no I2S0O_DATA_out9 1’d1
150 I2S0I_DATA_in10 0 no I2S0O_DATA_out10 1’d1
ESP32 TRM (Version 5.5)

151 I2S0I_DATA_in11 0 no I2S0O_DATA_out11 1’d1

152 I2S0I_DATA_in12 0 no I2S0O_DATA_out12 1’d1
153 I2S0I_DATA_in13 0 no I2S0O_DATA_out13 1’d1
154 I2S0I_DATA_in14 0 no I2S0O_DATA_out14 1’d1
155 I2S0I_DATA_in15 0 no I2S0O_DATA_out15 1’d1

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156 — — — I2S0O_DATA_out16 1’d1
157 — — — I2S0O_DATA_out17 1’d1
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

158 — — — I2S0O_DATA_out18 1’d1

159 — — — I2S0O_DATA_out19 1’d1
160 — — — I2S0O_DATA_out20 1’d1
161 — — — I2S0O_DATA_out21 1’d1
162 — — — I2S0O_DATA_out22 1’d1
163 — — — I2S0O_DATA_out23 1’d1
164 I2S1I_BCK_in 0 no I2S1I_BCK_out 1’d1
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165 I2S1I_WS_in 0 no I2S1I_WS_out 1’d1

166 I2S1I_DATA_in0 0 no I2S1O_DATA_out0 1’d1
167 I2S1I_DATA_in1 0 no I2S1O_DATA_out1 1’d1
168 I2S1I_DATA_in2 0 no I2S1O_DATA_out2 1’d1
129

169 I2S1I_DATA_in3 0 no I2S1O_DATA_out3 1’d1

170 I2S1I_DATA_in4 0 no I2S1O_DATA_out4 1’d1
171 I2S1I_DATA_in5 0 no I2S1O_DATA_out5 1’d1
172 I2S1I_DATA_in6 0 no I2S1O_DATA_out6 1’d1
173 I2S1I_DATA_in7 0 no I2S1O_DATA_out7 1’d1
174 I2S1I_DATA_in8 0 no I2S1O_DATA_out8 1’d1
175 I2S1I_DATA_in9 0 no I2S1O_DATA_out9 1’d1
176 I2S1I_DATA_in10 0 no I2S1O_DATA_out10 1’d1
ESP32 TRM (Version 5.5)

177 I2S1I_DATA_in11 0 no I2S1O_DATA_out11 1’d1

178 I2S1I_DATA_in12 0 no I2S1O_DATA_out12 1’d1
179 I2S1I_DATA_in13 0 no I2S1O_DATA_out13 1’d1
180 I2S1I_DATA_in14 0 no I2S1O_DATA_out14 1’d1
181 I2S1I_DATA_in15 0 no I2S1O_DATA_out15 1’d1

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182 — — — I2S1O_DATA_out16 1’d1
183 — — — I2S1O_DATA_out17 1’d1
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

184 — — — I2S1O_DATA_out18 1’d1

185 — — — I2S1O_DATA_out19 1’d1
186 — — — I2S1O_DATA_out20 1’d1
187 — — — I2S1O_DATA_out21 1’d1
188 — — — I2S1O_DATA_out22 1’d1
189 — — — I2S1O_DATA_out23 1’d1
190 I2S0I_H_SYNC 0 no pwm3_out1h 1’d1
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191 I2S0I_V_SYNC 0 no pwm3_out1l 1’d1

192 I2S0I_H_ENABLE 0 no pwm3_out2h 1’d1
193 I2S1I_H_SYNC 0 no pwm3_out2l 1’d1
194 I2S1I_V_SYNC 0 no pwm3_out3h 1’d1
130

195 I2S1I_H_ENABLE 0 no pwm3_out3l 1’d1

196 — — — pwm3_out4h 1’d1
197 — — — pwm3_out4l 1’d1
198 U2RXD_in 0 yes U2TXD_out 1’d1
199 U2CTS_in 0 yes U2RTS_out 1’d1
200 emac_mdc_i 0 no emac_mdc_o emac_mdc_oe
201 emac_mdi_i 0 no emac_mdo_o emac_mdo_o_e
202 emac_crs_i 0 no emac_crs_o emac_crs_oe
ESP32 TRM (Version 5.5)

203 emac_col_i 0 no emac_col_o emac_col_oe

204 pcmfsync_in 0 no bt_audio0_irq 1’d1
205 pcmclk_in 0 no bt_audio1_irq 1’d1
206 pcmdin 0 no bt_audio2_irq 1’d1
207 — — — ble_audio0_irq 1’d1

GoBack
208 — — — ble_audio1_irq 1’d1
209 — — — ble_audio2_irq 1’d1
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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Same Input Signal Output Enable of
No. Input Signals Default from IO_MUX Core Output Signals Output Signals
Value If
Unassigned*

210 — — — pcmfsync_out pcmfsync_en

211 — — — pcmclk_out pcmclk_en
212 — — — pcmdout pcmdout_en
213 — — — ble_audio_sync0_p 1’d1
214 — — — ble_audio_sync1_p 1’d1
215 — — — ble_audio_sync2_p 1’d1
224 — — — sig_in_func224 1’d1
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225 — — — sig_in_func225 1’d1

226 — — — sig_in_func226 1’d1
227 — — — sig_in_func227 1’d1
228 — — — sig_in_func228 1’d1
131
ESP32 TRM (Version 5.5)

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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

6.10 IO MUX Pin List

Table 6.10-1 shows the IO MUX functions for each I/O pin:

Table 6.10-1. IO_MUX Pin Summary

GPIO Pin Name Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 Reset Notes
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R
1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 -
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R
3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 -
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 -
6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 -
7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 -
8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 -
9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 -
10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 -
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 -
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 2 R
14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 3 R
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R
16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 -
17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 -
18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 -
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 -
21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 -
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 -
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 -
25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R
26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R
27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 0 R
32 32K_XP GPIO32 - GPIO32 - - - 0 R
33 32K_XN GPIO33 - GPIO33 - - - 0 R
34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I
35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I
36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I
37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I
38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I
39 SENSOR_VN GPIO39 - GPIO39 - - - 0 R, I

Reset Configurations

”Reset” column shows each pin’s default configurations after reset:

• 0 - IE=0 (input disabled).

• 1 - IE=1 (input enabled).

• 2 - IE=1, WPD=1 (input enabled, pull-down resistor).

• 3 - IE=1, WPU=1 (input enabled, pull-up resistor).

Notes

• R - Pin has RTC/analog functions via RTC_MUX.

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Chapter 6 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

• I - Pin can only be configured as input GPIO. These input-only pins do not feature an output driver or
internal pull-up/pull-down circuitry.

Please refer to the ESP32 Pin Lists in ESP32 Series Datasheetor more details.

6.11 RTC_MUX Pin List

Table 6.11-1 shows the RTC pins and how they correspond to GPIO pins:

Table 6.11-1. RTC IO MUX Pin Summary

Analog Function RTC Function

RTC GPIO Num GPIO Num Pin Name Function 0 Function 1
0 1 2
(FUN_SEL = 0) (FUN_SEL = 3)
0 36 SENSOR_VP ADC_H ADC1_CH0 - RTC_GPIO0 -
1 37 SENSOR_CAPP ADC_H ADC1_CH1 - RTC_GPIO1 -
2 38 SENSOR_CAPN ADC_H ADC1_CH2 - RTC_GPIO2 -
3 39 SENSOR_VN ADC_H ADC1_CH3 - RTC_GPIO3 -
4 34 VDET_1 - ADC1_CH6 - RTC_GPIO4 -
5 35 VDET_2 - ADC1_CH7 - RTC_GPIO5 -
6 25 GPIO25 DAC_1 ADC2_CH8 - RTC_GPIO6 -
7 26 GPIO26 DAC_2 ADC2_CH9 - RTC_GPIO7 -
8 33 32K_XN XTAL_32K_N ADC1_CH5 TOUCH8 RTC_GPIO8 -
9 32 32K_XP XTAL_32K_P ADC1_CH4 TOUCH9 RTC_GPIO9 -
10 4 GPIO4 - ADC2_CH0 TOUCH0 RTC_GPIO10 I2C_SCL∗
11 0 GPIO0 - ADC2_CH1 TOUCH1 RTC_GPIO11 I2C_SDA∗
12 2 GPIO2 - ADC2_CH2 TOUCH2 RTC_GPIO12 I2C_SCL∗
13 15 MTDO - ADC2_CH3 TOUCH3 RTC_GPIO13 I2C_SDA∗
14 13 MTCK - ADC2_CH4 TOUCH4 RTC_GPIO14 -
15 12 MTDI - ADC2_CH5 TOUCH5 RTC_GPIO15 -
16 14 MTMS - ADC2_CH6 TOUCH6 RTC_GPIO16 -
17 27 GPIO27 - ADC2_CH7 TOUCH7 RTC_GPIO17 -

Note:
For more information on the configuration of sar_i2c_xx, see Section RTC I2C Controller in Chapter 1 ULP Coprocessor
(ULP).

6.12 Register Summary

6.12.1 GPIO Matrix Register Summary

Table 6.12-1. GPIO Matrix Register Summary

Name Description Address Access

GPIO_OUT_REG GPIO 0-31 output register 0x3FF44004 R/W

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Name Description Address Access

GPIO_OUT_W1TS_REG GPIO 0-31 output register_W1TS 0x3FF44008 WO
GPIO_OUT_W1TC_REG GPIO 0-31 output register_W1TC 0x3FF4400C WO
GPIO_OUT1_REG GPIO 32-39 output register 0x3FF44010 R/W
GPIO_OUT1_W1TS_REG GPIO 32-39 output bit set register 0x3FF44014 WO
GPIO_OUT1_W1TC_REG GPIO 32-39 output bit clear register 0x3FF44018 WO
GPIO_ENABLE_REG GPIO 0-31 output enable register 0x3FF44020 R/W
GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable register_W1TS 0x3FF44024 WO
GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable register_W1TC 0x3FF44028 WO
GPIO_ENABLE1_REG GPIO 32-39 output enable register 0x3FF4402C R/W
GPIO_ENABLE1_W1TS_REG GPIO 32-39 output enable bit set register 0x3FF44030 WO
GPIO_ENABLE1_W1TC_REG GPIO 32-39 output enable bit clear register 0x3FF44034 WO
GPIO_STRAP_REG Bootstrap pin value register 0x3FF44038 RO
GPIO_IN_REG GPIO 0-31 input register 0x3FF4403C RO
GPIO_IN1_REG GPIO 32-39 input register 0x3FF44040 RO
GPIO_STATUS_REG GPIO 0-31 interrupt status register 0x3FF44044 R/W
GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS 0x3FF44048 WO
GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC 0x3FF4404C WO
GPIO_STATUS1_REG GPIO 32-39 interrupt status register1 0x3FF44050 R/W
GPIO_STATUS1_W1TS_REG GPIO 32-39 interrupt status bit set register 0x3FF44054 WO
GPIO_STATUS1_W1TC_REG GPIO 32-39 interrupt status bit clear register 0x3FF44058 WO
GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU interrupt status 0x3FF44060 RO
GPIO 0-31 APP_CPU non-maskable interrupt sta-
GPIO_ACPU_NMI_INT_REG 0x3FF44064 RO
tus
GPIO_PCPU_INT_REG GPIO 0-31 PRO_CPU interrupt status 0x3FF44068 RO
GPIO 0-31 PRO_CPU non-maskable interrupt sta-
GPIO_PCPU_NMI_INT_REG 0x3FF4406C RO
tus
GPIO_ACPU_INT1_REG GPIO 32-39 APP_CPU interrupt status 0x3FF44074 RO
GPIO 32-39 APP_CPU non-maskable interrupt
GPIO_ACPU_NMI_INT1_REG 0x3FF44078 RO
status
GPIO_PCPU_INT1_REG GPIO 32-39 PRO_CPU interrupt status 0x3FF4407C RO
GPIO 32-39 PRO_CPU non-maskable interrupt
GPIO_PCPU_NMI_INT1_REG 0x3FF44080 RO
status
GPIO_PIN0_REG Configuration for GPIO pin 0 0x3FF44088 R/W
GPIO_PIN1_REG Configuration for GPIO pin 1 0x3FF4408C R/W
GPIO_PIN2_REG Configuration for GPIO pin 2 0x3FF44090 R/W
... ...
GPIO_PIN38_REG Configuration for GPIO pin 38 0x3FF44120 R/W
GPIO_PIN39_REG Configuration for GPIO pin 39 0x3FF44124 R/W
GPIO_FUNC0_IN_SEL_CFG_REG Peripheral function 0 input selection register 0x3FF44130 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Peripheral function 1 input selection register 0x3FF44134 R/W
... ...
GPIO_FUNC254_IN_SEL_CFG_REG Peripheral function 254 input selection register 0x3FF44528 R/W
GPIO_FUNC255_IN_SEL_CFG_REG Peripheral function 255 input selection register 0x3FF4452C R/W

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Name Description Address Access

GPIO_FUNC0_OUT_SEL_CFG_REG Peripheral output selection for GPIO 0 0x3FF44530 R/W
GPIO_FUNC1_OUT_SEL_CFG_REG Peripheral output selection for GPIO 1 0x3FF44534 R/W
... ...

6.12.2 IO MUX Register Summary

Table 6.12-2. IO MUX Register Summary

Name Description Address Access

IO_MUX_PIN_CTRL Clock output configuration register 0x3FF49000 R/W
IO_MUX_GPIO36_REG Configuration register for GPIO36 0x3FF49004 R/W
IO_MUX_GPIO37_REG Configuration register for GPIO37 0x3FF49008 R/W
IO_MUX_GPIO38_REG Configuration register for GPIO38 0x3FF4900C R/W
IO_MUX_GPIO39_REG Configuration register for GPIO39 0x3FF49010 R/W
IO_MUX_GPIO34_REG Configuration register for GPIO34 0x3FF49014 R/W
IO_MUX_GPIO35_REG Configuration register for GPIO35 0x3FF49018 R/W
IO_MUX_GPIO32_REG Configuration register for GPIO32 0x3FF4901C R/W
IO_MUX_GPIO33_REG Configuration register for GPIO33 0x3FF49020 R/W
IO_MUX_GPIO25_REG Configuration register for GPIO25 0x3FF49024 R/W
IO_MUX_GPIO26_REG Configuration register for GPIO26 0x3FF49028 R/W
IO_MUX_GPIO27_REG Configuration register for GPIO27 0x3FF4902C R/W
IO_MUX_MTMS_REG Configuration register for MTMS 0x3FF49030 R/W
IO_MUX_MTDI_REG Configuration register for MTDI 0x3FF49034 R/W
IO_MUX_MTCK_REG Configuration register for MTCK 0x3FF49038 R/W
IO_MUX_MTDO_REG Configuration register for MTDO 0x3FF4903C R/W
IO_MUX_GPIO2_REG Configuration register for GPIO2 0x3FF49040 R/W
IO_MUX_GPIO0_REG Configuration register for GPIO0 0x3FF49044 R/W
IO_MUX_GPIO4_REG Configuration register for GPIO4 0x3FF49048 R/W
IO_MUX_GPIO16_REG Configuration register for GPIO16 0x3FF4904C R/W
IO_MUX_GPIO17_REG Configuration register for GPIO17 0x3FF49050 R/W
IO_MUX_SD_DATA2_REG Configuration register for SD_DATA2 0x3FF49054 R/W
IO_MUX_SD_DATA3_REG Configuration register for SD_DATA3 0x3FF49058 R/W
IO_MUX_SD_CMD_REG Configuration register for SD_CMD 0x3FF4905C R/W
IO_MUX_SD_CLK_REG Configuration register for SD_CLK 0x3FF49060 R/W
IO_MUX_SD_DATA0_REG Configuration register for SD_DATA0 0x3FF49064 R/W
IO_MUX_SD_DATA1_REG Configuration register for SD_DATA1 0x3FF49068 R/W
IO_MUX_GPIO5_REG Configuration register for GPIO5 0x3FF4906C R/W
IO_MUX_GPIO18_REG Configuration register for GPIO18 0x3FF49070 R/W
IO_MUX_GPIO19_REG Configuration register for GPIO19 0x3FF49074 R/W
1
IO_MUX_GPIO20_REG Configuration register for GPIO20 0x3FF49078 R/W
IO_MUX_GPIO21_REG Configuration register for GPIO21 0x3FF4907C R/W
IO_MUX_GPIO22_REG Configuration register for GPIO22 0x3FF49080 R/W
IO_MUX_U0RXD_REG Configuration register for U0RXD 0x3FF49084 R/W

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Name Description Address Access

IO_MUX_U0TXD_REG Configuration register for U0TXD 0x3FF49088 R/W
IO_MUX_GPIO23_REG Configuration register for GPIO23 0x3FF4908C R/W

1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet
for more information.

6.12.3 RTC IO MUX Register Summary

Table 6.12-3. RTC IO MUX Register Summary

Name Description Address Access

GPIO configuration / data registers
RTCIO_RTC_GPIO_OUT_REG RTC GPIO output register 0x3FF48400 R/W
RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO output bit set register 0x3FF48404 WO
RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO output bit clear register 0x3FF48408 WO
RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO output enable register 0x3FF4840C R/W
RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO output enable bit set register 0x3FF48410 WO
RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO output enable bit clear register 0x3FF48414 WO
RTCIO_RTC_GPIO_STATUS_REG RTC GPIO interrupt status register 0x3FF48418 WO
RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO interrupt status bit set register 0x3FF4841C WO
RTCIO_RTC_GPIO_STATUS_W1TC_REG RTC GPIO interrupt status bit clear register 0x3FF48420 WO
RTCIO_RTC_GPIO_IN_REG RTC GPIO input register 0x3FF48424 RO
RTCIO_RTC_GPIO_PIN0_REG RTC configuration for pin 0 0x3FF48428 R/W
RTCIO_RTC_GPIO_PIN1_REG RTC configuration for pin 1 0x3FF4842C R/W
RTCIO_RTC_GPIO_PIN2_REG RTC configuration for pin 2 0x3FF48430 R/W
RTCIO_RTC_GPIO_PIN3_REG RTC configuration for pin 3 0x3FF48434 R/W
RTCIO_RTC_GPIO_PIN4_REG RTC configuration for pin 4 0x3FF48438 R/W
RTCIO_RTC_GPIO_PIN5_REG RTC configuration for pin 5 0x3FF4843C R/W
RTCIO_RTC_GPIO_PIN6_REG RTC configuration for pin 6 0x3FF48440 R/W
RTCIO_RTC_GPIO_PIN7_REG RTC configuration for pin 7 0x3FF48444 R/W
RTCIO_RTC_GPIO_PIN8_REG RTC configuration for pin 8 0x3FF48448 R/W
RTCIO_RTC_GPIO_PIN9_REG RTC configuration for pin 9 0x3FF4844C R/W
RTCIO_RTC_GPIO_PIN10_REG RTC configuration for pin 10 0x3FF48450 R/W
RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11 0x3FF48454 R/W
RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12 0x3FF48458 R/W
RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13 0x3FF4845C R/W
RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14 0x3FF48460 R/W
RTCIO_RTC_GPIO_PIN15_REG RTC configuration for pin 15 0x3FF48464 R/W
RTCIO_RTC_GPIO_PIN16_REG RTC configuration for pin 16 0x3FF48468 R/W
RTCIO_RTC_GPIO_PIN17_REG RTC configuration for pin 17 0x3FF4846C R/W
RTCIO_DIG_PAD_HOLD_REG RTC GPIO hold register 0x3FF48474 R/W
GPIO RTC function configuration registers
RTCIO_SENSOR_PADS_REG Sensor pins configuration register 0x3FF4847C R/W
RTCIO_ADC_PAD_REG ADC configuration register 0x3FF48480 R/W

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Name Description Address Access

RTCIO_PAD_DAC1_REG DAC1 configuration register 0x3FF48484 R/W
RTCIO_PAD_DAC2_REG DAC2 configuration register 0x3FF48488 R/W
RTCIO_XTAL_32K_PAD_REG 32KHz crystal pins configuration register 0x3FF4848C R/W
RTCIO_TOUCH_CFG_REG Touch sensor configuration register 0x3FF48490 R/W
RTCIO_TOUCH_PAD0_REG Touch pin configuration register 0x3FF48494 R/W
... ...
RTCIO_TOUCH_PAD9_REG Touch pin configuration register 0x3FF484B8 R/W
RTCIO_EXT_WAKEUP0_REG External wake up configuration register 0x3FF484BC R/W
RTCIO_XTL_EXT_CTR_REG Crystal power down enable GPIO source 0x3FF484C0 R/W
RTCIO_SAR_I2C_IO_REG RTC I2C pin selection 0x3FF484C4 R/W

6.13 Registers

6.13.1 GPIO Matrix Registers

The addresses in parenthesis besides register names are the register addresses relative to the GPIO base
address provided in Table 3.3-6 Peripheral Address Mapping in Chapter 3 System and Memory. The absolute
register addresses are listed in Section 6.12.1 GPIO Matrix Register Summary.

Register 6.1. GPIO_OUT_REG (0x0004)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_REG GPIO0-31 output value. (R/W)

Register 6.2. GPIO_OUT_W1TS_REG (0x0008)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here,
the corresponding bit in GPIO_OUT_REG will be set. (WO)

Register 6.3. GPIO_OUT_W1TC_REG (0x000c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)

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Register 6.4. GPIO_OUT1_REG (0x0010)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value. (R/W)

Register 6.5. GPIO_OUT1_W1TS_REG (0x0014)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)

Register 6.6. GPIO_OUT1_W1TC_REG (0x0018)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)

Register 6.7. GPIO_ENABLE_REG (0x0020)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_REG GPIO0-31 output enable. (R/W)

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Register 6.8. GPIO_ENABLE_W1TS_REG (0x0024)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be set. (WO)

Register 6.9. GPIO_ENABLE_W1TC_REG (0x0028)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)

Register 6.10. GPIO_ENABLE1_REG (0x002c)

TA
DA
E_
BL
)

NA
ed

_E
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W)

Register 6.11. GPIO_ENABLE1_W1TS_REG (0x0030)

TA
DA
E_
BL
)

NA
ed

_E
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)

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Register 6.12. GPIO_ENABLE1_W1TC_REG (0x0034)

A
AT
_D
B LE
)

NA
ed

_E
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)

Register 6.13. GPIO_STRAP_REG (0x0038)

NG
PI
AP
)

TR
ed

_S
rv
se

IO
(re

GP
31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Reset

GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI,

GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively.

Register 6.14. GPIO_IN_REG (0x003c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_IN_REG GPIO0-31 input value. Each bit represents a pin input value, 1 for high level and 0 for
low level. (RO)

Register 6.15. GPIO_IN1_REG (0x0040)

E XT
_N
TA
DA
)
ed

N_
rv

_I
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pin input value. (RO)

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Register 6.16. GPIO_STATUS_REG (0x0044)

NT
_I
US
AT
ST
IO_
GP
31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT GPIO0-31 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16
bits in GPIO_PINn_REG should be set to 1. (R/W)

Register 6.17. GPIO_STATUS_W1TS_REG (0x0048)

S
1T
_W
NT
I
S_
TU
TA
_S
IO
GP

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT_W1TS GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be set. (WO)

Register 6.18. GPIO_STATUS_W1TC_REG (0x004c)

C
1T
_W
I NT
S_
TU
TA
_S
IO
GP

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT_W1TC GPIO0-31 interrupt status clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be cleared. (WO)

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Register 6.19. GPIO_STATUS1_REG (0x0050)

NT
_I
S1
TU
)

TA
ed

_S
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT GPIO32-39 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16
bits in GPIO_PINn_REG should be set to 1. (R/W)

Register 6.20. GPIO_STATUS1_W1TS_REG (0x0054)

S
1T
_W
NTI
1_
US
AT
)
ed

ST
rv

O_
se

I
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT_W1TS GPIO32-39 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS1_INT will be set. (WO)

Register 6.21. GPIO_STATUS1_W1TC_REG (0x0058)

C
1T
_W
NT
_I
S1
TU
)

TA
ed

_S
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT_W1TC GPIO32-39 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS1_INT will be cleared. (WO)

Register 6.22. GPIO_ACPU_INT_REG (0x0060)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)

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Register 6.23. GPIO_ACPU_NMI_INT_REG (0x0064)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO)

Register 6.24. GPIO_PCPU_INT_REG (0x0068)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO)

Register 6.25. GPIO_PCPU_NMI_INT_REG (0x006c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO)

Register 6.26. GPIO_ACPU_INT1_REG (0x0074)

NT
I
U_
CP
)

PP
ed

_A
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO)

Register 6.27. GPIO_ACPU_NMI_INT1_REG (0x0078)

T
IN
I_
M
_N
C PU
)

PP
ed

_A
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO)

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Register 6.28. GPIO_PCPU_INT1_REG (0x007c)

T
IN
U_
CP
RO
)
ed

_P
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO)

Register 6.29. GPIO_PCPU_NMI_INT1_REG (0x0080)

T
IN
I_
N M
U_
CP
RO
)
ed

P
rv

O_
se

I
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO)

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Register 6.30. GPIO_PINn_REG (n: 0-19, 21-23, 25-27, 32-39) (0x88+0x4*n)

LE
AB

R
EN

VE
P_

PE

RI
A
EN

EU

_D
TY
T_

T_
AK

AD
IN

IN
W

_P
n_

n_

n_

(re INn
d)

GP ed)

)
ed

ed
IN

IN

IN
ve

_P

_P

_P
rv

rv

rv
O_
r
se

se

se

se
IO

IO

IO
I
(re

(re

(re
GP

GP

GP
31 18 17 13 12 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x 0 0 x x x x 0 0 0 0 x 0 0 Reset

GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W)

bit0: APP CPU interrupt enable;
bit1: APP CPU non-maskable interrupt enable;
bit2: PRO CPU interrupt enable;
bit3: PRO CPU non-maskable interrupt enable.

GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)

GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)

Register 6.31. GPIO_FUNCy_IN_SEL_CFG_REG (y: 0-255) (0x130+0x4*y)

L
SE
V_

L
SE
IN
_I L
Cy SE
N_

N_
UN IN_

_I
Cy
_F _
IO IGy

UN
)
ed

GP _S

_F
rv
se

IO

IO
GP

GP
(re

31 8 7 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_SIGy_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal directly
to peripheral configured in the IO_MUX. (R/W)

GPIO_FUNCy_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)

GPIO_FUNCy_IN_SEL Selection control for peripheral input y. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)

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Register 6.32. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-19, 21-23, 25-27, 32-33) (0x530+0x4*n)

UT EL EL

EL
_O _S _S

_S

EL
Cn EN INV

NV

_S
_I
UN n_O _

UT
_F C EN
IO UN _O

_O
GP _F Cn

Cn
d)

IO UN

UN
ve

GP _F

_F
r
se

IO

IO
(re

GP

GP
31 12 11 10 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x Reset

GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)

[GPIO_FUNCn_OEN_SEL]1: Force the output enable signal to be sourced from bit n of

GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W)

GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)

GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. A value of s (0<=s<256)

connects peripheral output s to GPIO output n. A value of 256 selects bit n of
GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the output
value and output enable. (R/W)

6.13.2 IO MUX Registers

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Register 6.33. IO_MUX_PIN_CTRL (0x00)

K2
K3

K1
CL

CL

CL
L_

L_

L_
)
ed

R
CT

CT

CT
rv
se

N_

N_

N_
(re

PI

PI

PI
31 12 11 8 7 4 3 0

0x0 0x0 0x0 0x0 Reset

If you want to output clock for I2S0 (I2S0_CLK) to:

CLK_OUT1, then set PIN_CTRL[3:0] = 0x0;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0.
If you want to output clock for I2S1 (I2S1_CLK) to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0xF;
CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0.

If you want to output clock for APLL to

CLK_OUT1, then set PIN_CTRL[3:0] = 0x6;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x6 and PIN_CTRL[7:4] = 0x6;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x6 and PIN_CTRL[11:8] = 0x6. (R/W)

Note:

• Only the above mentioned combinations of clock source (i.e. I2S0/1_CLK, APLL clock) and clock output pins
(i.e. CLK_OUT1 ~ 3) are possible.

• The CLK_OUT1 ~ 3 can be found in the IO MUX Pin Summary.

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Register 6.34. IO_MUX_x_REG (x: 0-19, 201 , 21-23, 25-27, 32-39) (See Table 6.12-2 for the addresses)

U
P_ PD
)

CU V
N_ PU

CU D
EL

FU RV
ed

CU P
R

E
CU L
P

M _IE
M _W
SL _W
_D

_O
M SE
_S

FU IE
FU _W
W
rv

D
N_

N_
se

CU

CU
N
(re

FU
M

M
31 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 0 0 0 0x0 0 0 0 0 0 Reset

MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1,
etc. (R/W)

FUN_DRV Select the drive strength of the pin. A higher value corresponds with a higher strength.
For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table
”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. (R/W)

FUN_IE Input enable of the pin. 1: input enabled; 0: input disabled. (R/W)

FUN_WPU Pull-up enable of the pin. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO
pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-
down circuitry, therefore, their FUN_WPU is always 0. (R/W)

FUN_WPD Pull-down enable of the pin. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal
pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. (R/W)

MCU_DRV Select the drive strength of the pin during sleep mode. A higher value corresponds with
a higher strength. (R/W)

MCU_IE Input enable of the pin during sleep mode. 1: input enabled; 0: input disabled. (R/W)

MCU_WPU Pull-up enable of the pin during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)

MCU_WPD Pull-down enable of the pin during sleep mode. 1: internal pull-down enabled; 0: internal
pull-down disabled. (R/W)

SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. (R/W)

MCU_OE Output enable of the pin in sleep mode. 1: enable output; 0: disable output. (R/W)

Note:
1. GPIO20 is available only on ESP32-PICO-V3 and ESP32-PICO-V3-02.

6.13.3 RTC IO MUX Registers

The addresses in parenthesis besides register names are the register addresses relative to (the RTC base
address + 0x0400 = 0x3FF4_8400). The RTC base address is provided in Table 3.3-6 Peripheral Address
Mapping in Chapter 3 System and Memory. The absolute register addresses are listed in Section 6.12.3 RTC IO
MUX Register Summary.

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Register 6.35. RTCIO_RTC_GPIO_OUT_REG (0x0000)

A
AT
_D
UT
_O
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc. (R/W)

Register 6.36. RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004)

S
1T
A _W
AT
_D
UT
_O
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the value
written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO)

Register 6.37. RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008)

C
1T
A _W
AT
_D
UT
_O
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO)

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Register 6.38. RTCIO_RTC_GPIO_ENABLE_REG (0x000C)

B LE
NA
_E
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1 means
this GPIO pin is output. (R/W)

Register 6.39. RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)

S
1T
W
E_
BL
E NA
O_I
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)

Register 6.40. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)

C
1T
W
E_
BL
NA
_E
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)

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Register 6.41. RTCIO_RTC_GPIO_STATUS_REG (0x0018)

NTI
S_
TU
TA
_S
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1],

etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT-
CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W)

Register 6.42. RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)

S
1T
_W
NT
I
U S_
AT
ST
O_
I
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO)

Register 6.43. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)

C
1T
_W
NTI
S_
TU
TA
_S
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared. (WO)

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Register 6.44. RTCIO_RTC_GPIO_IN_REG (0x0024)

XT
NE
N_
_I
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each bit
represents a pin input value, 1 for high level, and 0 for low level. (RO)

Register 6.45. RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (0x28+4*n)

LE
AB

ER
EN

IV
P_

DR
P
EU

TY

D_
T_
AK

PA
IN
W
n_

n_

n_
IN

IN

IN
_P

_P

_P
IO

IO

ed PIO
GP

GP

se C_G
C_

C_
)

)
RT

RT

(re RT
ed

ed
O_

O_

O_
rv

rv

rv
se

se
CI

CI

CI
(re

(re
RT

RT

RT
31 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 0 x 0 0 Reset

RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the ESP32
from Light-sleep. (R/W)

RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pin driver selection. 0: normal output; 1: open drain. (R/W)

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Register 6.46. RTCIO_DIG_PAD_HOLD_REG (0x0074)

31 0

0 Reset

RTCIO_DIG_PAD_HOLD_REG Selects the digital pins which should be put on hold. While 0 allows
normal operation, 1 puts the pin on hold. (R/W)

Table 6.13-1. Mapping of Bits to Pins

Name Description
Bit[0] Set to 1 to enable the Hold function of pin U0RXD
Bit[1] Set to 1 to enable the Hold function of pin U0TXD
Bit[2] Set to 1 to enable the Hold function of pin SD_CLK
Bit[3] Set to 1 to enable the Hold function of pin
SD_DATA0
Bit[4] Set to 1 to enable the Hold function of pin
SD_DATA1
Bit[5] Set to 1 to enable the Hold function of pin
SD_DATA2
Bit[6] Set to 1 to enable the Hold function of pin
SD_DATA3
Bit[7] Set to 1 to enable the Hold function of pin
SD_CMD
Bit[8] Set to 1 to enable the Hold function of pin GPIO5
Bit[9] Set to 1 to enable the Hold function of pin GPIO16
Bit[10] Set to 1 to enable the Hold function of pin GPIO17
Bit[11] Set to 1 to enable the Hold function of pin GPIO18
Bit[12] Set to 1 to enable the Hold function of pin GPIO19
Bit[13] Set to 1 to enable the Hold function of pin
GPIO201
Bit[14] Set to 1 to enable the Hold function of pin GPIO21
Bit[15] Set to 1 to enable the Hold function of pin GPIO22
Bit[16] Set to 1 to enable the Hold function of pin GPIO23

1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet
for more information.

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Register 6.47. RTCIO_SENSOR_PADS_REG (0x007C)

R_ SE4 U SEL
UX EL
EL

S E LP L

_S SE SL EL
NS SEN E3_ UX EL

E LP EL

_S E3_ P_ L

4_ P_ L
O_ SOR SEN E2_ _SE

O_ SOR SEN E3_ _SE

_S E1_ P_I L
SE

O_ NS _S E3_ _IE

L E

SE SL SE
O_ NS _S E4_ _IE

IE
M _S
_S

S SL E

S
IE

SE 2_F _IE

UN E
_ S M S

FU I E
SO ENS 2_S _S

_S
EN FU E
M _
C SE OR EN 3_ LD

EN 1_ _S
CI SE OR EN 4_ LD
RT SE OR EN 1_M LD

NS _S SE UN_

N_
I
O_ SOR SEN E2_ UX_
C SE OR EN 2_ D

N_

N_

EN 4_ P_
X

UN

SE E3 LP
RT IO_ NS _S SE OL

P
RT IO_ NS _S SE HO
RT IO_ NS _S SE HO
O_ NS _S SE HO

FU

FU
FU

_S SE SL

S
S
F

F
C SE OR EN 1_H

O_ NS _S E2_

_
_

OR EN _
O_ NS _S E1_

OR EN 1_

4
RT IO_ NS _S SE

NS _S SE
N _ S

N _ S
S

NS

N _ S
S
S

NS
C SE OR EN

EN

RT SE OR EN

RT SE OR EN

RT SE OR EN

SE OR EN
E
RT IO_ NS _S

R_

_
C SE OR

CI E R

OR

CI SE OR

CI SE OR

OR

CI SE OR
O

O
RT IO_ NS

RT O_ NS

NS

RT O_ NS

RT IO_ NS

RT _ S
EN

EN

)
C SE

RT SE

CI SE

RT SE

CI SE

C SE

CI SE

ed
S

S
RT IO_

RT _

O_

RT O_

RT _

RT O_

rv
O

se
CI

CI

CI

CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal oper-
ation. (R/W)

RTCIO_SENSOR_SENSEn_MUX_SEL 1: route sensen to the RTC block; 0: route sensen to the

digital IO_MUX. (R/W)

RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pin. 0: select Func-
tion 0. (R/W)

RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pin: set to 1 to put the pin in
sleep mode. (R/W)

RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pin in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pin. 1: enabled; 0: disabled. (R/W)

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Register 6.48. RTCIO_ADC_PAD_REG (0x0080)

EL

AD AD 2_S SEL
UX EL

RT AD AD _SL EL

C2 LP EL
C LP EL

E
_S

_F E

_F _IE
C_ 2_M X_S

AD _S _S

_I
C_ 1_F _IE
AD _M LD

_
AD _S _S

_I
RT AD AD _H D

N_

UN

UN
C_ C2 LP
UN
O_ C_ C OL

C_ C1 P
C_ C1 O
C U

FU
CI AD AD H
RT IO_ C_ C1_

_
2

C2
C1

1
O_ C_ C

O_ C_ C
C AD AD

AD

CI AD AD

AD

CI AD AD
RT O_ C_

RT _ _

RT O_ C_
C

)
CI AD

RT AD

CI AD

RT AD

CI AD

ed
RT IO_

O_

RT O_

O_

RT O_

rv
O

se
CI

CI

CI

CI
C

(re
RT

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pin; 0 is for normal operation.
(R/W)

RTCIO_ADC_ADCn_MUX_SEL 0: route pin to the digital IO_MUX; (R/W)

1: route pin to the RTC block.

RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pin. 0: select Function 0; 3: select
Function 1. (R/W)

RTCIO_ADC_ADCn_SLP_SEL Signal selection of pin’s sleep mode. Set this bit to 1 to put the pin to
sleep. (R/W)

RTCIO_ADC_ADCn_SLP_IE Input enable of the pin in sleep mode. 1 enabled; 0 disabled. (R/W)

RTCIO_ADC_ADCn_FUN_IE Input enable of the pin. 1 enabled; 0 disabled. (R/W)

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Register 6.49. RTCIO_PAD_DAC1_REG (0x0084)

E
RC
FO
D_
FU EL
AC UX_ C

CI PA PD 1_S SEL

O_ D_ AC L EL
M DA

XP
AC FU E
DA IE
S

D_ AC SL E
PD 1_ P_O
CI PA PD 1_S _S
PD 1_ LD

N_

1_ N_
PA PD 1_ P_I

C_
D_ C1_ D_
C
V

E
1_ E

RT _ _ C LP
D_ AC HO

RU
DR

AC RD

DA

A XP
1_

PA D _

1_

O_ _PD C1_

1_
1
AC

O_ D_ AC

AC

RT O_ D_ AC
D A

A
PD

CI PA PD

PD

RT PA PD

PD

CI PA PD
P
D_

RT _ _

D_

O_ D_

RT O_ D_
D

)
RT PA

CI PA

PA

CI PA

RT PA

CI PA

ed
O_

RT IO_

O_

RT O_

RT O_

rv
O

se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC1_DRV Select the drive strength of the pin. (R/W)

RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pin; set to 0 for normal operation.
(R/W)

RTCIO_PAD_PDAC1_RDE 1: Pull-down on pin enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC1_RUE 1: Pull-up on pin enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC1_DAC Pin DAC1 output value. (R/W)

RTCIO_PAD_PDAC1_XPD_DAC Power on DAC1. Usually, PDAC1 needs to be tristated if we power on

the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC1_MUX_SEL 0: route pin to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC1_FUN_SEL the functional selection signal of the pin. (R/W)

RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pin. Set this bit to 1 to put the pin
to sleep. (R/W)

RTCIO_PAD_PDAC1_SLP_IE Input enable of the pin in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_SLP_OE Output enable of the pin. 1: enabled ; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_FUN_IE Input enable of the pin. 1: enabled it; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if we

power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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Register 6.50. RTCIO_PAD_DAC2_REG (0x0088)

E
RC
FO
D_
UN L
DA MU DAC

RT IO_ D_ AC SLP L

PA PD 2_ P_ L
_F SE

XP
AC FU OE
O_ D_ AC SL E

DA IE
_S

D_ AC SL IE
CI PA PD 2_ _S
C2 X_
PD 2_ LD

2_ N_
C_
D_ C2_ PD_

PD 2_ P_
C
O_ D_ AC RV

E
2_ E
D_ AC HO

RU
AC RD

DA
D

A X
2_

PA D _

2_

O_ _PD C2_

C PA PD 2_
2
AC

AC

RT _ _ C
D A

A
PD

CI PA PD

PD

RT PA PD

CI A D
P

P
D_

RT _ _

D_

O_ D_

RT O_ D_
D

)
RT PA

CI PA

PA

CI PA

RT PA

CI PA

ed
P
O_

RT IO_

O_

RT O_

RT _

rv
O

se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC2_DRV Select the drive strength of the pin. (R/W)

RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pin; 0 is for normal operation.
(R/W)

RTCIO_PAD_PDAC2_RDE 1: Pull-down on pin enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC2_RUE 1: Pull-up on pin enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC2_DAC Pin DAC2 output value. (R/W)

RTCIO_PAD_PDAC2_XPD_DAC Power on DAC2. PDAC2 needs to be tristated if we power on the

DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC2_MUX_SEL 0: route pin to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pin. 0: select Function 0. (R/W)

RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pin. Set this bit to 1 to put the
pin to sleep. (R/W)

RTCIO_PAD_PDAC2_SLP_IE Input enable of the pin in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_SLP_OE Output enable of the pin. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_FUN_IE Input enable of the pin. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if we

power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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Register 6.51. RTCIO_XTAL_32K_PAD_REG (0x008C)

K
K
2N X_S L

32
CI XT X3 _S SEL
CI XT X3 FUN L

O_ AL 2 LP L

32
2K

2P U 2K

L_ 2N LP EL
U SE

L_ 2P LP_ L
E

E
X3 FUN E
E

DR UN E
RT XTA X3 _S SE

_X E

L_
X3 _S _IE

_S
_ _O

X3 _S IE
_3

L_
RT XTA _X3 _S _S

_I
X3 M 3
_M X_

_F _O
_I
X3 _R D

_
X3 _R D

TA
L_ 2N OL
CI XT X3 DRV

X3 RUE
2N DE

N P

2N LP

UN
L_ 2P OL
RV

UE

TA
2P DE

CI XT XP TAL

L_ 2N L

2P LP
O_ AL 2 L
A

_X
RT XTA _X3 _H

RT XTA _X3 XT
_D

RT XTA X3 _H

_R

CI XT X3 _S
_F
_

_
X

AS
C_

ES
_
2N

RT _ L_ N
2P

2P

RT O_ L_ 2P

P
O_ AL D
O_ AL 2

O_ AL 2

ed DBI
DA
X3

CI XT X3

X3

CI XT X3
L_

RT _ L_

L_

RT O_ AL_

L_

RT O_ L_

L_

RT O_ L_

L_

RT IO_ AL_

L_

L_
RT XTA

RT XTA

RT XTA

RT XTA

A
A

RT XTA

(re XTA

)
CI XT

CI XT

CI XT

CI XT

C T

XT
X
O_

RT IO_

O_

RT _

O_

RT _

O_

RT _

O_

RT O_

O_

O_

rv
O

se
CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI
C
RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

2 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

RTCIO_XTAL_X32N_DRV Select the drive strength of the pin. (R/W)

RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pin; 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32N_RDE 1: Pull-down on pin enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32N_RUE 1: Pull-up on pin enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_X32P_DRV Select the drive strength of the pin. (R/W)

RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pin, 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32P_RDE 1: Pull-down on pin enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32P_RUE 1: Pull-up on pin enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_DAC_XTAL_32K 32K XTAL bias current DAC value. (R/W)

RTCIO_XTAL_XPD_XTAL_32K Power up 32 KHz crystal oscillator. (R/W)

RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pin to the digital IO_MUX; 1: route to RTC block. (R/W)

RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pin to the digital IO_MUX; 1: route to RTC block. (R/W)

RTCIO_XTAL_X32N_FUN_SEL Select the RTC function. 0: select function 0. (R/W)

RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pin to sleep. (R/W)

RTCIO_XTAL_X32N_SLP_IE Input enable of the pin in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32N_SLP_OE Output enable of the pin. 1: enabled; 0; disabled. (R/W)

RTCIO_XTAL_X32N_FUN_IE Input enable of the pin. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32P_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.

(R/W)

RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pin to sleep. (R/W)

RTCIO_XTAL_X32P_SLP_IE Input enable of the pin in sleep mode. 1: enabled; 0: disabled. (R/W)

Continued on the next page...

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Register 6.51. RTCIO_XTAL_32K_PAD_REG (0x008C)

Continued from the previous page...

RTCIO_XTAL_X32P_SLP_OE Output enable of the pin in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_XTAL_X32P_FUN_IE Input enable of the pin. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W)

RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W)

Register 6.52. RTCIO_TOUCH_CFG_REG (0x0090)

RE S
_D BIA

GE
FH

UR
AN
EF
UC PD_

DC
DR

DR
X
O_ CH_

H_
H

CH

CH

UC
RT TOU

)
TO

TO

TO

TO

ed
O_

O_

O_

O_

rv
se
CI

CI

CI

CI

CI

(re
RT

RT

RT

RT

31 30 29 28 27 26 25 24 23 22 0

0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W)

RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W)

RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W)

RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W)

RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is avail-
able. (R/W)

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Register 6.53. RTCIO_TOUCH_PADn_REG (n: 0-7) (0x94+4*n)

UN L

RT O_T UC PA _SL EL

TO H D LP EL
_F SE

IO
AD _XP OPT

Dn UN E
O_ E
_S

UC _PA n_S _IE

GP
PA _F _O
P _T T

O_ UC PA _S S

_T _I
Dn X_
n_ D

RT TOU H_ Dn TAR

CI O H_ Dn P_
PA HOL

AC

O_ CH_ ADn IE_

V

UE
Dn DE

n_ D

H_ Dn LP
PA MU
DR

_D
PA _R
_R

O_ UC PA _S
_
Dn

Dn

CI O H_ Dn

CI O H_ Dn
D

ed H D
RT TOU PA

rv C PA

PA

RT O_T UC PA

RT O_T C PA
P
O_ CH_

RT IO_T H_

se OU H_
_

H_

CI O H_

RT O_T H_

CI O H_
C

(re _T C

UC

RT O_T C

RT O_T UC
RT TOU

OU

U
)

d)
CI O

TO

CI O

CI O

ve
RT IO_T

T
O_

O_
O

r
se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT

RT
31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 0

0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_PADn_HOLD Write 1 to hold the current value of the output. (R/W)

RTCIO_TOUCH_PADn_DRV Selects the drive strength of the pin. A higher value corresponds with a
higher strength. For detailed drive strength, please see ESP32 Datasheet > Appendix A.1 Notes
on ESP32 Pin Lists > Note 8. (R/W)

RTCIO_TOUCH_PADn_RDE 1: Pull-down on pin enabled; 0: Pull-down disabled. (R/W)

RTCIO_TOUCH_PADn_RUE 1: Pull-up on pin enabled; 0: Pull-up disabled. (R/W)

RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pin. Default is b’100.
(R/W)

RTCIO_TOUCH_PADn_START Write 1 to start touch sensor. (R/W)

RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option.

0: Tied to 0 V
1: Tied to VDD_RTC voltage
(R/W)

RTCIO_TOUCH_PADn_XPD Write 1 to power on the touch sensor. (R/W)

RTCIO_TOUCH_PADn_MUX_SEL Selects RTC IO_MUX or IO_MUX to control the IE/OE/RUE/RDE

statues of RTC pin.
1: Selects RTC IO_MUX
0: Selects IO_MUX
(R/W)

RTCIO_TOUCH_PADn_FUN_SEL Selects the function of the RTC.

0: RTC Function 0
1: Reserved
2: Reserved
3: RTC Function 1
(R/W)

RTCIO_TOUCH_PADn_SLP_SEL Sleep mode selection signal of the pin. Set this bit to 1 to put the
pin to sleep. (R/W)

Continued on the next page...

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Register 6.53. RTCIO_TOUCH_PADn_REG (n: 0-7) (0x94+4*n)

Continued from the previous page...

RTCIO_TOUCH_PADn_SLP_IE Input enable of the pin in sleep mode (SLP_SEL = 1).

1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_SLP_OE Output enable of the pin in sleep mode (SLP_SEL = 1).

1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_FUN_IE Input enable of the pin in normal working mode (SLP_SEL = 0).
1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_TO_GPIO Controls the routing of touch pin input signals to IO_MUX.

1: The input signal from the touch pin is routed to IO_MUX through analog function.
0: The input signal from the touch pin is routed to IO_MUX through digital function.
(R/W)

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Register 6.54. RTCIO_TOUCH_PADm_REG (m = 8, 9) (0x00B4, 0x00B8)

IO
Dm XP PT

GP
UC _PA m_ ART
PA _ _O
AC

_T D
O_
H_ Dm TIE
TO H D ST
_D

O_ UC PA _
Dm

CI O H_ Dm
PA

RT _T C A P
H_

CI O H_
UC

RT O_T UC
U
d)

d)
TO

CI O
ve

ve
RT O_T
O_

O
r

r
se

se
CI

CI
(re

(re
RT

RT
31 26 25 23 22 21 20 19 16 0

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_PADm_DAC Touch sensor slope control. 3-bit for each touch pin. Default b’100.
(R/W)

RTCIO_TOUCH_PADm_START Write 1 to start touch sensor. (R/W)

RTCIO_TOUCH_PADm_TIE_OPT Default touch sensor tie option.

0: Tied to 0 V
1: Tied to VDD_RTC voltage
(R/W)

RTCIO_TOUCH_PADm_XPD Write 1 to power on the touch sensor. (R/W)

RTCIO_TOUCH_PADm_TO_GPIO Controls the routing of touch pin input signals to IO_MUX.

1: The input signal from the touch pin is routed to IO_MUX through analog function.
0: The input signal from the touch pin is routed to IO_MUX through digital function.
(R/W)

Register 6.55. RTCIO_EXT_WAKEUP0_REG (0x00BC)

E L
_S
P0
EU
AK
_W
XT

)
ed
E
O_

rv
se
CI

(re
RT

31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the
sleep mode. This register prompts the pin source to wake up the chip when the latter is in
deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W)

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Register 6.56. RTCIO_XTL_EXT_CTR_REG (0x00C0)

S EL
R_
CT
T_
_EX
TL

d)
X

ve
O_

r
se
CI

(re
RT

31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into
sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR
RTC_CNTL_XTL_EXT_CTR_LV is the crystal power down enable signal. (R/W)

Register 6.57. RTCIO_SAR_I2C_IO_REG (0x00C4)

L

L
SE

SE
A_

L_
SC
SD
C_

C_
I2

I2
R_

R_

)
SA

SA

ed
O_

O_

rv
se
CI

CI

(re
RT

RT

31 30 29 28 27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SAR_I2C_SDA_SEL Selects the other pin as the RTC I2C SDA signal. 0: pin TOUCH_PAD[1];
1: pin TOUCH_PAD[3]. Default value is 0. (R/W)

RTCIO_SAR_I2C_SCL_SEL Selects the other pin as the RTC I2C SCL signal. 0: pin TOUCH_PAD[0];
1: pin TOUCH_PAD[2]. Default value is 0. (R/W)

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Chapter 7

Reset and Clock

7.1 System Reset

7.1.1 Introduction
The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear
the RAM. Figure 7.1-1 shows the subsystems included in each reset level.

Figure 7.1-1. System Reset

• CPU reset: Only resets the registers of one or both of the CPU cores.

• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC
is not reset.

• System reset: Resets all the registers on the chip, including those of the RTC.

7.1.2 Reset Source

While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able
to reset only one of the two cores. The reset reason for each core can be looked up individually: the
PRO_CPU reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the
APP_CPU in
RTC_CNTL_RESET_CAUSE_APPCPU. Table 7.1-1 shows the possible reset reason values that can be read from
these registers.

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Table 7.1-1. PRO_CPU and APP_CPU Reset Reason Values

PRO APP Source Reset Type Note

0x01 0x01 Chip Power On Reset System Reset -
0x10 0x10 RWDT System Reset System Reset See WDT Chapter.
0x0F 0x0F Brown Out Reset System Reset See Power Management Chapter.
0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register.
0x05 0x05 Deep Sleep Reset Core Reset See Power Management Chapter.
0x06 0x06 SDIO Reset Core Reset Reserved
0x07 0x07 MWDT0 Global Reset Core Reset See WDT Chapter.
0x08 0x08 MWDT1 Global Reset Core Reset See WDT Chapter.
0x09 0x09 RWDT Core Reset Core Reset See WDT Chapter.
0x0B - MWDT0 CPU Reset CPU Reset See WDT Chapter.
0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
- 0x0B MWDT1 CPU Reset CPU Reset See WDT Chapter.
- 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
0x0D 0x0D RWDT CPU Reset CPU Reset See WDT Chapter.
Indicates that the PRO CPU has independently
- 0xE PRO CPU Reset CPU Reset reset the APP CPU by configuring the
DPORT_APPCPU_RESETTING register.

7.2 System Clock

7.2.1 Introduction
The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks
can be configured to meet different requirements. Figure 7.2-1 shows the system clock structure.

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Figure 7.2-1. System Clock

7.2.2 Clock Source

The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:

• High Speed Clocks

– PLL_CLK is an internal PLL clock with a frequency of 320 MHz or 480 MHz.

– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.

• Low Power Clocks

– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.

– RC_FAST_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.

– RC_FAST_DIV_CLK is divided from RC_FAST_CLK. Its frequency is (RC_FAST_CLK / 256). With the
default RC_FAST_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.

– RC_SLOW_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.

• Audio Clock

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– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.

7.2.3 CPU Clock

As Figure 7.2-1 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as
240 MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to
reduce power consumption.

The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RC_FAST_CLK, and XTL_CLK can be set as the CPU_CLK source; see Table 7.2-1 and 7.2-2.

Table 7.2-1. CPU_CLK Source

RTC_CNTL_SOC_CLK_SEL Value Clock Source

0 XTL_CLK
1 PLL_CLK
2 RC_FAST_CLK
3 APLL_CLK

Table 7.2-2. CPU_CLK Derivation

Clock Source *SEL_0 *SEL_1 CPU Clock Frequency

XTL_CLK 0 - CPU_CLK = XTL_CLK / (SYSCON_PRE_DIV_CNT+1)
CPU_CLK = PLL_CLK / 4
PLL_CLK (320 MHz) 1 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
PLL_CLK (320 MHz) 1 1
CPU_CLK frequency is 160 MHz
CPU_CLK = PLL_CLK / 2
PLL_CLK (480 MHz) 1 2
CPU_CLK frequency is 240 MHz
RC_FAST_CLK 2 - CPU_CLK = RC_FAST_CLK / (SYSCON_PRE_DIV_CNT+1)
APLL_CLK 3 0 CPU_CLK = APLL_CLK / 4
APLL_CLK 3 1 CPU_CLK = APLL_CLK / 2

*SEL_0: The value of register RTC_CNTL_SOC_CLK_SEL

*SEL_1: The value of register CPU_CPUPERIOD_SEL

7.2.4 Peripheral Clock

Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK, and PLL_F160M_CLK.
Table 7.2-3 shows which clocks can be used by which peripherals.

Table 7.2-3. Peripheral Clock Usage

Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_F160M_CLK

EMAC Y N N Y N
TIMG Y N N N N
I2S Y N N Y Y
UART Y Y N N N

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RMT Y Y N N N
LED PWM Y Y Y N N
PWM Y N N N Y
I2C Y N N N N
SPI Y N N N N
PCNT Y N N N N
eFuse Controller Y N N N N
SDIO Slave Y N N N N
SDMMC Y N N N N

7.2.4.1 APB_CLK
The APB_CLK frequency is determined by CPU_CLK source, as detailed in Table 7.2-4.

Table 7.2-4. APB_CLK

CPU_CLK Source APB_CLK Frequency

PLL_CLK 80 MHz
APLL_CLK CPU_CLK / 2
XTL_CLK CPU_CLK
RC_FAST_CLK CPU_CLK

7.2.4.2 REF_TICK
REF_TICK is derived from APB_CLK. The APB_CLK frequency is determined by CPU_CLK source. The
REF_TICK frequency should be fixed. When CPU_CLK source changes, users need to make sure the REF_TICK
frequency remains unchanged by setting a correct divider value.

Clock divider registers are shown in Table 7.2-5.

Table 7.2-5. REF_TICK

CPU_CLK Source APB_CLK Frequency REF_TICK Frequency

PLL_CLK 80 MHz APB_CLK / (SYSCON_PLL_TICK_NUM+1)
APLL_CLK CPU_CLK / 2 APB_CLK / (SYSCON_APLL_TICK_NUM+1)
XTL_CLK CPU_CLK APB_CLK / (SYSCON_XTAL_TICK_NUM+1)
FOSC_CLK CPU_CLK APB_CLK / (SYSCON_CK8M_TICK_NUM+1)

For example, when CPU_CLK source is PLL_CLK and users need to keep the REF_TICK frequency at 1 MHz,
then they should set SYSCON_PLL_TICK_NUM to 79 (0x4F) so that the REF_TICK frequency = 80 MHz /
(79+1) = 1 MHz.

7.2.4.3 LEDC_SCLK Source

The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 7.2-6.

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Table 7.2-6. LEDC_SCLK Derivation

LEDC_APB_CLK_SEL Value LEDC_SCLK Source

0 RC_FAST_CLK
1 APB_CLK

7.2.4.4 APLL_SCLK Source

The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.

7.2.4.5 PLL_F160M_CLK Source

PLL_F160M_CLK is divided from PLL_CLK by automatically adjusting the clock division and its frequency is
always 160 MHz.

7.2.4.6 Clock Source Considerations

Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change.
Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without
changing clock source. Please see Table 7.2-3 for details.

The LED PWM module can use RC_FAST_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see Chapter 9 Low-Power Management (RTC_CNTL)),
normal peripherals will be halted (APB_CLK is turned off), but the LED PWM can work normally via
RC_FAST_CLK.

7.2.5 Wi-Fi BT Clock

Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low-power consumption mode first.

For LOW_POWER_CLK, one of RC_SLOW_CLK, RTC_SLOW_CLK, RC_FAST_CLK or XTL_CLK can be selected

as the low-power consumption mode clock source for Wi-Fi and BT.

7.2.6 RTC Clock

The clock sources of RTC_SLOW_CLK and RTC_FAST_CLK are low-frequency clocks. The RTC module can
operate when most other clocks are stopped.

RTC_SLOW_CLK is used to clock the Power Management module. It can be sourced from RC_SLOW_CLK,
XTL32K_CLK or RC_FAST_DIV_CLK.

RTC_FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or
from RC_FAST_CLK.

7.2.7 Audio PLL

The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter,
and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may

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carry jitter and, therefore, they do not support a high-precision clock frequency setting.

Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an
audio PLL.

The Audio PLL formula is as follows:

fxtal (sdm2 + sdm1

28
+ sdm0
216
+ 4)
fout =
2(odiv + 2)

The parameters of this formula are defined below:

• fxtal : the frequency of the crystal oscillator, usually 40 MHz;

• sdm0: the value is 0 ~ 255;

• sdm1: the value is 0 ~ 255;

• sdm2: the value is 0 ~ 63;

• odiv: the value is 0 ~ 31;

• The operating frequency range of the numerator is 350 MHz ~ 500 MHz

sdm1 sdm0
350M Hz < fxtal (sdm2 + + + 4) < 500M Hz
28 216

Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ESP32 Series SoC Errata for further details.

Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA
_FORCE_PD, respectively. Disabling it takes priority over enabling it. When RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system, i.e., when the system enters sleep
mode, PLL will be disabled automatically; when the system wakes up, PLL will be enabled automatically.

7.3 Register Summary

The addresses in this section are relative to the SYSCON base address provided in Table 3.3-6 Peripheral
Address Mapping in Chapter 3 System and Memory.

Name Description Address Access

Configuration register
SYSCON_SYSCLK_CONF_REG Configures system clock frequency 0x0000 R/W
SYSCON_XTAL_TICK_CONF_REG Configures the divider value of REF_TICK 0x0004 R/W
SYSCON_PLL_TICK_CONF_REG Configures the divider value of REF_TICK 0x0008 R/W
SYSCON_CK8M_TICK_CONF_REG Configures the divider value of REF_TICK 0x000C R/W
SYSCON_APLL_TICK_CONF_REG Configures the divider value of REF_TICK 0x003C R/W
Chip revision register
SYSCON_DATE_REG Chip revision register 0x007C R/W

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7.4 Registers
The addresses in this section are relative to the SYSCON base address provided in Table 3.3-6 Peripheral
Address Mapping in Chapter 3 System and Memory.

Register 7.1. SYSCON_SYSCLK_CONF_REG (0x0000)

T
CN
V_
DI
RE_
_P
d)
ve

ON
r

SC
se
(re

SY
31 10 9 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

SYSCON_PRE_DIV_CNT Configures the divider value of CPU_CLK when the source of CPU_CLK
is XTL_CLK or RC_FAST_CLK. The value range is 0x0 ~ 0x3FF. CPU_CLK = XTL_CLK ( or
RC_FAST_CLK) / (the value of this field +1). (R/W)

Register 7.2. SYSCON_XTAL_TICK_CONF_REG (0x0004)

U M
_N
I CK
_T
L
TA
_X
)
ed

ON
rv

SC
se
(re

SY
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 Reset

SYSCON_XTAL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is XTL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

Register 7.3. SYSCON_PLL_TICK_CONF_REG (0x0008)

UM
_N
CK
I
_T
LL
_P
)
ed

ON
rv

SC
se
(re

SY

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 Reset

SYSCON_PLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is PLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

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Register 7.4. SYSCON_CK8M_TICK_CONF_REG (0x000C)

M
NU
K_
IC
_T
M
K8
_C
)
ed

ON
rv

SC
se
(re

SY
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 Reset

SYSCON_CK8M_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is FOSC_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

Register 7.5. SYSCON_APLL_TICK_CONF_REG (0x003C)

UM
_N
I CK
_T
L
PL
_A
)
ed

ON
rv

SC
se
(re

SY
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 Reset

SYSCON_APLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is APLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

Register 7.6. SYSCON_DATE_REG (0x007C)

E
AT
_D
ON
SC
SY

31 0

0x16042000 Reset

SYSCON_DATE Chip revision register. For more information see ESP32 Series SoC Errata. (R/W)

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Chapter 8

Interrupt Matrix (INTERRUPT)

8.1 Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different
needs.

8.2 Features
• Accepts 71 peripheral interrupt sources as input.

• Generates 26 peripheral interrupt sources per CPU as output (52 total).

• CPU NMI Interrupt Mask.

• Queries current interrupt status of peripheral interrupt sources.

The structure of the Interrupt Matrix is shown in Figure 8.2-1.

Figure 8.2-1. Interrupt Matrix Structure

8.3 Functional Description

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8.3.1 Peripheral Interrupt Source

ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 8.3-1. 67 of
71 ESP32 peripheral interrupt sources can be allocated to either CPU.

The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and
GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each
have 69 peripheral interrupt sources.

PeripheralInterruptConfigStatusSource.tex

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Chapter 8 Interrupt Matrix (INTERRUPT)

PRO_CPU APP_CPU
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
DPORT_PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 DPORT_APP_MAC_INTR_MAP_REG
DPORT_PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 DPORT_APP_MAC_NMI_MAP_REG
DPORT_PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 DPORT_APP_BB_INT_MAP_REG
DPORT_PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 DPORT_APP_BT_MAC_INT_MAP_REG
DPORT_PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 DPORT_APP_BT_BB_INT_MAP_REG
DPORT_PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 DPORT_APP_BT_BB_NMI_MAP_REG
DPORT_PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 DPORT_APP_RWBT_IRQ_MAP_REG
DPORT_PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 DPORT_APP_RWBLE_IRQ_MAP_REG
DPORT_PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 DPORT_APP_RWBT_NMI_MAP_REG
DPORT_PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 DPORT_APP_RWBLE_NMI_MAP_REG
DPORT_PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 DPORT_APP_SLC0_INTR_MAP_REG
DPORT_PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 DPORT_APP_SLC1_INTR_MAP_REG
DPORT_PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 DPORT_APP_UHCI0_INTR_MAP_REG
DPORT_PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 DPORT_APP_UHCI1_INTR_MAP_REG
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 DPORT_APP_TG_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 DPORT_APP_TG_T1_LEVEL_INT_MAP_REG
DPORT_PRO_INTR_STATUS_REG_0_REG DPORT_APP_INTR_STATUS_REG_0_REG
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DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG

DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_MAP_REG 22 22 GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP 22 22 DPORT_APP_GPIO_INTERRUPT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG 23 23 GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI 23 23 DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG
175

DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG

DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG
DPORT_PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 DPORT_APP_SPI_INTR_0_MAP_REG
DPORT_PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 DPORT_APP_SPI_INTR_1_MAP_REG
DPORT_PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 DPORT_APP_SPI_INTR_2_MAP_REG
DPORT_PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 DPORT_APP_SPI_INTR_3_MAP_REG
DPORT_PRO_I2S0_INT_MAP_REG 0 32 I2S0_INT 32 0 DPORT_APP_I2S0_INT_MAP_REG
DPORT_PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 DPORT_APP_I2S1_INT_MAP_REG
DPORT_PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 DPORT_APP_UART_INTR_MAP_REG
DPORT_PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 DPORT_APP_UART1_INTR_MAP_REG
DPORT_PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 DPORT_APP_UART2_INTR_MAP_REG
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG
DPORT_PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 DPORT_APP_EMAC_INT_MAP_REG
DPORT_PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 DPORT_APP_PWM0_INTR_MAP_REG
DPORT_PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 DPORT_APP_PWM1_INTR_MAP_REG
ESP32 TRM (Version 5.5)

Reserved 9 41 Reserved 41 9 Reserved

Reserved 10 DPORT_PRO_INTR_STATUS_REG_1_REG 42 Reserved 42 DPORT_APP_INTR_STATUS_REG_1_REG 10 Reserved
DPORT_PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 DPORT_APP_LEDC_INT_MAP_REG
DPORT_PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 DPORT_APP_EFUSE_INT_MAP_REG
DPORT_PRO_TWAI_INT_MAP_REG 13 45 TWAI_INT 45 13 DPORT_APP_TWAI_INT_MAP_REG
DPORT_PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 DPORT_APP_RTC_CORE_INTR_MAP_REG
DPORT_PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 DPORT_APP_RMT_INTR_MAP_REG
DPORT_PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 DPORT_APP_PCNT_INTR_MAP_REG
DPORT_PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 DPORT_APP_I2C_EXT0_INTR_MAP_REG

GoBack
DPORT_PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 DPORT_APP_I2C_EXT1_INTR_MAP_REG
DPORT_PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 DPORT_APP_RSA_INTR_MAP_REG
DPORT_PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 DPORT_APP_SPI1_DMA_INT_MAP_REG
 Espressif Systems
PRO_CPU APP_CPU

Chapter 8 Interrupt Matrix (INTERRUPT)

Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
DPORT_PRO_SPI2_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 DPORT_APP_SPI2_DMA_INT_MAP_REG
DPORT_PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 DPORT_APP_SPI3_DMA_INT_MAP_REG
DPORT_PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 DPORT_APP_WDG_INT_MAP_REG
DPORT_PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 DPORT_APP_TIMER_INT1_MAP_REG
DPORT_PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 DPORT_APP_TIMER_INT2_MAP_REG
DPORT_PRO_TG_T0_EDGE_INT_MAP_REG 26 DPORT_PRO_INTR_STATUS_REG_1_REG 58 TG_T0_EDGE_INT 58 DPORT_APP_INTR_STATUS_REG_1_REG 26 DPORT_APP_TG_T0_EDGE_INT_MAP_REG
DPORT_PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 DPORT_APP_TG_T1_EDGE_INT_MAP_REG
DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 DPORT_APP_TG_WDT_EDGE_INT_MAP_REG
DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 DPORT_APP_TG_LACT_EDGE_INT_MAP_REG
DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 DPORT_APP_TG1_T0_EDGE_INT_MAP_REG
DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 DPORT_APP_TG1_T1_EDGE_INT_MAP_REG
DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG 0 64 TG1_WDT_EDGE_INT 64 0 DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG
DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG
DPORT_PRO_MMU_IA_INT_MAP_REG 2 DPORT_PRO_INTR_STATUS_REG_2_REG 66 MMU_IA_INT 66 DPORT_APP_INTR_STATUS_REG_2_REG 2 DPORT_APP_MMU_IA_INT_MAP_REG
DPORT_PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 DPORT_APP_MPU_IA_INT_MAP_REG
DPORT_PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 DPORT_APP_CACHE_IA_INT_MAP_REG
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8.3.2 CPU Interrupt

Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All
interrupts in a CPU are listed in Table 8.3-2.

Table 8.3-2. CPU Interrupts

No. Category Type Priority Level

0 Peripheral Level-Triggered 1
1 Peripheral Level-Triggered 1
2 Peripheral Level-Triggered 1
3 Peripheral Level-Triggered 1
4 Peripheral Level-Triggered 1
5 Peripheral Level-Triggered 1
6 Internal Timer.0 1
7 Internal Software 1
8 Peripheral Level-Triggered 1
9 Peripheral Level-Triggered 1
10 Peripheral Edge-Triggered 1
11 Internal Profiling 3
12 Peripheral Level-Triggered 1
13 Peripheral Level-Triggered 1
14 Peripheral NMI NMI
15 Internal Timer.1 3
16 Internal Timer.2 5
17 Peripheral Level-Triggered 1
18 Peripheral Level-Triggered 1
19 Peripheral Level-Triggered 2
20 Peripheral Level-Triggered 2
21 Peripheral Level-Triggered 2
22 Peripheral Edge-Triggered 3
23 Peripheral Level-Triggered 3
24 Peripheral Level-Triggered 4
25 Peripheral Level-Triggered 4
26 Peripheral Level-Triggered 5
27 Peripheral Level-Triggered 3
28 Peripheral Edge-Triggered 4
29 Internal Software 3
30 Peripheral Edge-Triggered 4
31 Peripheral Level-Triggered 5

8.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU

In this section:

• Source_X stands for any particular peripheral interrupt source.

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• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration
register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to
the peripheral interrupt source Source_X. In Table 8.3-1 the registers listed under “PRO_CPU (APP_CPU)
- Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in
“Peripheral Interrupt Source - Name”.

• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5,
8 ~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.

• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15,
16, 29.

Using this terminology, the possible operations of the Interrupt Matrix controller can be described as
follows:

• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG (or APP_X_MAP_REG) to Num_P. Num_P can be any CPU peripheral interrupt
number. CPU interrupts can be shared between multiple peripherals (see below).

• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG (or APP_X _MAP_REG) for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I is connected to either CPU.

• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral
interrupts will trigger CPU Interrupt_P.

8.3.4 CPU NMI Interrupt Mask

The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s )
NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from
the peripheral PID Controller, respectively.

8.3.5 Query Current Interrupt Status of Peripheral Interrupt Source

The current interrupt status of a peripheral interrupt source can be read via the bit value in
PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 8.3-1.

8.4 Registers
The interrupt matrix registers are part of the DPORT registers and are described in Section 12.4 in Chapter 12
DPort Registers.

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Chapter 9

Low-Power Management (RTC_CNTL)

9.1 Introduction
ESP32 offers efficient and flexible power-management technology to achieve the best balance between
power consumption, wakeup latency and available wakeup sources. Users can select out of five predefined
power modes of the main processors to suit specific needs of the application. In addition, to save power in
power-sensitive applications, control may be executed by the Ultra-Low-Power coprocessor (ULP
coprocessor), while the main processors are in Deep-sleep mode.

9.2 Features
• Five predefined power modes to support various applications

• Up to 16 KB of retention memory

• 8 x 32 bits of retention registers

• ULP coprocessor enabled in all low-power modes

• RTC boot supported to shorten the wakeup latency

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Figure 9.2-1. ESP32 Power Control

9.3 Functional Description

9.3.1 Overview
The low-power management unit includes voltage regulators, a power controller, power switch cells, power
domain isolation cells, etc. Figure 9.2-1 shows the high-level architecture of ESP32’s low-power
management.

9.3.2 Digital Core Voltage Regulator

The built-in voltage regulator can convert the external power supply (typically 3.3V) to 1.1V to support the
internal digital core. It receives a wide range of external power supply from 1.8V to 3.6V, and provides an
output voltage from 0.90V to 1.25V.

1. When XPD_DIG_REG == 1, the regulator outputs a 1.1V voltage and the digital core is able to run; when
XPD_DIG_REG == 0, both the regulator and the digital core stop running.

2. DIG_REG_DBIAS[2:0] tunes the supply voltage of the digital core:

VDD_DIG = 0.90 + DBIAS · 0.05V

3. The current to the digital core comes from pin VDD3P3_CPU and pin VDD3P3_RTC.

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Figure 9.3-1 shows the structure of a digital core’s voltage regulator.

90

Figure 9.3-1. Digital Core Voltage Regulator

9.3.3 Low-Power Voltage Regulator

The built-in low-power voltage regulator can convert the external power supply (typically 3.3V) to 1.1V to
support the internal RTC core. To save power, it receives a wide range of external power supply from 1.8V to
3.6V, and supports an adjustable output voltage of 0.90V to 1.25V in normal work mode, a fixed output voltage
of about 0.75V both in Deep-sleep mode and Hibernation mode.

1. When the pin CHIP_PU is at a high level, the low-power voltage regulator cannot be turned off. It should
be switched only between normal-work mode and Deep-sleep mode.

2. In normal-work mode, RTC_DBIAS[2:0] can be used to tune the output voltage:

VDD_RTC = 0.90 + DBIAS · 0.05V

3. In Deep-sleep mode, the output voltage of the regulator is fixed at about 0.75V.

4. The current to the RTC core comes from pin VDD3P3_RTC.

Figure 9.3-2 shows the structure of a low-power voltage regulator.

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90

Figure 9.3-2. Low-Power Voltage Regulator

9.3.4 Flash Voltage Regulator

The built-in flash voltage regulator can supply a voltage of 3.3V or 1.8V to other devices (flash, for example) in
the system, with a maximum output current of 40 mA.

1. When XPD_SDIO_VREG == 1, the regulator outputs a voltage of 3.3V or 1.8V; when XPD_SDIO_VREG == 0,
the output is high-impedance and, in this case, the voltage is provided by the external power supply.

2. When SDIO_TIEH == 1, the regulator shorts pin VDD_SDIO to pin VDD3P3_RTC. The regulator then
outputs a voltage of 3.3V which is the voltage of pin VDD3P3_RTC. When SDIO_TIEH == 0, the inner loop
ties the regulator output to the voltage of VREF, which is typically 1.8V.

3. DREFH_SDIO, DREFM_SDIO and DREFL_SDIO could be used to tune the reference voltage VREF slightly.
However, it is recommended that users do not change the value of these registers, since it may affect
the stability of the inner loop.

4. When the regulator output is 3.3V or 1.8V, the output current comes from the pin VDD3P3_RTC.

Figure 9.3-3 shows the structure of a flash voltage regulator.

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Figure 9.3-3. Flash Voltage Regulator

9.3.5 Brownout Detector

The brownout detector checks the voltage of pin VDD3P3_RTC. If the voltage drops rapidly and becomes too
low, the detector would trigger a signal to shut down some power-consuming blocks (such as LNA, PA, etc.)
to allow extra time for the digital block to save and transfer important data. The power consumption of the
detector is ultra low. It remains enabled whenever the chip is powered on, with an adjustable trigger level
calibrated around 2.5V.

1. As the output of the brownout detector, RTC_CNTL_BROWN_OUT_DET goes high when the voltage of
pin VDD3P3_RTC is lower than the threshold value.

2. RTC_CNTL_DBROWN_OUT_THRES[2:0] is used to tune the threshold voltage, which is usually calibrated

around 2.5V.

Figure 9.3-4 shows the structure of a brownout detector.

Figure 9.3-4. Brownout Detector

9.3.6 RTC Module

The RTC module is designed to handle the entry into, and exit from, the low-power mode, and control the
clock sources, PLL, power switch and isolation cells to generate power-gating, clock-gating, and reset signals.
As for the low-power management, RTC is composed of the following modules (see Figure 9.3-5):

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• RTC main state machine: records the power state.

• Digital & analog power controller: generates actual power-gating/clock-gating signals for digital parts and
analog parts.

• Sleep & wakeup controller: handles the entry into & exit from the low-power mode.

• Timers: include RTC main timer, ULP coprocessor timer and touch timer.

• Low-Power processor and sensor controllers: include ULP coprocessor, touch controller, SAR ADC
controller, etc.

• Retention memory:

– RTC slow memory: an 8 KB SRAM, mostly used as retention memory or instruction & data memory
for the ULP coprocessor. The CPU accesses it through the APB, starting from address
0x50000000.

– RTC fast memory: an 8 KB SRAM, mostly used as retention memory. The CPU accesses it through
IRAM0/DRAM0. Fast RTC memory is about 10 times faster than the RTC slow memory.

• Retention registers: always-on registers of 8 x 32 bits, serving as data storage.

• RTC IO pads: 18 always-on analog pads, usually functioning as wake-up sources.

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Figure 9.3-5. RTC Structure

9.3.7 Low-Power Clocks

In the low-power mode, the 40 MHz crystal and PLL are usually powered down to save power. But clocks are
needed for the chip to remain active in the low-power mode.

For the RTC core, there are five possible clock sources:

• external low-speed (32.768 kHz) crystal clock XTL32K_CLK,

• external high-speed (2 MHz ~ 40 MHz) crystal clock XTAL_DIV_CLK,

• internal RC oscillator RC_SLOW_CLK (typically about 150 kHz and adjustable),

• internal 8-MHz oscillator RC_FAST_CLK, and

• internal 31.25-kHz clock RC_FAST_DIV_CLK (derived from the internal 8-MHz oscillator divided by 256).

With these clocks, RTC_FAST_CLK and RTC_SLOW_CLK is derived. By default, RTC_FAST_CLK is

RC_FAST_CLK while RTC_SLOW_CLK is RC_SLOW_CLK. For details, please see Figure 9.3-6.

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Selection Signal
RTC Timer
RC_SLOW_CLK
0
XTL32K_CLK
RTC_SLOW_CLK
1 RTC Main State
RC_FAST_DIV_CLK
2

PMU
RTC Slow Clock

ULP Coprocessor

Selection Signal

XTAL_DIV_CLK
Sensor Controller
0
RTC_FAST_CLK

RC_FAST_CLK ESP32
1 RTC Memory

RTC Fast Clock

RTC Registers

RTC Clock

Figure 9.3-6. RTC Low-Power Clocks

For the digital core, LOW_POWERE_CLK is switched among four sources. For details, please see Figure
9.3-7.

Selection Signals

RC_SLOW_CLK

RTC_SLOW_CLK
LP_MUX

LOW_POWER_CLK
Wireless

RC_FAST_CLK

XTL_CLK

Figure 9.3-7. Digital Low-Power Clocks

Low-power Clock

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9.3.8 Power-Gating Implementation

Figure 9.3-8. RTC States

The switch among power-gating states can be see in Figure 9.3-8. The actual power-control signals could also
be set by software as force-power-up (FPU) or force-power-down (FPD). Since the power domains can be
power-gated independently, there are many combinations for different applications. Table 9.3-1 shows how
the power domains in ESP32 are controlled.

Table 9.3-1. RTC Power Domains

RTC Main State S/W Options

Power Domains Notes*
DIG Active RTC Active RTC Sleep FPU FPD
RTC Digital Core ON ON ON N N 1
RTC Peripherals ON ON OFF Y Y 2
RTC
RTC Slow Memory ON OFF OFF Y Y 3
RTC Fast Memory ON OFF OFF Y Y 4
Digital Core ON OFF OFF Y Y 5
Wi-Fi ON OFF OFF Y Y 6
Digital
ROM ON OFF OFF Y Y -
Internal SRAM ON OFF OFF Y Y 7
40 MHz Crystal ON OFF OFF Y Y -
PLL ON OFF OFF Y Y -
Analog
8 MHz OSC ON OFF OFF Y Y -
Radio - - - Y Y -
Notes*:
1. The power-domain RTC core is the “always-on” power domain, and the FPU/FPD option is not
available.
2. The power-domain RTC peripherals include most of the fast logic in RTC, including the ULP co-processor,
sensor controllers, etc.
3. The power-domain RTC slow memory should be forced to power on when it is used as retention memory, or
when the ULP co-processor is working.
4. The power-domain RTC fast memory should be forced to power on, when it is used as retention
memory.

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5. When the power-domain digital core is powered down, all included in power domains are powered
down.
6. The power-domain Wi-Fi includes the Wi-Fi MAC and BB.
7. Each internal SRAM can be power-gated independently.

9.3.9 Predefined Power Modes

In ESP32, we recommend that you always use the predefined power modes first, before trying to tune each
power control signal. The predefined power modes should cover most scenarios:

• Active mode

– The CPU is clocked at XTAL_DIV_N (40 MHz/26 MHz) or PLL (80 MHz/160 MHz/240 MHz).

– The chip can receive, transmit, or listen.

• Modem-sleep mode

– The CPU is operational and the clock is configurable.

– The Wi-Fi/Bluetooth baseband is clock-gated or powered down. The radio is turned off.

– Current consumption: ∼30 mA with 80 MHz PLL.

– Current consumption: ∼3 mA with 2 MHz XTAL.

– Immediate wake-up.

• Light-sleep mode

– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.

– The clock in the digital core is gated. The CPUs are stalled.

– The ULP coprocessor and touch controller can be periodically triggered by monitor sensors.

– Current consumption: ∼ 800 µA.

– Wake-up latency: less than 1 ms.

• Deep-sleep mode

– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL and radio are disabled.

– The digital core is powered down. The CPU context is lost.

– The supply voltage to the RTC core drops to 0.7V.

– 8 x 32 bits of data are kept in general-purpose retention registers.

– The RTC memory and fast RTC memory can be retained.

– Current consumption: ∼ 6.5 µA.

– Wake-up latency: less than 1 ms.

– Recommended for ultra-low-power infrequently-connected Wi-Fi/Bluetooth applications.

• Hibernatation mode

– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.

– The digital core is powered down. The CPU context is lost.

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– The RTC peripheral domain is powered down.

– The supply voltage to the RTC core drops to 0.7V.

– 8 x 32 bits of data are kept in general-purpose retention registers.

– The RTC memory and fast RTC memory are powered down.

– Current consumption: ∼ 4.5 µA.

– Wake-up source: RTC timer only.

– Wake-up latency: less than 1 ms.

– Recommended for ultra-low-power infrequently-connected Wi-Fi/Bluetooth applications.

Figure 9.3-9. Power Modes

By default, ESP32 first enters the Modem-sleep mode after a system reset and can be configured to Active
mode when transmitting or receiving packets. After the CPU stalls for a while, the chip can enter several
low-power modes. It is up to the user to select the mode that best balances power consumption, wake-up
latency and available wake-up sources. For details, please see Figure 9.3-9.
Please note that the predefined power mode could be further optimized and adapted to any application.

9.3.10 Wakeup Source

The ESP32 supports various wake-up sources, which could wake up the CPU in different sleep modes. The
wake-up source is determined by RTC_CNTL_WAKEUP_ENA, as shown in Table 9.3-2.

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Table 9.3-2. Wake-up Source

WAKEUP_ENA Wake-up Source1 Light-sleep Deep-sleep Hibernation

0x1 EXT02 Y Y -
0x2 EXT13 Y Y Y
0x4 GPIO4 Y Y -
0x8 RTC timer Y Y Y
0x10 SDIO5 Y - -
0x20 Wi-Fi6 Y - -
0x40 UART0 7 Y - -
0x80 UART1 7 Y - -
0x100 TOUCH Y Y -
0x200 ULP co-processor Y Y -
0x400 BT 6 Y - -
1 All wakeup sources can also be configured as the causes to reject sleep, ex-
cept UART.
2 EXT0 can only wake up the chip in light-sleep/deep-sleep mode.
If RTC_CNTL_EXT_WAKEUP0_LV is 1, it is pad high-level triggered; otherwise, it
is low-level triggered. Users can set RTCIO_EXT_WAKEUP0_SEL[4:0] to select
one of the RTC PADs to be the wake-up source.
3 EXT1 is especially designed to wake up the chip from any sleep mode, and it
also supports multiple pads’ combinations.
First, RTC_CNTL_EXT_WAKEUP1_SEL[17:0] should be configured
with the bitmap of PADS selected as a wake-up source. Then, if
RTC_CNTL_EXT_WAKEUP1_LV is 1, as long as one of the PADs is at high-voltage
level, it can trigger a wake-up. However, if RTC_CNTL_EXT_WAKEUP1_LV is 0,
it needs all selected PADs to be at low-voltage level to trigger a wake-up.
Note that the EXT1 hold time should be longer than three RTC slow
clock cycles, otherwise the signal status will not be captured in
RTC_CNTL_EXT_WAKEUP1_STATUS.
4 In Deep-sleep mode, only RTC GPIOs (not DIGITAL GPIOs) can work as wakeup
source.
5 Wake-up is triggered by receiving any SDIO command.
6 To wake up the chip with a Wi-Fi or BT source, the power mode switches be-
tween the Active, Modem- and Light-sleep modes. The CPU, Wi-Fi, Bluetooth,
and radio are woken up at predetermined intervals to keep Wi-Fi/BT connec-
tions active.
7 Wake-up is triggered when the number or positive edges of RxD signal is greater
than or equal to (UART_ACTIVE_THRESHOLD+2). Note that the RxD signal can-
not be input through GPIO Matrix but only through IO_MUX.

9.3.11 Reject Sleep

ESP32 implements a hardware mechanism that equips the chip with the ability to reject to sleep, which
prevents the chip from going to sleep unexpectedly when some peripherals are still working but not detected

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by the CPU, thus guaranteeing the proper functioning of the peripherals.

All the wakeup sources specified in Table 9.3-2 (except UART) can also be configured as the causes to reject
sleep.

Users can configure the reject to sleep option via the following registers.

• Configure the RTC_CNTL_SLP_REJECT field to enable or disable the option to reject to sleep:

– Set RTC_CNTL_LIGHT_SLP_REJECT_EN to enable reject-to-light-sleep.

– Set RTC_CNTL_DEEP_SLP_REJECT_EN to enable reject-to-deep-sleep.

• Read RTC_CNTL_REJECT_CAUSE to check the reason for rejecting to sleep.

9.3.12 RTC Timer

The RTC timer is a 48-bit counter that can be read. The clock is RTC_SLOW_CLK. Any reset/sleep mode,
except for the power-up reset, will not stop or reset the RTC timer.

The RTC timer can be used to wake up the CPU at a designated time, and to wake up TOUCH or the ULP
coprocessor periodically.

9.3.13 RTC Boot

Since the CPU, ROM and RAM are powered down during Deep-sleep and Hibernation mode, the wake-up time
is much longer than that in Light sleep/Modem sleep, because of the ROM unpacking and data-copying from
the flash (SPI booting). There are two types of SRAM in the RTC, named slow RTC memory and fast RTC
memory, which remain powered-on in Deep-sleep mode. For small-scale codes (less than 8 KB), there are
two methods of speeding up the wake-up time, i.e. avoiding ROM unpacking and SPI booting.

The first method is to use the RTC slow memory:

1. Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL for PRO_CPU (or register

RTC_CNTL_APPCPU_STAT_VECTOR_SEL for APP_CPU) to 0.

2. Put the chip into sleep.

3. When the CPU is powered up, the reset vector starts from 0x50000000, instead of 0x40000400. ROM
unpacking & SPI boot are not needed. The code in RTC memory has to do itself some initialization for
the C program environment.

The second method is to use the fast RTC memory:

1. Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL for PRO_CPU (or register

RTC_CNTL_APPCPU_STAT_VECTOR_SEL for APP_CPU) to 1.

2. Calculate CRC for the fast RTC memory, and save the result in register
RTC_CNTL_RTC_STORE6_REG[31:0].

3. Input register RTC_CNTL_RTC_STORE7_REG[31:0] with the entry address in the fast RTC memory.

4. Put the chip into sleep.

5. When the CPU is powered up, after ROM unpacking and some necessary initialization, the CRC is
calculated again. If the result matches with register RTC_CNTL_RTC_STORE6_REG[31:0], the CPU will
jump to the entry address.

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The boot flow is shown in Figure 9.3-10.

Figure 9.3-10. ESP32 Boot Flow

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9.4 Register Summary

Notes:

• The registers listed below have been grouped according to their functionality. This particular grouping
does not reflect the exact sequential order in which they are stored in memory.

• The base address for registers is 0x60008000 when accessed by AHB, and 0x3FF48000 when
accessed by DPORT bus.

Name Description Address Access

RTC option register
RTC_CNTL_OPTIONS0_REG Configure RTC options 0x3FF48000 R/W
Control and configuration of RTC timer registers
RTC_CNTL_SLP_TIMER0_REG RTC sleep timer 0x3FF48004 R/W
RTC_CNTL_SLP_TIMER1_REG RTC sleep timer, alarm and control 0x3FF48008 R/W
RTC_CNTL_TIME_UPDATE_REG Update control of RTC timer 0x3FF4800C RO
RTC_CNTL_TIME0_REG RTC timer low 32 bits 0x3FF48010 RO
RTC_CNTL_TIME1_REG RTC timer high 16 bits 0x3FF48014 RO
RTC_CNTL_STATE0_REG RTC sleep, SDIO and ULP control 0x3FF48018 R/W
RTC_CNTL_TIMER1_REG CPU stall enable 0x3FF4801C R/W
Slow clock and touch controller config-
RTC_CNTL_TIMER2_REG 0x3FF48020 R/W
uration
RTC_CNTL_TIMER5_REG Minimal sleep cycles in slow clock 0x3FF4802C R/W
Reset state and wakeup control registers
RTC_CNTL_RESET_STATE_REG Reset state control and cause of CPUs 0x3FF48034 RO
RTC_CNTL_WAKEUP_STATE_REG Wake-up filter, enable and cause 0x3FF48038 RO
Configuration of wake-up at low/high
RTC_CNTL_EXT_WAKEUP_CONF_REG 0x3FF48060 R/W
level
Selection of pads for external wake-up
RTC_CNTL_EXT_WAKEUP1_REG 0x3FF480CC R/W
and wake-up clear bit
RTC_CNTL_EXT_WAKEUP1_STATUS_REG External wake-up status 0x3FF480D0 RO
RTC interrupt control and status registers
RTC_CNTL_INT_ENA_REG Interrupt enable bits 0x3FF4803C R/W
RTC_CNTL_INT_RAW_REG Raw interrupt status 0x3FF48040 RO
RTC_CNTL_INT_ST_REG Masked interrupt status 0x3FF48044 RO
RTC_CNTL_INT_CLR_REG Interrupt clear bits 0x3FF48048 WO
RTC general purpose retention registers
RTC_CNTL_STORE0_REG General purpose retention register 0 0x3FF4804C R/W
RTC_CNTL_STORE1_REG General purpose retention register 1 0x3FF48050 R/W
RTC_CNTL_STORE2_REG General purpose retention register 2 0x3FF48054 R/W
RTC_CNTL_STORE3_REG General purpose retention register 3 0x3FF48058 R/W
RTC_CNTL_STORE4_REG General purpose retention register 4 0x3FF480B0 R/W
RTC_CNTL_STORE5_REG General purpose retention register 5 0x3FF480B4 R/W
RTC_CNTL_STORE6_REG General purpose retention register 6 0x3FF480B8 R/W
RTC_CNTL_STORE7_REG General purpose retention register 7 0x3FF480BC R/W

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Name Description Address Access

Internal power management registers
RTC_CNTL_ANA_CONF_REG Power-up/down configuration 0x3FF48030 R/W
RTC_CNTL_VREG_REG Internal power distribution and control 0x3FF4807C R/W
RTC_CNTL_PWC_REG RTC domain power management 0x3FF48080 R/W
RTC_CNTL_DIG_PWC_REG Digital domain power management 0x3FF48084 R/W
RTC_CNTL_DIG_ISO_REG Digital domain isolation control 0x3FF48088 RO
RTC watchdog configuration and control registers
RTC_CNTL_WDTCONFIG0_REG WDT Configuration register 0 0x3FF4808C R/W
RTC_CNTL_WDTCONFIG1_REG WDT Configuration register 1 0x3FF48090 R/W
RTC_CNTL_WDTCONFIG2_REG WDT Configuration register 2 0x3FF48094 R/W
RTC_CNTL_WDTCONFIG3_REG WDT Configuration register 3 0x3FF48098 R/W
RTC_CNTL_WDTCONFIG4_REG WDT Configuration register 4 0x3FF4809C R/W
RTC_CNTL_WDTFEED_REG Watchdog feed register 0x3FF480A0 WO
RTC_CNTL_WDTWPROTECT_REG Watchdog write protect register 0x3FF480A4 R/W
Miscellaneous RTC configuration registers
RTC_CNTL_EXT_XTL_CONF_REG XTAL control by external pads 0x3FF4805C R/W
RTC_CNTL_SLP_REJECT_CONF_REG Reject cause and enable control 0x3FF48064 R/W
RTC_CNTL_CPU_PERIOD_CONF_REG CPU period select 0x3FF48068 R/W
RTC_CNTL_CLK_CONF_REG Configuration of RTC clocks 0x3FF48070 R/W
RTC_CNTL_SDIO_CONF_REG SDIO configuration 0x3FF48074 R/W
RTC_CNTL_SW_CPU_STALL_REG Stall of CPUs 0x3FF480AC R/W
RTC_CNTL_LOW_POWER_ST_REG RTC state register 0x3FF480C0 RO
RTC_CNTL_HOLD_FORCE_REG RTC pad hold register 0x3FF480C8 R/W
RTC_CNTL_BROWN_OUT_REG Brownout management 0x3FF480D4 R/W

9.5 Registers
The addresses in parenthesis besides register names are the register addresses relative to the Low-power
Management (RTC) base address provided in Table 3.3-6 Peripheral Address Mapping in Chapter 3 System
and Memory. The absolute register addresses are listed in Section 9.4 Register Summary.

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Register 9.1. RTC_CNTL_OPTIONS0_REG (0x0000)

RS T
E_ RS

C0
RT _CN L_B S_I RE_ ORC _PU
RT CN _B S_I _F OLW _PD

RT NTL W_ C_ RC CE_ U
CN SW RO RC PU D
RT _CN L_X _F EEP SLE EEP

RT _CN L_B PLL CE U 8M

T

_C
RT _CN L_B S_I _F CE 8M
RC NO

C _S I2 FO R _P
_ P FO E_ P
RT _CN L_B S_F _F CE U
RT CN _B S_F RCE W_ D

U_
C T IA O _ 8M

C T TL OR _F EP

PU
C T B OR _P W_
C T IA 2C OR _P
C_ TL IA O OL _P

PC U_ PD
C T TL L _ SL
C T IA O F E
C_ TL IA 2C F E
C T IA 2C OR _

C_ TL B_ C_ FO E
FO E_

C T B _I CE U
C T B _I F D

CP
RT _CN L_B S_C RE_ ORC

RT _CN L_B _I2 2C_ ORC

ST U_R T
ST
RT _CN L_B PLL OR _P
RT _CN L_B PLL 2C_ _P

OC
RT _CN L_B _F CE OL
RT _CN L_X S_S RCE NO

TL _AP CP E_
P RS
P_ RC

RT CN _B LL OR D

PP
C T B _F CE
C_ TL BP _F _P

R
C T IA O F
RA O
G_ RA T

_P

_A
RT _CN L_B S_C RE_
W P_F
_D W RS

LL

LL
TL G_ S_

C T IA O

TA
RT _CN L_B S_C
CN _D SY

_S
C_ TL W_

_
C T IA

W
RT _CN L_B
RT _CN L_S

_S

_S
TL
)
ed
C T

C T
RT _CN

RT _CN

CN
rv
se

C_

C_
C

C
(re
RT

RT

RT
31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_SW_SYS_RST SW system reset. (WO)

RTC_CNTL_DG_WRAP_FORCE_NORST The digital core forces no reset in deep sleep. (R/W)

RTC_CNTL_DG_WRAP_FORCE_RST The digital core can force a reset in deep sleep. (R/W)

RTC_CNTL_BIAS_CORE_FORCE_PU BIAS_CORE force power up. (R/W)

RTC_CNTL_BIAS_CORE_FORCE_PD BIAS_CORE force power down. (R/W)

RTC_CNTL_BIAS_CORE_FOLW_8M BIAS_CORE follow CK8M. (R/W)

RTC_CNTL_BIAS_I2C_FORCE_PU BIAS_I2C force power up. (R/W)

RTC_CNTL_BIAS_I2C_FORCE_PD BIAS_I2C force power down. (R/W)

RTC_CNTL_BIAS_I2C_FOLW_8M BIAS_I2C follow CK8M. (R/W)

RTC_CNTL_BIAS_FORCE_NOSLEEP BIAS_SLEEP force no sleep. (R/W)

RTC_CNTL_BIAS_FORCE_SLEEP BIAS_SLEEP force sleep. (R/W)

RTC_CNTL_BIAS_SLEEP_FOLW_8M BIAS_SLEEP follow CK8M. (R/W)

RTC_CNTL_XTL_FORCE_PU Crystal force power up. (R/W)

RTC_CNTL_XTL_FORCE_PD Crystal force power down. (R/W)

RTC_CNTL_BBPLL_FORCE_PU BB_PLL force power up. (R/W)

RTC_CNTL_BBPLL_FORCE_PD BB_PLL force power down. (R/W)

RTC_CNTL_BBPLL_I2C_FORCE_PU BB_PLL_I2C force power up. (R/W)

RTC_CNTL_BBPLL_I2C_FORCE_PD BB_PLL _I2C force power down. (R/W)

RTC_CNTL_BB_I2C_FORCE_PU BB_I2C force power up. (R/W)

RTC_CNTL_BB_I2C_FORCE_PD BB_I2C force power down. (R/W)

Continued on the next page...

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Register 9.1. RTC_CNTL_OPTIONS0_REG (0x0000)

Continued from the previous page...

RTC_CNTL_SW_PROCPU_RST PRO_CPU SW reset. (WO)

RTC_CNTL_SW_APPCPU_RST APP_CPU SW reset. (WO)

RTC_CNTL_SW_STALL_PROCPU_C0 described under RTC_CNTL_SW_CPU_STALL_REG. (R/W)

RTC_CNTL_SW_STALL_APPCPU_C0 described under RTC_CNTL_SW_CPU_STALL_REG. (R/W)

Register 9.2. RTC_CNTL_SLP_TIMER0_REG (0x0004)

31 0

0x000000000 Reset

RTC_CNTL_SLP_TIMER0_REG RTC sleep timer low 32 bits. (R/W)

Register 9.3. RTC_CNTL_SLP_TIMER1_REG (0x0008)

N
_E
RM
LA
_A
ER

HI
M

L_
TI

VA
N_

P_
AI

SL
M
L_

L_
)
ed

NT

NT
rv

C
se

C_

C_
(re

RT

RT

31 17 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset

RTC_CNTL_MAIN_TIMER_ALARM_EN Timer alarm enable bit. (R/W)

RTC_CNTL_SLP_VAL_HI RTC sleep timer high 16 bits. (R/W)

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Register 9.4. RTC_CNTL_TIME_UPDATE_REG (0x000C)

VA TE
E_ DA

D
LI
IM UP
_T E_
TL IM
CN _T
C_ TL

d)
ve
RT _CN

r
se
C

(re
RT

31 30 29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_TIME_UPDATE Set 1: to update register with RTC timer. (WO)

RTC_CNTL_TIME_VALID Indicates that the register is updated. (RO)

Register 9.5. RTC_CNTL_TIME0_REG (0x0010)

31 0

0x000000000 Reset

RTC_CNTL_TIME0_REG RTC timer low 32 bits. (RO)

Register 9.6. RTC_CNTL_TIME1_REG (0x0014)

HI
E_
M
TI
L_
)
ed

NT
rv

C
se

C_
(re

RT

31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset

RTC_CNTL_TIME_HI RTC timer high 16 bits. (RO)

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Register 9.7. RTC_CNTL_STATE0_REG (0x0018)

ER N
N
IM _E
_E
_T ER
ND

LP IM
_I

_S P_T
AC P
VE
DI AK T
O_ EU
_S _W EC

CH SL
TI
CN _S _R N

OU P_
C_ TL LP _E
TL LP EJ

_T _C
RT _CN L_S EP

TL LP
C T LE

CN _U
RT _CN L_S

C_ TL
)

d)
ed
C T

ve
RT _CN

RT N
rv

r
se

C_

se
C

(re

(re
RT

RT

31 30 29 28 27 25 24 23 22 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_SLEEP_EN Sleep enable bit. (R/W)

RTC_CNTL_SLP_REJECT Sleep reject bit. (R/W)

RTC_CNTL_SLP_WAKEUP Sleep wake-up bit. (R/W)

RTC_CNTL_SDIO_ACTIVE_IND SDIO active indication. (RO)

RTC_CNTL_ULP_CP_SLP_TIMER_EN ULP coprocessor timer enable bit. (R/W)

RTC_CNTL_TOUCH_SLP_TIMER_EN Touch timer enable bit. (R/W)

Register 9.8. RTC_CNTL_TIMER1_REG (0x001C)

N
_E
LL
A
ST
U_
CP
L_
)
ed

NT
rv

C
se

C_
(re

31 1
RT
0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

RTC_CNTL_CPU_STALL_EN CPU stall enable bit. (R/W)

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Register 9.9. RTC_CNTL_TIMER2_REG (0x0020)

T
AI
_W
F

RT
F
_O

TA
_S
8M

H
CK

UC
E_

TO
M

P_
I
_T

PC
IN

UL
M
L_

L_

)
ed
NT

NT

rv
C

se
C_

C_

(re
RT

RT
31 24 23 15 14 0

0x001 0x010 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MIN_TIME_CK8M_OFF Minimal amount of cycles in RTC_SLOW_CLK to power down

CK8M. (R/W)

RTC_CNTL_ULPCP_TOUCH_START_WAIT Awaited cycles in RTC_SLOW_CLK before

ULP coprocessor/touch controller starts working. (R/W)

Register 9.10. RTC_CNTL_TIMER5_REG (0x002C)

L
VA
P_
L
_S
IN
M
L_
)

)
ed

ed
T
CN
rv

rv
se

se
C_
(re

(re
RT

31 16 15 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x080 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MIN_SLP_VAL Minimal amount of sleep cycles in RTC_SLOW_CLK. (R/W)

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Register 9.11. RTC_CNTL_ANA_CONF_REG (0x0030)

RC PU
PD
M _P U
U

C d VT 2C _P

FO E_
E_
_P

ON U
U
EN PU

RT rve _P F_I US

A _ RC
_P
2C
C_ d) KG C_

se TL XR PB

LL FO
_I
RT rve L_C _I2

(re CN _T _

_P A _
X
C_ TL FR
se T LL

TL LL
(re _CN L_P

CN _P
RT _CN L_R

C_ TL
RT _CN )

d)
C T

C T

ve
RT _CN

RT CN

r
se
C

(re
RT

31 30 29 28 27 26 25 24 23 22 0

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_PLL_I2C_PU 1: PLL_I2C power up, otherwise power down. (R/W)

RTC_CNTL_CKGEN_I2C_PU 1: CKGEN_I2C power up, otherwise power down. (R/W)

RTC_CNTL_RFRX_PBUS_PU 1: RFRX_PBUS power up, otherwise power down. (R/W)

RTC_CNTL_TXRF_I2C_PU 1: TXRF_I2C power up, otherwise power down. (R/W)

RTC_CNTL_PVTMON_PU 1: PVTMON power up, otherwise power down. (R/W)

RTC_CNTL_PLLA_FORCE_PU PLLA force power up. (R/W)

RTC_CNTL_PLLA_FORCE_PD PLLA force power down. (R/W)

Register 9.12. RTC_CNTL_RESET_STATE_REG (0x0034)

R_ L
L
TO SE
SE
EC R_

U
U

CP
CP
_V TO

RO
PP
AT C
ST _VE

_P
_A
U_ AT

SE

SE
CP _ST

AU

AU
_C

_C
PP PU

ET

ET
_A C
TL RO

ES

ES
CN _P

_R

_R
C_ TL

TL

TL
)
ed

RT _CN

CN

CN
rv
se

C_

C_
C
(re

RT

RT

RT

31 14 13 12 11 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x x x x x x Reset

RTC_CNTL_PROCPU_STAT_VECTOR_SEL PRO_CPU state vector selection. (R/W)

RTC_CNTL_APPCPU_STAT_VECTOR_SEL APP_CPU state vector selection. (R/W)

RTC_CNTL_RESET_CAUSE_APPCPU Reset cause for APP_CPU. (RO)

RTC_CNTL_RESET_CAUSE_PROCPU Reset cause for PRO_CPU. (RO)

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Register 9.13. RTC_CNTL_WAKEUP_STATE_REG (0x0038)

ER
ILT
F

E
P_

US
NA
EU

CA
E
AK

P_

P_
_W

EU

EU
IO

AK

AK
GP

W
L_

L_

L_
)
ed

NT

T
CN

CN
rv

C
se

C_

C_

C_
(re

RT

RT

RT
31 23 22 21 11 10 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0x000 Reset

RTC_CNTL_GPIO_WAKEUP_FILTER Enable filter for GPIO wake-up event. (R/W)

RTC_CNTL_WAKEUP_ENA Wake-up enable bitmap. (R/W)

RTC_CNTL_WAKEUP_CAUSE Wake-up cause. (RO)

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Register 9.14. RTC_CNTL_INT_ENA_REG (0x003C)

RT _CN L_W E_V INT NA NA

A
RT _CN L_T _C NT_ INT NA

IN NA
EN
A

EU INT A
C T IM P_ E _E

TL LP IDL A EN
C T LP _I T_ _E

P_ _E
AK T_ EN

T_
RT _CN L_U CH OU INT

RT _CN L_S T_IN ID_ NA

CN _S O_ EN T_

_W EC T_
C_ TL DI T_ IN
C T D AL _E
C T OU N_ _

LP EJ IN
RT _CN L_T W ER

_S _R E_
C T RO TIM
RT _CN L_B IN_
C T A
RT _CN L_M
)
ed

C T
RT _CN
rv
se

C
(re

RT
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MAIN_TIMER_INT_ENA The interrupt enable bit for the RTC_CNTL_MAIN_TIMER_INT

interrupt. (R/W)

RTC_CNTL_BROWN_OUT_INT_ENA The interrupt enable bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (R/W)

RTC_CNTL_TOUCH_INT_ENA The interrupt enable bit for the RTC_CNTL_TOUCH_INT interrupt.

(R/W)

RTC_CNTL_ULP_CP_INT_ENA The interrupt enable bit for the RTC_CNTL_ULP_CP_INT interrupt.

(R/W)

RTC_CNTL_TIME_VALID_INT_ENA The interrupt enable bit for the RTC_CNTL_TIME_VALID_INT in-

terrupt. (R/W)

RTC_CNTL_WDT_INT_ENA The interrupt enable bit for the RTC_CNTL_WDT_INT interrupt. (R/W)

RTC_CNTL_SDIO_IDLE_INT_ENA The interrupt enable bit for the RTC_CNTL_SDIO_IDLE_INT inter-

rupt. (R/W)

RTC_CNTL_SLP_REJECT_INT_ENA The interrupt enable bit for the RTC_CNTL_SLP_REJECT_INT in-

terrupt. (R/W)

RTC_CNTL_SLP_WAKEUP_INT_ENA The interrupt enable bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (R/W)

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Register 9.15. RTC_CNTL_INT_RAW_REG (0x0040)

RT _CN L_W E_V INT AW AW

W
RT _CN L_T _C NT_ INT AW

IN AW
W

RA
AK T_ RAW
C T IM P_ R _R
C T LP _I T_ _R

TL LP IDL W RA

P_ _R
T_
RT _CN L_S T_IN ID_ AW
RT _CN L_U CH OU INT

CN _S O_ RA T_

EU INT
_W EC T_
C_ TL DI T_ IN
C T D AL _R
C T OU N_ _

LP EJ IN
RT _CN L_T W ER

_S _R E_
C T RO TIM
RT _CN L_B IN_
C T A
RT _CN L_M
d)

C T
ve

RT _CN
r
se

C
(re

RT
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MAIN_TIMER_INT_RAW The raw interrupt status bit for the

RTC_CNTL_MAIN_TIMER_INT interrupt. (RO)

RTC_CNTL_BROWN_OUT_INT_RAW The raw interrupt status bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (RO)

RTC_CNTL_TOUCH_INT_RAW The raw interrupt status bit for the RTC_CNTL_TOUCH_INT interrupt.
(RO)

RTC_CNTL_ULP_CP_INT_RAW The raw interrupt status bit for the RTC_CNTL_ULP_CP_INT interrupt.
(RO)

RTC_CNTL_TIME_VALID_INT_RAW The raw interrupt status bit for the

RTC_CNTL_TIME_VALID_INT interrupt. (RO)

RTC_CNTL_WDT_INT_RAW The raw interrupt status bit for the RTC_CNTL_WDT_INT interrupt. (RO)

RTC_CNTL_SDIO_IDLE_INT_RAW The raw interrupt status bit for the RTC_CNTL_SDIO_IDLE_INT

interrupt. (RO)

RTC_CNTL_SLP_REJECT_INT_RAW The raw interrupt status bit for the

RTC_CNTL_SLP_REJECT_INT interrupt. (RO)

RTC_CNTL_SLP_WAKEUP_INT_RAW The raw interrupt status bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO)

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Register 9.16. RTC_CNTL_INT_ST_REG (0x0044)

ST
RT _CN L_T _IN NT_ INT T

IN T
C T IM T_ S _S
C T AR _I T_ _S

ST

P_ _S
AK T_ ST

T_
RT _CN L_S CH OU INT

CN _S O_ ST T_

EU INT
_W EC T_
RT _CN L_W E_V ST T

C_ TL DI T_ IN
C T OU N_ _

LP J N
RT CN _S _IN ID_
RT _CN L_T W ER

I
_S _R E_
C T RO TIM

C_ TL D AL

TL LP IDL
E
RT _CN L_B IN_

T
C T A
RT _CN L_M
d)

C T
ve

RT _CN
r
se

C
(re

RT
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MAIN_TIMER_INT_ST The masked interrupt status bit for the

RTC_CNTL_MAIN_TIMER_INT interrupt. (RO)

RTC_CNTL_BROWN_OUT_INT_ST The masked interrupt status bit for the

RTC_CNTL_BROWN_OUT_INT interrupt. (RO)

RTC_CNTL_TOUCH_INT_ST The masked interrupt status bit for the RTC_CNTL_TOUCH_INT inter-
rupt. (RO)

RTC_CNTL_SAR_INT_ST The masked interrupt status bit for the RTC_CNTL_SAR_INT interrupt.
(RO)

RTC_CNTL_TIME_VALID_INT_ST The masked interrupt status bit for the

RTC_CNTL_TIME_VALID_INT interrupt. (RO)

RTC_CNTL_WDT_INT_ST The masked interrupt status bit for the RTC_CNTL_WDT_INT interrupt.
(RO)

RTC_CNTL_SDIO_IDLE_INT_ST The masked interrupt status bit for the

RTC_CNTL_SDIO_IDLE_INT interrupt. (RO)

RTC_CNTL_SLP_REJECT_INT_ST The masked interrupt status bit for the

RTC_CNTL_SLP_REJECT_INT interrupt. (RO)

RTC_CNTL_SLP_WAKEUP_INT_ST The masked interrupt status bit for the

RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO)

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Register 9.17. RTC_CNTL_INT_CLR_REG (0x0048)

RT _CN L_W E_V CL LR LR

R
RT _CN L_T _IN NT_ INT LR

IN LR
CL
TL LP IDL R CLR

AK T_ CLR
C T IM T_ C _C
C T AR _I T_ _C

P_ _C
T_
RT _CN L_S CH OU INT

CN _S O_ CL T_

EU INT
_W EC T_
C_ TL DI T_ IN
C T OU N_ _

LP EJ IN
C T D AL R
RT _CN L_S T_IN ID_
RT _CN L_T W ER

_S _R E_
C T RO TIM
RT _CN L_B IN_
C T A
RT _CN L_M
)
ed

C T
RT _CN
rv
se

C
(re

RT
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_MAIN_TIMER_INT_CLR Set this bit to clear the RTC_CNTL_MAIN_TIMER_INT interrupt.

(WO)

RTC_CNTL_BROWN_OUT_INT_CLR Set this bit to clear the RTC_CNTL_BROWN_OUT_INT interrupt.

(WO)

RTC_CNTL_TOUCH_INT_CLR Set this bit to clear the RTC_CNTL_TOUCH_INT interrupt. (WO)

RTC_CNTL_SAR_INT_CLR Set this bit to clear the RTC_CNTL_SAR_INT interrupt. (WO)

RTC_CNTL_TIME_VALID_INT_CLR Set this bit to clear the RTC_CNTL_TIME_VALID_INT interrupt.

(WO)

RTC_CNTL_WDT_INT_CLR Set this bit to clear the RTC_CNTL_WDT_INT interrupt. (WO)

RTC_CNTL_SDIO_IDLE_INT_CLR Set this bit to clear the RTC_CNTL_SDIO_IDLE_INT interrupt.

(WO)

RTC_CNTL_SLP_REJECT_INT_CLR Set this bit to clear the RTC_CNTL_SLP_REJECT_INT interrupt.

(WO)

RTC_CNTL_SLP_WAKEUP_INT_CLR Set this bit to clear the RTC_CNTL_SLP_WAKEUP_INT interrupt.

(WO)

Register 9.18. RTC_CNTL_STOREn_REG (n: 0-3) (0x004C+4*n)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W)

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Register 9.19. RTC_CNTL_LOW_POWER_ST_REG (0x00C0)

P
EU
L
DE

AK
I
N_

W
R_
I
E_

FO
AT

Y_
ST

RD
N_

C_
AI

RT
M
L_

L_
)

d)

d)
ed

NT

T
ve

ve
CN
rv

r
se

se

se
C_

C_
(re

(re

(re
RT

RT
31 28 27 26 20 19 18 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_RTC_RDY_FOR_WAKEUP The value 1 indicates the RTC is ready to be triggered by any

wakeup source. (RO)

RTC_CNTL_MAIN_STATE_IN_IDLE Indicates the RTC state.

• 0: the chip can be either

– in sleep modes.

– entering sleep modes. In this case, wait until RTC_CNTL_RTC_RDY_FOR_WAKEUP bit

is set, then you can wake up the chip.

– exiting sleep mode. In this case, RTC_CNTL_MAIN_STATE_IN_IDLE will eventually be-

come 1.

• 1: the chip is not in sleep modes (i.e. running normally).

(RO)

Register 9.20. RTC_CNTL_EXT_XTL_CONF_REG (0x005C)

TR N
V
_C _E
_L
XT TR
_E _C
TL XT
_X _E
TL TL
CN _X
C_ TL

)
ed
RT _CN

rv
se
C

(re
RT

31 30 29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_XTL_EXT_CTR_EN Enable control XTAL with external pads. (R/W)

RTC_CNTL_XTL_EXT_CTR_LV 0: power down XTAL at high level, 1: power down XTAL at low level.
(R/W)

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Register 9.21. RTC_CNTL_EXT_WAKEUP_CONF_REG (0x0060)

V
P0 V
_L
EU _L
AK P1
_W EU
XT AK
_E _W
T L XT
CN _E
C_ TL

d)
ve
RT _CN

r
se
C

(re
RT

31 30 29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_EXT_WAKEUP1_LV 0: external wake-up at low level, 1: external wake-up at high level.

(R/W)

RTC_CNTL_EXT_WAKEUP0_LV 0: external wake-up at low level, 1: external wake-up at high level.

(R/W)

Register 9.22. RTC_CNTL_SLP_REJECT_CONF_REG (0x0064)

CT N N
O_ JE JE EN
JE _E _E
PI RE RE T_
RE CT CT
_G O_ P_ EC

N
_E
SE

TL DI SL REJ
AU

CN _S HT_ P_
_C

C_ TL IG SL
CT

RT CN _L P_
JE

C_ TL EE
RE

RT CN _D
L_

C_ TL

)
ed
NT

RT CN

rv
C

se
C_

C_

(re
RT

RT

31 28 27 26 25 24 23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_REJECT_CAUSE Sleep reject cause. (RO)

RTC_CNTL_DEEP_SLP_REJECT_EN Enable reject for deep sleep. (R/W)

RTC_CNTL_LIGHT_SLP_REJECT_EN Enable reject for light sleep. (R/W)

RTC_CNTL_SDIO_REJECT_EN Enable SDIO reject. (R/W)

RTC_CNTL_GPIO_REJECT_EN Enable GPIO reject. (R/W)

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Register 9.23. RTC_CNTL_CPU_PERIOD_CONF_REG (0x0068)

NF EL
CO _S
L_ IOD
R
PU UPE
P
SE
_C
CN RTC
_C
_
RT NTL

TL

d)
ve
C

r
C_

se
C_

(re
RT

31 30 29 28 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_RTC_CPUPERIOD_SEL CPU period selection. (R/W)

RTC_CNTL_CPUSEL_CONF CPU selection option. (R/W)

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Register 9.24. RTC_CNTL_CLK_CONF_REG (0x0070)

_ M EN EN
_S SEL

CN ENB CK8 2K_ 6_

EL

CE U
D
AS C_S

_ _ 3 25
OR _P
_P
_

M IV
C _E _X 8M N
L
C_ TL C_C CLK

RT NTL NB TAL _D
EL

C_ TL IG LK _E

_C CK8 _D
SE
_F CE

EQ
T
TC K_R

RT _CN L_D _C 8M
IV_
M R

FR
_

V
T

K8 _FO
LK

DI
_D

_D

C T IG LK
L

_
RT NTL A_C

_F

RT CN _D _C
_C M

8M

M
TL K8

K8

K8
C_ TL IG
N

CK

RT CN _D
CN _C

_C
_A

_R

_S

L_
RT NTL

RT NTL

TL

C_ TL

TL
)

C_ d)

)
ed

ed
NT

RT rve
RT CN

CN

RT CN
rv

rv
C

C
se
C_

C_

se

se
C_

C_

C_

C_

C_
(re

(re

(re
RT

RT

RT
31 30 29 28 27 26 25 24 17 16 15 14 12 11 10 9 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 Reset

RTC_CNTL_ANA_CLK_RTC_SEL RTC_SLOW_CLK sel. 0: RC_SLOW_CLK, 1: XTL32K_CLK,

2: RC_FAST_DIV_CLK. (R/W)

RTC_CNTL_RTC_FAST_CLK_SEL RTC_FAST_CLK sel. 0: XTAL div 4, 1: CK8M. (R/W)

RTC_CNTL_SOC_CLK_SEL SoC clock selection. 0: XTAL, 1: PLL, 2: CK8M, 3: APLL. (R/W)

RTC_CNTL_CK8M_FORCE_PU CK8M force power up. (R/W)

RTC_CNTL_CK8M_FORCE_PD CK8M force power down. (R/W)

RTC_CNTL_CK8M_DFREQ CK8M_DFREQ. (R/W)

RTC_CNTL_CK8M_DIV_SEL Divider = reg_rtc_cntl_ck8m_div_sel + 1. (R/W)

RTC_CNTL_DIG_CLK8M_EN Enable CK8M for digital core (no relation to RTC core). (R/W)

RTC_CNTL_DIG_CLK8M_D256_EN Enable RC_FAST_DIV_CLK for digital core (no relation to RTC

core). (R/W)

RTC_CNTL_DIG_XTAL32K_EN Enable XTL32K_CLK for digital core (no relation to RTC core). (R/W)

RTC_CNTL_ENB_CK8M_DIV 1: RC_FAST_DIV_CLK is actually CK8M, 0: RC_FAST_DIV_CLK is CK8M

divided by 256. (R/W)

RTC_CNTL_ENB_CK8M Disable CK8M and RC_FAST_DIV_CLK. (R/W)

RTC_CNTL_CK8M_DIV RC_FAST_DIV_CLK divider. 00: div128, 01: div256, 10: div512, 11: div1024.
(R/W)

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Register 9.25. RTC_CNTL_SDIO_CONF_REG (0x0074)

EN
D_
_S EG

_S O_ H Y
TL DI TIE AD

_P
R

O
O

VR E
O
RE O_V

DI

O_ RC
CN _S _ E
DI

DI

EG
R
_S

_S

C_ TL DI 8_

DI FO
_D SDI

FM
FH

C_ TL EFL

RT _CN L_S 1P
_

O
RE

C T EG
CN XPD

R
_D

C_ L_D

RT CN _R
_
RT NTL

TL

TL

)
ed
T
CN

CN

RT N

rv
C

C
C_

se
C_

C_

C_

(re
RT

RT

RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 0

0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_XPD_SDIO_VREG SW option for XPD_SDIO_VREG; active only when

reg_rtc_cntl_sdio_force == 1. (R/W)

RTC_CNTL_DREFH_SDIO SW option for DREFH_SDIO; active only when reg_rtc_cntl_sdio_force

== 1. (R/W)

RTC_CNTL_DREFM_SDIO SW option for DREFM_SDIO; active only when reg_rtc_cntl_sdio_force

== 1. (R/W)

RTC_CNTL_DREFL_SDIO SW option for DREFL_SDIO; active only when reg_rtc_cntl_sdio_force ==

1. (R/W)

RTC_CNTL_REG1P8_READY Read-only register for REG1P8_READY. (RO)

RTC_CNTL_SDIO_TIEH SW option for SDIO_TIEH; active only when reg_rtc_cntl_sdio_force == 1.

(R/W)

RTC_CNTL_SDIO_FORCE 1: use SW option to control SDIO_VREG; 0: use state machine to control

SDIO_VREG. (R/W)

RTC_CNTL_SDIO_VREG_PD_EN Power down SDIO_VREG in sleep; active only when

reg_rtc_cntl_sdio_force == 0. (R/W)

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Register 9.26. RTC_CNTL_VREG_REG (0x007C)

AK

PL
RC PU
PD

_S
S_
_D O RC PU

FO E_
E_
OS FO PD

AS
IA
T_ RC
TL BO FO E_
BO ST_ E_

BI
B
_D

_D
CN _D G_ RC

LP

AP
A

EG

EG
C_ TL RE FO

_S

DC
S_

VR

VR
RT _CN L_P G_

AS

K_

G_

G_
A
C T RE

BI

BI

SC

DI

DI
_D

_D
RT _CN L_P

L_

L_

L_
TL

TL

d)
C T

NT

NT

ve
RT _CN

CN

CN

CN
C

r
se
C_

C_

C_

C_

C_
C

(re
RT

RT

RT

RT

RT

RT
31 30 29 28 27 25 24 22 21 14 13 11 10 8 7 0

1 0 1 0 4 4 0 4 4 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_VREG_FORCE_PU RTC voltage regulator - force power up. (R/W)

RTC_CNTL_VREG_FORCE_PD RTC voltage regulator - force power down (in this case power down
means decreasing the voltage to 0.8V or lower). (R/W)

RTC_CNTL_DBOOST_FORCE_PU RTC_DBOOST force power up. (R/W)

RTC_CNTL_DBOOST_FORCE_PD RTC_DBOOST force power down. (R/W)

RTC_CNTL_DBIAS_WAK RTC_DBIAS during wake-up. (R/W)

RTC_CNTL_DBIAS_SLP RTC_DBIAS during sleep. (R/W)

RTC_CNTL_SCK_DCAP Used to adjust the frequency of RTC slow clock. (R/W)

RTC_CNTL_DIG_VREG_DBIAS_WAK Digital voltage regulator DBIAS during wake-up. (R/W)

RTC_CNTL_DIG_VREG_DBIAS_SLP Digital voltage regulator DBIAS during sleep. (R/W)

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Register 9.27. RTC_CNTL_PWC_REG (0x0080)

CE SO O

SO
OR _I IS
C T AS EM FO E_ U
C T AS EM O _C D

EM FO CE_ O
RT _CN L_F CE _F RCE LPU
RT _CN L_S CE OI LW_ LPD

_F RCE NO
RT CN _F TM _P RC PU

RT _CN L_F TM _F RCE PU

RT _CN L_S TM _F _EN PD

OI
RT _CN L_F TM M_ RC LP
RT _CN L_F TM _F LW LP
RT CN _S WM M_ RCE PU

PU
RT _CN L_F WM M_ RC PD

TM _ R IS

_N
C_ TL AS EM FO E_
C T AS EM D E_

C T AS E FO E_

AS EM FO E_
C_ TL LO E O _
C T LO E FO _

C T OR EM O _
C T OR _N O _
C T LO _I SO C
C T AS E FO N

RT _CN L_S WM _F RCE

RT _CN L_F TM M_ RC

_F TM M_ RC
RT _CN L_F WM M_ _E
C T LO E PD

TL AS ME FO
C T LO EM O
RT _CN L_S WM M_

CN _F W M_
RT _CN L_S WM SO
RT CN _S CE U
RT _CN L_S WM D
C_ TL OR _P
C T LO _P
C T LO E

C_ TL LO E
RT _CN L_F EN
RT _CN L_F CE
C T D_
C T OR
RT _CN L_P
)
ed

C T
RT _CN
rv
se

C
(re

RT
31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 Reset

RTC_CNTL_PD_EN Enable power down rtc_peri in sleep. (R/W)

RTC_CNTL_FORCE_PU rtc_peri force power up. (R/W)

RTC_CNTL_FORCE_PD rtc_peri force power down. (R/W)

RTC_CNTL_SLOWMEM_PD_EN Enable power down RTC memory in sleep. (R/W)

RTC_CNTL_SLOWMEM_FORCE_PU RTC memory force power up. (R/W)

RTC_CNTL_SLOWMEM_FORCE_PD RTC memory force power down. (R/W)

RTC_CNTL_FASTMEM_PD_EN Enable power down fast RTC memory in sleep. (R/W)

RTC_CNTL_FASTMEM_FORCE_PU Fast RTC memory force power up. (R/W)

RTC_CNTL_FASTMEM_FORCE_PD Fast RTC memory force power down. (R/W)

RTC_CNTL_SLOWMEM_FORCE_LPU RTC memory force power up in low-power mode. (R/W)

RTC_CNTL_SLOWMEM_FORCE_LPD RTC memory force power down in low-power mode. (R/W)

RTC_CNTL_SLOWMEM_FOLW_CPU 1: RTC memory low-power mode PD following CPU; 0: RTC

memory low-power mode PD following RTC state machine. (R/W)

RTC_CNTL_FASTMEM_FORCE_LPU Fast RTC memory force power up in low-power mode. (R/W)

RTC_CNTL_FASTMEM_FORCE_LPD Fast RTC memory force power down in low-power mode.

(R/W)

RTC_CNTL_FASTMEM_FOLW_CPU 1: Fast RTC memory low-power mode PD following CPU; 0: fast

RTC memory low-power mode PD following RTC state machine. (R/W)

RTC_CNTL_FORCE_NOISO rtc_peri force no isolation. (R/W)

RTC_CNTL_FORCE_ISO rtc_peri force isolation. (R/W)

RTC_CNTL_SLOWMEM_FORCE_ISO RTC memory force isolation. (R/W)

RTC_CNTL_SLOWMEM_FORCE_NOISO RTC memory force no isolation. (R/W)

RTC_CNTL_FASTMEM_FORCE_ISO Fast RTC memory force isolation. (R/W)

RTC_CNTL_FASTMEM_FORCE_NOISO Fast RTC memory force no isolation. (R/W)

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Register 9.28. RTC_CNTL_DIG_PWC_REG (0x0084)

C T NT R 1_ RC PU

TL SL _F CE RC PU
C T NT R 1_ C PD

SL ME CE U PD
C T NT R 2_ RC PU
C T NT R 3_ RC PU

C T NT R 2_ RC PD
C T NT R 3_ RC PD

C T O R 0_ C U
C_ TL OM _F 0_ RC D

CE U
D
RT _CN L_R ER_ AM FOR E_P
RT _CN L_R M0 AM FO E_P
RT _CN L_I ER_ AM FO E_
RT _CN L_I ER_ AM FOR E_

CN _L 0 OR FO E_
_L P_ OR _P E_
RT _CN L_I ER_ AM FO E_
RT _CN L_I ER_ AM FO E_
RT _CN L_I ER_ AM FO E_
RT _CN L_I ER_ AM FO E_

OR _P
_P
RT _CN L_I I_F CE RCE U
RT _CN L_I ER_ CE U D
0_ M D_ N

N
_R ER AM PD N
CN _I ER AM PD N

PD 0_ EN

C T IF OR O _P
C T NT OR _P _P

C T NT R 4_ RC
OM _R 1_ _E

N _E
TL NT _R 2_ _E
C_ TL NT R 3_ _E

_F RCE
M _F D
RT _CN L_I ER_ EN _EN

RT CN _W I_F P_F CE
_E PD
RT _CN L_I ER_ AM PD

RT _CN L_I ER_ AM FO

P_ M _P
RT _CN L_I ER_ AM D
A P

EM O
C_ TL IF A OR

C T NT R _P
C T NT R 4_

C T NT R 4_
C T NT D_ D
RT CN _I I_P P_P

RT _CN L_W _WR P_F

RT _CN L_I ER_ AM
C T NT R
C_ TL IF A

C T G A
RT _CN L_W _WR

RT _CN L_D _WR

C T G

C T G
RT CN _D

RT N _D
C_ TL

C_ TL
)

)
ed

ed
RT _CN

RT CN
rv

rv
C
se

se
C_
C

(re

(re
RT

RT
31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

x x x x x x x x 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 Reset

RTC_CNTL_DG_WRAP_PD_EN Enable power down digital core in sleep mode. (R/W)

RTC_CNTL_WIFI_PD_EN Enable power down Wi-Fi in sleep. (R/W)

RTC_CNTL_INTER_RAM4_PD_EN Enable power down internal SRAM 4 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM3_PD_EN Enable power down internal SRAM 3 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM2_PD_EN Enable power down internal SRAM 2 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM1_PD_EN Enable power down internal SRAM 1 in sleep mode. (R/W)

RTC_CNTL_INTER_RAM0_PD_EN Enable power down internal SRAM 0 in sleep mode. (R/W)

RTC_CNTL_ROM0_PD_EN Enable power down ROM in sleep mode. (R/W)

RTC_CNTL_DG_WRAP_FORCE_PU Digital core force power up. (R/W)

RTC_CNTL_DG_WRAP_FORCE_PD Digital core force power down. (R/W)

RTC_CNTL_WIFI_FORCE_PU Wi-Fi force power up. (R/W)

RTC_CNTL_WIFI_FORCE_PD Wi-Fi force power down. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_PU Internal SRAM 4 force power up. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_PD Internal SRAM 4 force power down. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_PU Internal SRAM 3 force power up. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_PD Internal SRAM 3 force power down. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_PU Internal SRAM 2 force power up. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_PD Internal SRAM 2 force power down. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_PU Internal SRAM 1 force power up. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_PD Internal SRAM 1 force power down. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_PU Internal SRAM 0 force power up. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_PD Internal SRAM 0 force power down. (R/W)

RTC_CNTL_ROM0_FORCE_PU ROM force power up. (R/W)

Continued on the next page...

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Register 9.28. RTC_CNTL_DIG_PWC_REG (0x0084)

Continued from the previous page...

RTC_CNTL_ROM0_FORCE_PD ROM force power down. (R/W)

RTC_CNTL_LSLP_MEM_FORCE_PU Memories in digital core force power up in sleep mode. (R/W)

RTC_CNTL_LSLP_MEM_FORCE_PD Memories in digital core force power down in sleep mode.

(R/W)

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Register 9.29. RTC_CNTL_DIG_ISO_REG (0x0088)

D
OH N
OL
UT _E
_ A LD
AD O
_P OH
LD DG UT
RT _CN L_I ER_ AM FOR E_ ISO

RT _CN L_D _PA OR _N E_ ISO

RT _CN L_I ER_ AM FO E_ ISO
RT _CN L_I ER_ AM FO E_ ISO

RT _CN L_R M0 AM FO E_I ISO

HO L _ _ A
TL LR TC RC IS LD
C T NT R 1_ C ISO

C T G D_ CE OI ISO
C T NT R 2_ RC ISO
C T NT R 3_ RC ISO

C T NT R 1_ RC NO

C T G _F CE RC NO
C T NT R 2_ RC NO
C T NT R 3_ RC NO
C_ TL NT OR _N _I SO

C T O _F 0_ RC SO

TO NT AD
C T O R 0_ C O

D_ TC DG O
RT _CN L_R ER_ AM FOR E_N

CN _C _R FO E_ HO
RT _CN L_R _PA FO E_ LD

AU _C _P
RT _CN L_I I_F CE RCE OI

RT _CN L_I ER_ AM FO E_

RT _CN L_D M0 OR FO E_
RT _CN L_I ER_ AM FO E_
RT _CN L_I ER_ AM FO E_

PA _R L_ IS
RT CN _I ER_ CE OI SO

RT _CN L_D _PA FO _IS SO

_D _R _C E_ O
G_ EG NT NO
C T G D_ RC HO
C T IF OR O _N

C_ TL EG D_ RC UN
C T NT R 4_ RC
C T NT R _I SO

C T G D_ RC O
RT _CN L_W I_F P_F RCE

RT _CN L_D _PA FO E_

RT _CN L_I ER_ AM FO
RT _CN L_I ER_ AM SO
C T NT R 4_
C T IF A O
RT CN _W WR P_F
C_ TL G_ A
RT _CN L_D _WR
C T G
RT _CN L_D

)
ed
C T
RT _CN

rv
se
C

(re
RT

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_DG_WRAP_FORCE_NOISO Digital core force no isolation. (R/W)

RTC_CNTL_DG_WRAP_FORCE_ISO Digital core force isolation. (R/W)

RTC_CNTL_WIFI_FORCE_NOISO Wi-Fi force no isolation. (R/W)

RTC_CNTL_WIFI_FORCE_ISO Wi-Fi force isolation. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_NOISO Internal SRAM 4 force no isolation. (R/W)

RTC_CNTL_INTER_RAM4_FORCE_ISO Internal SRAM 4 force isolation. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_NOISO Internal SRAM 3 force no isolation. (R/W)

RTC_CNTL_INTER_RAM3_FORCE_ISO Internal SRAM 3 force isolation. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_NOISO Internal SRAM 2 force no isolation. (R/W)

RTC_CNTL_INTER_RAM2_FORCE_ISO Internal SRAM 2 force isolation. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_NOISO Internal SRAM 1 force no isolation. (R/W)

RTC_CNTL_INTER_RAM1_FORCE_ISO Internal SRAM 1 force isolation. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_NOISO Internal SRAM 0 force no isolation. (R/W)

RTC_CNTL_INTER_RAM0_FORCE_ISO Internal SRAM 0 force isolation. (R/W)

RTC_CNTL_ROM0_FORCE_NOISO ROM force no isolation. (R/W)

RTC_CNTL_ROM0_FORCE_ISO ROM force isolation. (R/W)

RTC_CNTL_DG_PAD_FORCE_HOLD Digital pad force hold. (R/W)

RTC_CNTL_DG_PAD_FORCE_UNHOLD Digital pad force un-hold. (R/W)

RTC_CNTL_DG_PAD_FORCE_ISO Digital pad force isolation. (R/W)

RTC_CNTL_DG_PAD_FORCE_NOISO Digital pad force no isolation. (R/W)

Continued on the next page...

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Register 9.29. RTC_CNTL_DIG_ISO_REG (0x0088)

Continued from the previous page...

RTC_CNTL_REG_RTC_CNTL_DG_PAD_AUTOHOLD_EN Digital pad enable auto-hold. (R/W)

RTC_CNTL_CLR_REG_RTC_CNTL_DG_PAD_AUTOHOLD Write-only register clears digital pad auto-

hold. (WO)

RTC_CNTL_DG_PAD_AUTOHOLD Read-only register indicates digital pad auto-hold status. (RO)

Register 9.30. RTC_CNTL_WDTCONFIG0_REG (0x008C)

SE _R ET_ EN
H

TH

_I ES EN

P N
GT

AU U ES D_

SL _E
NG
EN

_P CP R O

N_ ET
DT PP U_ M
LE
_L

_
T_

_W _A CP OT
ET

SE
ES

TL DT RO BO
RE
_R

CN _W T_P SH
0

_
1

PU
TG

TG

TG

TG

YS

C_ TL D LA
N

_C
_S

_S

_S

_S

_S
_E

RT CN _W _F
DT

DT

DT

DT

DT

DT

DT

T
C_ TL D
W

_W

_W

_W

_W

_W

_W

RT CN _W
L_

TL

TL

TL

TL

TL

TL

C_ TL
NT

se d
ed

ed
CN

CN

CN

CN

CN

CN

RT _CN
re rve
C

rv

rv
C_

C_

C_

C_

C_

C_

C_
se

se
C
RT

RT

RT

RT

RT

RT

RT

RT
re

re
31 30 28 27 25 24 22 21 19 18 17 16 14 13 11 10 9 8 7 6 0

0 0 0 0 0 0 0 1 1 1 0 0 1 0 Reset

RTC_CNTL_WDT_PAUSE_IN_SLP Pause RTC WDT in sleep. (R/W)

RTC_CNTL_WDT_APPCPU_RESET_EN RTC WDT reset APP_CPU enable. (R/W)

RTC_CNTL_WDT_PROCPU_RESET_EN RTC WDT reset PRO_CPU enable. (R/W)

RTC_CNTL_WDT_FLASHBOOT_MOD_EN Enable RTC WDT in flash boot. (R/W)

RTC_CNTL_WDT_SYS_RESET_LENGTH System reset counter length, unit: RTC_SLOW_CLK cycle.

The value can be 0 ~ 7. (R/W)

RTC_CNTL_WDT_CPU_RESET_LENGTH CPU reset counter length, unit: RTC_SLOW_CLK cycle.

The value can be 0 ~ 7. (R/W)

RTC_CNTL_WDT_STG3 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG2 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG1 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_STG0 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)

RTC_CNTL_WDT_EN Enable RTC WDT. (R/W)

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Register 9.31. RTC_CNTL_WDTCONFIGn_REG (n: 1-4) (0x008C+4*n)

31 0

0x000000FFF Reset

RTC_CNTL_WDTCONFIGn_REG Hold cycles for WDT stage n. (R/W)

Register 9.32. RTC_CNTL_WDTFEED_REG (0x00A0)

D
EE
_F
DT
W
L_

)
ed
NT

rv
C

se
C_

(re
RT

31 30 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_WDT_FEED SW feeds WDT. (WO)

Register 9.33. RTC_CNTL_WDTWPROTECT_REG (0x00A4)

31 0

0x050D83AA1 Reset

RTC_CNTL_WDTWPROTECT_REG If the register contains a different value than 0x50d83aa1, write

protection for the RTC watchdog (RWDT) is enabled. (R/W)

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Register 9.34. RTC_CNTL_SW_CPU_STALL_REG (0x00AC)

C1

1
_C
U_

PU
CP

PC
O
PR

AP
L_

L_
L

L
TA

TA
_S

_S
SW

SW
L_

L_

d)
NT

NT

ve
C

r
se
C_

C_

(re
RT

31 26 25
RT 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_SW_STALL_PROCPU_C1 reg_rtc_cntl_sw_stall_procpu_c1[5:0],
reg_rtc_cntl_sw_stall_procpu_c0[1:0] == 0x86 (100001 10) will stall PRO_CPU, see also
RTC_CNTL_OPTIONS0_REG. (R/W)

RTC_CNTL_SW_STALL_APPCPU_C1 reg_rtc_cntl_sw_stall_appcpu_c1[5:0],
reg_rtc_cntl_sw_stall_appcpu_c0[1:0] == 0x86 (100001 10) will stall APP_CPU, see also
RTC_CNTL_OPTIONS0_REG. (R/W)

Register 9.35. RTC_CNTL_STOREn_REG (n: 4-7) (0x00B0+4*(n-4))

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W)

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Register 9.36. RTC_CNTL_HOLD_FORCE_REG (0x00C8)

RT CN _T CH AD HO _F CE

RT _CN L_S SE HO HO _F CE

RT _CN L_P SE HO _F CE CE
RT _CN L_T CH AD HO _F CE

RT _CN L_S SE AD HO _F CE
RT _CN L_S CH AD HO _F CE

RT _CN L_S SE HO _F _F CE
RT _CN L_T CH AD HO _F CE
C_ TL OU _P 4_ LD OR

C T EN 4_ 0_ LD OR

C T EN 2_ LD OR OR
C T OU _P 3_ LD OR

C T EN _P 1_ LD OR
C T OU _P 2_ LD OR

C T EN 3_ LD LD OR
C T OU _P 5_ LD R
RT _CN L_T CH AD HO _FO

CN _A C1 O _F CE
RT _CN L_P C2 HO _F CE

_A 2_ OL FO CE
1_ OLD FO E
LD FO E
OR E
DC H D_ RC
C T OU _P _F CE

C_ TL DA _H LD OR
C T DA 1_ LD OR

CE
H O _ RC
C T OU _P 7_ CE
C T OU _P 6_ LD

TL DC _H LD_ OR

_F RC
RT CN _T CH LD OR
RT _CN L_T CH AD OR
RT _CN L_T CH AD HO
C_ TL OU HO _F
RT _CN L_T P_ LD
C T 32 HO
RT _CN L_X N_
C T 32
RT CN _X
C_ TL
d)
ve

RT _CN
r
se

C
(re

RT
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_X32N_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_X32P_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD7_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD6_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD5_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD4_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD3_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_TOUCH_PAD0_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE4_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE3_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_SENSE1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_PDAC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_PDAC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_ADC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

RTC_CNTL_ADC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W)

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Register 9.37. RTC_CNTL_EXT_WAKEUP1_REG (0x00CC)

LR
C
S_
TU

L
TA

E
_S

_S
P1

P1
EU

EU
AK

AK
W

W
T_

T_
EX

EX
L_

L_
d)

T
ve

CN

CN
r
se

C_

C_
(re

RT

RT
31 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_EXT_WAKEUP1_STATUS_CLR Clear external wakeup1 status. (WO)

RTC_CNTL_EXT_WAKEUP1_SEL Bitmap to select RTC pads for external wakeup1. (R/W)

Register 9.38. RTC_CNTL_EXT_WAKEUP1_STATUS_REG (0x00D0)

S
TU
TA
_S
P1
EU
AK
W
T_
EX
L_
)
ed

NT
rv

C
se

C_
(re

RT

31 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_EXT_WAKEUP1_STATUS EXT1 wakeup source status. (RO)

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Register 9.39. RTC_CNTL_BROWN_OUT_REG (0x00D4)

A
EN
H_
AS
E_ A
OS EN
FL
T
A

AI
S

CL F_
EN

W
RE

T_ _R
T_

T_
A
T_ T

TH

OU PD
EN
OU DE

RS

RS
T_
N_ T_

T_

T_

N_ T_
OU
W OU

OU

OU

W OU
N_
RO N_

N_

N_

RO N_
OW
_B W

_B W
TL RO

RO

RO

TL RO
BR
_D
CN _B

_B

_B

CN _B
C_ TL

TL

TL

TL

C_ TL

)
ed
RT _CN

CN

CN

CN

RT CN

rv
se
C_

C_

C_

C_
C

(re
RT

RT

RT

RT

RT
31 30 29 27 26 25 16 15 14 13 0

0 0 0x2 0 0x3FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTC_CNTL_BROWN_OUT_DET Brownout detect. (RO)

RTC_CNTL_BROWN_OUT_ENA Enables brownout. (R/W)

RTC_CNTL_DBROWN_OUT_THRES Brownout threshold. The brownout detector will reset the chip
when the supply voltage is approximately below this level. Note that there may be some variation
of brownout voltage level between each ESP32 chip. 0: 2.43 V ± 0.05; 1: 2.48 V ± 0.05; 2: 2.58
V ± 0.05; 3: 2.62 V ± 0.05; 4: 2.67 V ± 0.05; 5: 2.70 V ± 0.05; 6: 2.77 V ± 0.05; 7: 2.80 V ±
0.05. (R/W)

RTC_CNTL_BROWN_OUT_RST_ENA Enables brownout reset. (R/W)

RTC_CNTL_BROWN_OUT_RST_WAIT Brownout reset wait cycles. (R/W)

RTC_CNTL_BROWN_OUT_PD_RF_ENA Enables power down RF when brownout happens. (R/W)

RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA Sends suspend command to flash when brownout

happens. (R/W)

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Chapter 10

Timer Group (TIMG)

10.1 Introduction
There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on
16-bit prescalers and 64-bit auto-reload-capable up/downcounters.

The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated
by an x in TIMGn_Tx; the blocks themselves are indicated by an n.

The timers feature:

• A 16-bit clock prescaler, from 2 to 65536

• A 64-bit time-base counter

• Configurable up/down time-base counter: incrementing or decrementing

• Halt and resume of time-base counter

• Auto-reload at alarm

• Software-controlled instant reload

• Level and edge interrupt generation

10.2 Functional Description

10.2.1 16-bit Prescaler

Each timer uses the APB clock (APB_CLK, normally 80 MHz) as the basic clock. This clock is then divided
down by a 16-bit precaler which generates the time-base counter clock (TB_clk). Every cycle of TB_clk
causes the time-base counter to increment or decrement by one. The timer must be disabled (TIMGn_Tx_EN
is cleared) before changing the prescaler divisor which is configured by TIMGn_Tx_DIVIDER register; changing
it on an enabled timer can lead to unpredictable results. The prescaler can divide the APB clock by a factor
from 2 to 65536. Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2; when
TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will cause the clock to be divided by
exactly that value.

10.2.2 64-bit Time-base Counter

The 64-bit time-base counter can be configured to count either up or down, depending on whether
TIMGn_Tx_INCREASE is set or cleared, respectively. It supports both auto-reload and software instant reload.
An alarm event can be set when the counter reaches a value specified by the software.

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Counting can be enabled and disabled by setting and clearing TIMGn_Tx_EN. Clearing this bit essentially
freezes the counter, causing it to neither count up nor count down; instead, it retains its value until
TIMGn_Tx_EN is set again. Reloading the counter when TIMGn_Tx_EN is cleared will change its value, but
counting will not be resumed until TIMGn_Tx_EN is set.

Software can set a new counter value by setting registers TIMGn_Tx_LOAD_LO and TIMGn_Tx_LOAD_HI to the
intended new value. The hardware will ignore these register settings until a reload; a reload will cause the
contents of these registers to be copied to the counter itself. A reload event can be triggered by an alarm
(auto-reload at alarm) or by software (software instant reload). To enable auto-reload at alarm, the register
TIMGn_Tx_AUTORELOAD should be set. If auto-reload at alarm is not enabled, the time-base counter will
continue incrementing or decrementing after the alarm. To trigger a software instant reload, any value can be
written to the register TIMGn_Tx_LOAD_REG; this will cause the counter value to change instantly. Software
can also change the direction of the time-base counter instantly by changing the value of
TIMGn_Tx_INCREASE.

The time-base counter can also be read by software, but because the counter is 64-bit, the CPU can only get
the value as two 32-bit values, the counter value needs to be latched onto TIMGn_TxLO_REG and
TIMGn_TxHI_REG first. This is done by writing any value to TIMGn_TxUPDATE_REG; this will instantly latch the
64-bit timer value onto the two registers. Software can then read them at any point in time. This approach
stops the timer value being read erroneously when a carry-over happens between reading the low and high
word of the timer value.

10.2.3 Alarm Generation

The timer can trigger an alarm, which can cause a reload and/or an interrupt to occur. The alarm is triggered
when the alarm registers TIMGn_Tx_ALARMLO_REG and TIMGn_Tx_ALARMHI_REG match the current timer
value. In order to simplify the scenario where these registers are set ’too late’ and the counter has already
passed these values, the alarm also triggers when the current timer value is higher (for an up-counting timer)
or lower (for a down-counting timer) than the current alarm value: if this is the case, the alarm will be triggered
immediately upon loading the alarm registers. The timer alarm enable bit is automatically cleared once an
alarm occurs.

10.2.4 MWDT
Each timer module also contains a Main System Watchdog Timer and its associated registers. While these
registers are described here, their functional description can be found in the chapter entitled Watchdog
Timer.

10.2.5 Interrupts
• TIMGn_INT_WDT_INT: Generated when a watchdog timer interrupt stage times out.

• TIMGn_INT_T1_INT: An alarm event on timer 1 generates this interrupt.

• TIMGn_INT_T0_INT: An alarm event on timer 0 generates this interrupt.

10.3 Register Summary

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Name Description TIMG0 TIMG1 Acc

Timer 0 configuration and control registers
TIMGn_T0CONFIG_REG Timer 0 configuration register 0x3FF5F000 0x3FF60000 R/W
TIMGn_T0LO_REG Timer 0 current value, low 32 bits 0x3FF5F004 0x3FF60004 RO
TIMGn_T0HI_REG Timer 0 current value, high 32 bits 0x3FF5F008 0x3FF60008 RO
Write to copy current timer value to
TIMGn_T0UPDATE_REG 0x3FF5F00C 0x3FF6000C WO
TIMGn_T0_(LO/HI)_REG
TIMGn_T0ALARMLO_REG Timer 0 alarm value, low 32 bits 0x3FF5F010 0x3FF60010 R/W
TIMGn_T0ALARMHI_REG Timer 0 alarm value, high bits 0x3FF5F014 0x3FF60014 R/W
TIMGn_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x3FF5F018 0x3FF60018 R/W
TIMGn_T0LOADHI_REG Timer 0 reload value, high 32 bits 0x3FF5F01C 0x3FF6001C R/W
Write to reload timer from
TIMGn_T0LOAD_REG 0x3FF5F020 0x3FF60020 WO
TIMGn_T0_(LOADLOLOADHI)_REG
Timer 1 configuration and control registers
TIMGn_T1CONFIG_REG Timer 1 configuration register 0x3FF5F024 0x3FF60024 R/W
TIMGn_T1LO_REG Timer 1 current value, low 32 bits 0x3FF5F028 0x3FF60028 RO
TIMGn_T1HI_REG Timer 1 current value, high 32 bits 0x3FF5F02C 0x3FF6002C RO
Write to copy current timer value to
TIMGn_T1UPDATE_REG 0x3FF5F030 0x3FF60030 WO
TIMGn_T1_(LO/HI)_REG
TIMGn_T1ALARMLO_REG Timer 1 alarm value, low 32 bits 0x3FF5F034 0x3FF60034 R/W
TIMGn_T1ALARMHI_REG Timer 1 alarm value, high 32 bits 0x3FF5F038 0x3FF60038 R/W
TIMGn_T1LOADLO_REG Timer 1 reload value, low 32 bits 0x3FF5F03C 0x3FF6003C R/W
TIMGn_T1LOADHI_REG Timer 1 reload value, high 32 bits 0x3FF5F040 0x3FF60040 R/W
Write to reload timer from
TIMGn_T1LOAD_REG 0x3FF5F044 0x3FF60044 WO
TIMGn_T1_(LOADLOLOADHI)_REG
System watchdog timer configuration and control registers
TIMGn_WDTCONFIG0_REG Watchdog timer configuration regis- 0x3FF5F048 0x3FF60048 R/W
ter
TIMGn_WDTCONFIG1_REG Watchdog timer prescaler register 0x3FF5F04C 0x3FF6004C R/W
TIMGn_WDTCONFIG2_REG Watchdog timer stage 0 timeout 0x3FF5F050 0x3FF60050 R/W
value
TIMGn_WDTCONFIG3_REG Watchdog timer stage 1 timeout 0x3FF5F054 0x3FF60054 R/W
value
TIMGn_WDTCONFIG4_REG Watchdog timer stage 2 timeout 0x3FF5F058 0x3FF60058 R/W
value
TIMGn_WDTCONFIG5_REG Watchdog timer stage 3 timeout 0x3FF5F05C 0x3FF6005C R/W
value
TIMGn_WDTFEED_REG Write to feed the watchdog timer 0x3FF5F060 0x3FF60060 WO
TIMGn_WDTWPROTECT_REG Watchdog write protect register 0x3FF5F064 0x3FF60064 R/W
Configuration and Control Register for RTC CALI
TIMGn_RTCCALICFG_REG RTC calibration configuration register 0x3FF5F068 0x3FF60068 varies
TIMGn_RTCCALICFG1_REG RTC calibration configuration register 0x3FF5F06C 0x3FF6006C RO
1
Interrupt registers
TIMGn_INT_ENA_REG Interrupt enable bits 0x3FF5F098 0x3FF60098 R/W

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Name Description TIMG0 TIMG1 Acc

TIMGn_INT_RAW_REG Raw interrupt status 0x3FF5F09C 0x3FF6009C RO
TIMGn_INT_ST_REG Masked interrupt status 0x3FF5F0A0 0x3FF600A0 RO
TIMGn_INT_CLR_REG Interrupt clear bits 0x3FF5F0A4 0x3FF600A4 WO

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10.4 Registers
The addresses in parenthesis besides register names are the register addresses relative to the TIMG base
address provided in Table 3.3-6 Peripheral Address Mapping in Chapter 3 System and Memory. The absolute
register addresses are listed in Section 10.3 Register Summary.

Register 10.1. TIMGn_TxCONFIG_REG (x: 0-1) (0x0+0x24*x)

_E N
AL L_ EN
AD

M T_E
N
x_ VE T_
LO
TO SE

AR IN
_T LE _IN
RE

ER
AU EA

Gn _ E
ID
x_ R

M Tx G
_T INC

IV
TI _ EN

TI n_ _ED
D
Gn _
Gn _

x_
M Tx
M Tx

M Tx
_T
TI n_

TI n_
Gn
G

G
G
M

M
TI

TI

TI
31 30 29 28 13 12 11 10

0 1 1 0x00001 0 0 0 Reset

TIMGn_Tx_EN When set, the timer x time-base counter is enabled. (R/W)

TIMGn_Tx_INCREASE When set, the timer x time-base counter will increment every clock tick.
When cleared, the timer x time-base counter will decrement. (R/W)

TIMGn_Tx_AUTORELOAD When set, timer x auto-reload at alarm is enabled. (R/W)

TIMGn_Tx_DIVIDER Timer x clock (Tx_clk) prescale value. (R/W)

TIMGn_Tx_EDGE_INT_EN When set, an alarm will generate an edge type interrupt. (R/W)

TIMGn_Tx_LEVEL_INT_EN When set, an alarm will generate a level type interrupt. (R/W)

TIMGn_Tx_ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an
alarm occurs. (R/W)

Register 10.2. TIMGn_TxLO_REG (x: 0-1) (0x4+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxLO_REG After writing to TIMGn_TxUPDATE_REG, the low 32 bits of the time-base counter
of timer x can be read here. (RO)

Register 10.3. TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter
of timer x can be read here. (RO)

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Register 10.4. TIMGn_TxUPDATE_REG (x: 0-1) (0xC+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxUPDATE_REG Write any value to trigger a timer x time-base counter value update (timer
x current value will be stored in registers above). (WO)

Register 10.5. TIMGn_TxALARMLO_REG (x: 0-1) (0x10+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxALARMLO_REG Timer x alarm trigger time-base counter value, low 32 bits. (R/W)

Register 10.6. TIMGn_TxALARMHI_REG (x: 0-1) (0x14+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxALARMHI_REG Timer x alarm trigger time-base counter value, high 32 bits. (R/W)

Register 10.7. TIMGn_TxLOADLO_REG (x: 0-1) (0x18+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxLOADLO_REG Low 32 bits of the value that a reload will load onto timer x time-base
counter. (R/W)

Register 10.8. TIMGn_TxLOADHI_REG (x: 0-1) (0x1C+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxLOADHI_REG High 32 bits of the value that a reload will load onto timer x time-base
counter. (R/W)

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Register 10.9. TIMGn_TxLOAD_REG (x: 0-1) (0x20+0x24*x)

31 0

0x000000000 Reset

TIMGn_TxLOAD_REG Write any value to trigger a timer x time-base counter reload. (WO)

Register 10.10. TIMGn_WDTCONFIG0_REG (0x0048)

N
TH

_E
GT
NG

OD
EN
LE

_M
N
_I EN

_L
_E

T_

OT
ET
EL T_
NT

SE

BO
ES
EV IN

RE
_L E_

SH
_R
_
0

G2

3
1

PU
DT DG
TG

TG

TG

YS

LA
N

ST

_C
_S

_S

_S

_S
Gn T_E

_W T_E

_F
_
DT

DT

DT

DT

DT

DT

DT
D

Gn D
_W

_W

_W

_W

_W

M W

_W

_W

_W
TI n_
Gn

Gn

Gn

Gn

Gn

Gn

Gn
G
M

M
TI

TI

TI

TI

TI

TI

TI

TI

TI
31 30 29 28 27 26 25 24 23 22 21 20 18 17 15 14

0 0 0 0 0 0 0 0x1 0x1 1 Reset

TIMGn_WDT_EN When set, MWDT is enabled. (R/W)

TIMGn_WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)

TIMGn_WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)

TIMGn_WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)

TIMGn_WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)

TIMGn_WDT_EDGE_INT_EN When set, an edge type interrupt will occur at the timeout of a stage
configured to generate an interrupt. (R/W)

TIMGn_WDT_LEVEL_INT_EN When set, a level type interrupt will occur at the timeout of a stage
configured to generate an interrupt. (R/W)

TIMGn_WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300
ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)

TIMGn_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2:
300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)

TIMGn_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W)

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Register 10.11. TIMGn_WDTCONFIG1_REG (0x004c)

E
AL
SC
RE
_P
LK
_C
DT
_W
Gn
M
TI
31 16

0x00001 Reset

TIMGn_WDT_CLK_PRESCALE MWDT clock prescale value. MWDT clock period = MWDT’s clock
source period * TIMGn_WDT_CLK_PRESCALE. (R/W)

Register 10.12. TIMGn_WDTCONFIG2_REG (0x0050)

31 0

26000000 Reset

TIMGn_WDTCONFIG2_REG Stage 0 timeout value, in MWDT clock cycles. (R/W)

Register 10.13. TIMGn_WDTCONFIG3_REG (0x0054)

31 0

0x007FFFFFF Reset

TIMGn_WDTCONFIG3_REG Stage 1 timeout value, in MWDT clock cycles. (R/W)

Register 10.14. TIMGn_WDTCONFIG4_REG (0x0058)

31 0

0x0000FFFFF Reset

TIMGn_WDTCONFIG4_REG Stage 2 timeout value, in MWDT clock cycles. (R/W)

Register 10.15. TIMGn_WDTCONFIG5_REG (0x005c)

31 0

0x0000FFFFF Reset

TIMGn_WDTCONFIG5_REG Stage 3 timeout value, in MWDT clock cycles. (R/W)

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Register 10.16. TIMGn_WDTFEED_REG (0x0060)

31 0

0x000000000 Reset

TIMGn_WDTFEED_REG Write any value to feed the MWDT. (WO)

Register 10.17. TIMGn_WDTWPROTECT_REG (0x0064)

31 0

0x050D83AA1 Reset

TIMGn_WDTWPROTECT_REG If the register contains a different value than its reset value, write pro-
tection is enabled. (R/W)

Register 10.18. TIMGn_RTCCALICFG_REG (0x0068)

G
IN
CL
CY
EL

T_
_S
T
AR

AR
AX

CA DY

_C CLK
ST

ST
M

R
I_

I_

I_

I_
LI
AL

AL

AL

AL
_C

_C

Gn C_C

_
TC

TC

TC

TC

)
T

ed
_R

_R

_R

_R

_R

rv
Gn

Gn

Gn

Gn

se
M

(re
TI

TI

TI

TI

TI

31 30 16 15 14 13 12 11 0

0 0x01 0 0x1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TIMGn_RTC_CALI_START_CYCLING Reserved. (R/W)

TIMGn_RTC_CALI_CLK_SEL Used to select the clock to be calibrated. 0: RC_SLOW_CLK. 1:

RC_FAST_DIV_CLK. 2: XTAL32K_CLK. (R/W)

TIMGn_RTC_CALI_RDY Set this bit to mark the completion of calibration. (RO)

TIMGn_RTC_CALI_MAX Calibration time, in cycles of the clock to be calibrated. (R/W)

TIMGn_RTC_CALI_START Set this bit to starts calibration. (R/W)

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Register 10.19. TIMGn_RTCCALICFG1_REG (0x006C)

E
LU
VA
L I_
CA
C_

)
RT

ed
_

rv
Gn

se
M

(re
TI
31 7 5 0

0x00000 0 0 0 0 0 0 Reset

TIMGn_RTC_CALI_VALUE Calibration value when cycles of clock to be calibrated reach

TIMGn_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles. (RO)

Register 10.20. TIMGn_INT_ENA_REG (0x0098)

0_ _E A
_T NT EN

A
IN NA
EN
NT _I T_

T_
_I _T1 IN
Gn T T_
M IN D
TI _ _W
Gn T
)

M _IN
ed
rv

Gn
se

M
(re

TI
TI
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TIMGn_INT_WDT_INT_ENA The interrupt enable bit for the TIMGn_INT_WDT_INT interrupt. (R/W)
(R/W)

TIMGn_INT_T1_INT_ENA The interrupt enable bit for the TIMGn_INT_T1_INT interrupt. (R/W) (R/W)

TIMGn_INT_T0_INT_ENA The interrupt enable bit for the TIMGn_INT_T0_INT interrupt. (R/W) (R/W)

Register 10.21. TIMGn_INT_RAW_REG (0x009c) 0_ _R W

W
_T NT RA
IN AW
RA
NT _I T_

T_
_I _T1 IN
Gn T T_
M IN D
TI _ _W
Gn T
)

M IN
ed

TI n_
rv
se

G
M
(re

TI

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TIMGn_INT_WDT_INT_RAW The raw interrupt status bit for the TIMGn_INT_WDT_INT interrupt. (RO)

TIMGn_INT_T1_INT_RAW The raw interrupt status bit for the TIMGn_INT_T1_INT interrupt. (RO)

TIMGn_INT_T0_INT_RAW The raw interrupt status bit for the TIMGn_INT_T0_INT interrupt. (RO)

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Register 10.22. TIMGn_INT_ST_REG (0x00a0)

_T NT ST

ST
IN T
NT _I T_
0_ _S
T_
_I _T1 IN
Gn T T_
M IN D
TI _ _W
Gn T
d)

M IN
ve

TI n_
r
se

G
M
(re

TI
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TIMGn_INT_WDT_INT_ST The masked interrupt status bit for the TIMGn_INT_WDT_INT interrupt.
(RO)

TIMGn_INT_T1_INT_ST The masked interrupt status bit for the TIMGn_INT_T1_INT interrupt. (RO)

TIMGn_INT_T0_INT_ST The masked interrupt status bit for the TIMGn_INT_T0_INT interrupt. (RO)

Register 10.23. TIMGn_INT_CLR_REG (0x00a4)

0_ _C R
_T NT CL

R
IN LR
CL
NT _I T_

T_
_I _T1 IN
Gn T T_
M IN D
TI n_ T_W
)

M IN
ed

TI n_
rv
se

G
G
M
(re

TI
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TIMGn_INT_WDT_INT_CLR Set this bit to clear the TIMGn_INT_WDT_INT interrupt. (WO)

TIMGn_INT_T1_INT_CLR Set this bit to clear the TIMGn_INT_T1_INT interrupt. (WO)

TIMGn_INT_T0_INT_CLR Set this bit to clear the TIMGn_INT_T0_INT interrupt. (WO)

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Chapter 11

Watchdog Timers (WDT)

11.1 Introduction
The ESP32 has three watchdog timers: one in each of the two timer modules (called Main System Watchdog
Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These
watchdog timers are intended to recover from an unforeseen fault, causing the application program to
abandon its normal sequence. A watchdog timer has four stages. Each stage may take one out of three or
four actions upon the expiry of a programmed period of time for this stage, unless the watchdog is fed or
disabled. The actions are: interrupt, CPU reset, core reset and system reset. Only the RWDT can trigger the
system reset, and is able to reset the entire chip and the main system including the RTC itself. A timeout value
can be set for each stage individually.

During flash boot, the RWDT and the first MWDT start automatically in order to detect and recover from booting
problems.

11.2 Features
• Four stages, each of which can be configured or disabled separately

• Programmable time period for each stage

• One out of three or four possible actions (interrupt, CPU reset, core reset and system reset) upon the
expiry of each stage

• 32-bit expiry counter

• Write protection, to prevent the RWDT and MWDT configuration from being inadvertently altered.

• Flash boot protection

If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.

11.3 Functional Description

11.3.1 Clock
The RWDT is clocked from the RTC slow clock RTC_SLOW_CLK. The MWDT clock source is derived from the
APB clock APB_CLK via a pre-MWDT 16-bit configurable prescaler. For either watchdog, the clock source is
fed into the 32-bit expiry counter. When this counter reaches the timeout value of the current stage, the
action configured for the stage will execute, the expiry counter will be reset and the next stage will become
active.

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11.3.2 Operating Procedure

When a watchdog timer is enabled, it will proceed in loops from stage 0 to stage 3, then back to stage 0 and
start again. The expiry action and time period for each stage can be configured individually.

Every stage can be configured for one of the following actions when the expiry timer reaches the stage’s
timeout value:

• Trigger an interrupt
When the stage expires an interrupt is triggered.

• Reset a CPU core

When the stage expires the designated CPU core will be reset. MWDT0 CPU reset only resets the PRO
CPU. MWDT1 CPU reset only resets the APP CPU. The RWDT CPU reset can reset either of them, or both,
or none, depending on configuration.

• Reset the main system

When the stage expires, the main system, including the MWDTs, will be reset. In this article, the main
system includes the CPU and all peripherals. The RTC is an exception to this, and it will not be reset.

• Reset the main system and RTC

When the stage expires the main system and the RTC will both be reset. This action is only available in
the RWDT.

• Disabled
This stage will have no effects on the system.

When software feeds the watchdog timer, it returns to stage 0 and its expiry counter restarts from 0.

11.3.3 Write Protection

Both the MWDTs, as well as the RWDT, can be protected from accidental writing. To accomplish this, they
have a write-key register (TIMGn_WDTWPROTECT_REG for the MWDT, RTC_CNTL_WDTWPROTECT_REG for the
RWDT.) On reset, these registers are initialized to the value 0x50D83AA1. When the value in this register is
changed from 0x50D83AA1, write protection is enabled. Writes to any WDT register, including the feeding
register (but excluding the write-key register itself), are ignored. The recommended procedure for accessing a
WDT is:

1. Disable the write protection

2. Make the required modification or feed the watchdog

3. Re-enable the write protection

11.3.4 Flash Boot Protection

During flash booting, the MWDT in timer group 0 (TIMG0), as well as the RWDT, are automatically enabled.
Stage 0 for the enabled MWDT is automatically configured to reset the system upon expiry; stage 0 for the
RWDT resets the RTC when it expires. After booting, the register TIMERS_WDT_FLASHBOOT_MOD_EN should
be cleared to stop the flash boot protection procedure for the MWDT, and
RTC_CNTL_WDT_FLASHBOOT_MOD_EN should be cleared to do the same for the RWDT. After this, the MWDT
and RWDT can be configured by software.

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11.4 Registers
The MWDT registers are part of the timer submodule and are described in the Timer Registers section. The
RWDT registers are part of the RTC submodule and are described in the RTC Registers section.

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Chapter 12

DPort Registers

12.1 Introduction
The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to
achieve optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control
clock management (clock gating), power management, and the configuration of peripherals and core-system
modules. The system arranges each module with configuration registers contained in the DPort
Register.

12.2 Features
DPort registers correspond to different peripheral blocks and core modules:

• System and memory

• Reset and clock

• Interrupt matrix

• DMA

• MPU/MMU

• APP_CPU controller

• Peripheral clock gating and reset

12.3 Functional Description

12.3.1 System and Memory Register

System and memory registers are used for system and memory configuration, such as cache configuration
and memory remapping. They are listed in Section 12.4, categorized as ”System and memory registers”. For a
detailed description of these registers, please refer to Chapter System and Memory.

12.3.2 Reset and Clock Registers

Reset and clock registers are listed in Section 12.4, categorized as ”Reset and clock registers”. For a detailed
description of these registers, please refer to Chapter Reset and Clock.

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12.3.3 Interrupt Matrix Register

The interrupt matrix registers are used for configuring and mapping interrupts through the interrupt matrix.
They are listed in Section 12.4, categorized as ”Interrupt matrix registers”. For a detailed description of these
registers, please refer to Chapter Interrupt Matrix (INTERRUPT).

12.3.4 DMA Registers

DMA registers are used for the SPI DMA configuration. They are listed in Section 12.4, categorized as ”DMA
registers”. For a detailed description of these registers, please refer to Chapter DMA Controller (DMA).

12.3.5 MPU/MMU Registers

MPU/MMU registers are used for MPU/MMU configuration and operation control. They are listed in Section
12.4, categorized as ”MPU/MMU registers”. For a detailed description of these registers, please refer to
Chapter Memory Management and Protection Units (MMU, MPU).

12.3.6 APP_CPU Controller Registers

APP_CPU controller registers are used for some basic configuration of the APP_CPU, such as performing a
stalling execution, and for configuring the ROM boot jump address. The registers are listed in Section 12.4,
categorized as ”APP_CPU controller registers”. A detailed description of these registers is provided in section
12.5. Note that reset bits are not self-clearing.

12.3.7 Peripheral Clock Gating and Reset

The following registers are used for controlling the clock gating and reset of different peripherals. A detailed
description of these registers is provided in section 12.5.

• DPORT_PERI_CLK_EN_REG

• DPORT_PERI_RST_EN_REG

• DPORT_PERIP_CLK_EN_REG

• DPORT_PERIP_RST_EN_REG

• DPORT_WIFI_CLK_EN_REG

• DPORT_WIFI_RST_EN_REG

Notice:

• Clock gating and reset registers are active high.

• Reset registers cannot be cleared by hardware. Therefore, SW reset clear is required after setting the
reset registers.

• ESP32 features low power consumption. This is why some peripheral clocks are gated (disabled) by
default. Before using any of these peripherals, it is mandatory to enable the clock for the given
peripheral by setting the corresponding CLK_EN bit to 1, and release the peripheral from reset state to
make it operational by setting the RST_EN bit to 0.

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12.4 Register Summary

Name Description Address Access

System and memory registers
DPORT_PRO_BOOT_REMAP_CTRL_REG remap mode for PRO_CPU 0x3FF00000 R/W
DPORT_APP_BOOT_REMAP_CTRL_REG remap mode for APP_CPU 0x3FF00004 R/W
the mode of the two caches
DPORT_CACHE_MUX_MODE_REG 0x3FF0007C R/W
sharing the memory
Reset and clock registers
DPORT_CPU_PER_CONF_REG Selects CPU clock 0x3FF0003C R/W
Interrupt matrix registers
DPORT_CPU_INTR_FROM_CPU_0_REG interrupt 0 in both CPUs 0x3FF000DC R/W
DPORT_CPU_INTR_FROM_CPU_1_REG interrupt 1 in both CPUs 0x3FF000E0 R/W
DPORT_CPU_INTR_FROM_CPU_2_REG interrupt 2 in both CPUs 0x3FF000E4 R/W
DPORT_CPU_INTR_FROM_CPU_3_REG interrupt 3 in both CPUs 0x3FF000E8 R/W
DPORT_PRO_INTR_STATUS_REG_0_REG PRO_CPU interrupt status 0 0x3FF000EC RO
DPORT_PRO_INTR_STATUS_REG_1_REG PRO_CPU interrupt status 1 0x3FF000F0 RO
DPORT_PRO_INTR_STATUS_REG_2_REG PRO_CPU interrupt status 2 0x3FF000F4 RO
DPORT_APP_INTR_STATUS_REG_0_REG APP_CPU interrupt status 0 0x3FF000F8 RO
DPORT_APP_INTR_STATUS_REG_1_REG APP_CPU interrupt status 1 0x3FF000FC RO
DPORT_APP_INTR_STATUS_REG_2_REG APP_CPU interrupt status 2 0x3FF00100 RO
DPORT_PRO_MAC_INTR_MAP_REG interrupt map 0x3FF00104 R/W
DPORT_PRO_MAC_NMI_MAP_REG interrupt map 0x3FF00108 R/W
DPORT_PRO_BB_INT_MAP_REG interrupt map 0x3FF0010C R/W
DPORT_PRO_BT_MAC_INT_MAP_REG interrupt map 0x3FF00110 R/W
DPORT_PRO_BT_BB_INT_MAP_REG interrupt map 0x3FF00114 R/W
DPORT_PRO_BT_BB_NMI_MAP_REG interrupt map 0x3FF00118 R/W
DPORT_PRO_RWBT_IRQ_MAP_REG interrupt map 0x3FF0011C R/W
DPORT_PRO_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00120 R/W
DPORT_PRO_RWBT_NMI_MAP_REG interrupt map 0x3FF00124 R/W
DPORT_PRO_RWBLE_NMI_MAP_REG interrupt map 0x3FF00128 R/W
DPORT_PRO_SLC0_INTR_MAP_REG interrupt map 0x3FF0012C R/W
DPORT_PRO_SLC1_INTR_MAP_REG interrupt map 0x3FF00130 R/W
DPORT_PRO_UHCI0_INTR_MAP_REG interrupt map 0x3FF00134 R/W
DPORT_PRO_UHCI1_INTR_MAP_REG interrupt map 0x3FF00138 R/W
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0013C R/W
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00140 R/W
DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00144 R/W
DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00148 R/W
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0014C R/W
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00150 R/W
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00154 R/W
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00158 R/W
DPORT_PRO_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF0015C R/W

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Name Description Address Access

DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00160 R/W
DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00164 R/W
DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF00168 R/W
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG Interrupt map 0x3FF0016C R/W
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00170 R/W
DPORT_PRO_SPI_INTR_0_MAP_REG interrupt map 0x3FF00174 R/W
DPORT_PRO_SPI_INTR_1_MAP_REG interrupt map 0x3FF00178 R/W
DPORT_PRO_SPI_INTR_2_MAP_REG interrupt map 0x3FF0017C R/W
DPORT_PRO_SPI_INTR_3_MAP_REG interrupt map 0x3FF00180 R/W
DPORT_PRO_I2S0_INT_MAP_REG interrupt map 0x3FF00184 R/W
DPORT_PRO_I2S1_INT_MAP_REG interrupt map 0x3FF00188 R/W
DPORT_PRO_UART_INTR_MAP_REG interrupt map 0x3FF0018C R/W
DPORT_PRO_UART1_INTR_MAP_REG interrupt map 0x3FF00190 R/W
DPORT_PRO_UART2_INTR_MAP_REG interrupt map 0x3FF00194 R/W
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF00198 R/W
DPORT_PRO_EMAC_INT_MAP_REG interrupt map 0x3FF0019C R/W
DPORT_PRO_PWM0_INTR_MAP_REG interrupt map 0x3FF001A0 R/W
DPORT_PRO_PWM1_INTR_MAP_REG interrupt map 0x3FF001A4 R/W
DPORT_PRO_LEDC_INT_MAP_REG interrupt map 0x3FF001B0 R/W
DPORT_PRO_EFUSE_INT_MAP_REG interrupt map 0x3FF001B4 R/W
DPORT_PRO_TWAI_INT_MAP_REG interrupt map 0x3FF001B8 R/W
DPORT_PRO_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF001BC R/W
DPORT_PRO_RMT_INTR_MAP_REG interrupt map 0x3FF001C0 R/W
DPORT_PRO_PCNT_INTR_MAP_REG interrupt map 0x3FF001C4 R/W
DPORT_PRO_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF001C8 R/W
DPORT_PRO_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF001CC R/W
DPORT_PRO_RSA_INTR_MAP_REG interrupt map 0x3FF001D0 R/W
DPORT_PRO_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF001D4 R/W
DPORT_PRO_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF001D8 R/W
DPORT_PRO_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF001DC R/W
DPORT_PRO_WDG_INT_MAP_REG interrupt map 0x3FF001E0 R/W
DPORT_PRO_TIMER_INT1_MAP_REG interrupt map 0x3FF001E4 R/W
DPORT_PRO_TIMER_INT2_MAP_REG interrupt map 0x3FF001E8 R/W
DPORT_PRO_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001EC R/W
DPORT_PRO_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF001F0 R/W
DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF001F4 R/W
DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF001F8 R/W
DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001FC R/W
DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00200 R/W
DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00204 R/W
DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF00208 R/W
DPORT_PRO_MMU_IA_INT_MAP_REG interrupt map 0x3FF0020C R/W
DPORT_PRO_MPU_IA_INT_MAP_REG interrupt map 0x3FF00210 R/W

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Name Description Address Access

DPORT_PRO_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00214 R/W
DPORT_APP_MAC_INTR_MAP_REG interrupt map 0x3FF00218 R/W
DPORT_APP_MAC_NMI_MAP_REG interrupt map 0x3FF0021C R/W
DPORT_APP_BB_INT_MAP_REG interrupt map 0x3FF00220 R/W
DPORT_APP_BT_MAC_INT_MAP_REG interrupt map 0x3FF00224 R/W
DPORT_APP_BT_BB_INT_MAP_REG interrupt map 0x3FF00228 R/W
DPORT_APP_BT_BB_NMI_MAP_REG interrupt map 0x3FF0022C R/W
DPORT_APP_RWBT_IRQ_MAP_REG interrupt map 0x3FF00230 R/W
DPORT_APP_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00234 R/W
DPORT_APP_RWBT_NMI_MAP_REG interrupt map 0x3FF00238 R/W
DPORT_APP_RWBLE_NMI_MAP_REG interrupt map 0x3FF0023C R/W
DPORT_APP_SLC0_INTR_MAP_REG interrupt map 0x3FF00240 R/W
DPORT_APP_SLC1_INTR_MAP_REG interrupt map 0x3FF00244 R/W
DPORT_APP_UHCI0_INTR_MAP_REG interrupt map 0x3FF00248 R/W
DPORT_APP_UHCI1_INTR_MAP_REG interrupt map 0x3FF0024C R/W
DPORT_APP_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00250 R/W
DPORT_APP_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00254 R/W
DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00258 R/W
DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0025C R/W
DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00260 R/W
DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00264 R/W
DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00268 R/W
DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0026C R/W
DPORT_APP_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF00270 R/W
DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00274 R/W
DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00278 R/W
DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF0027C R/W
DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG interrupt map 0x3FF00280 R/W
DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00284 R/W
DPORT_APP_SPI_INTR_0_MAP_REG interrupt map 0x3FF00288 R/W
DPORT_APP_SPI_INTR_1_MAP_REG interrupt map 0x3FF0028C R/W
DPORT_APP_SPI_INTR_2_MAP_REG interrupt map 0x3FF00290 R/W
DPORT_APP_SPI_INTR_3_MAP_REG interrupt map 0x3FF00294 R/W
DPORT_APP_I2S0_INT_MAP_REG interrupt map 0x3FF00298 R/W
DPORT_APP_I2S1_INT_MAP_REG interrupt map 0x3FF0029C R/W
DPORT_APP_UART_INTR_MAP_REG interrupt map 0x3FF002A0 R/W
DPORT_APP_UART1_INTR_MAP_REG interrupt map 0x3FF002A4 R/W
DPORT_APP_UART2_INTR_MAP_REG interrupt map 0x3FF002A8 R/W
DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF002AC R/W
DPORT_APP_EMAC_INT_MAP_REG interrupt map 0x3FF002B0 R/W
DPORT_APP_PWM0_INTR_MAP_REG interrupt map 0x3FF002B4 R/W
DPORT_APP_PWM1_INTR_MAP_REG interrupt map 0x3FF002B8 R/W
DPORT_APP_LEDC_INT_MAP_REG interrupt map 0x3FF002C4 R/W

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Name Description Address Access

DPORT_APP_EFUSE_INT_MAP_REG interrupt map 0x3FF002C8 R/W
DPORT_APP_TWAI_INT_MAP_REG interrupt map 0x3FF002CC R/W
DPORT_APP_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF002D0 R/W
DPORT_APP_RMT_INTR_MAP_REG interrupt map 0x3FF002D4 R/W
DPORT_APP_PCNT_INTR_MAP_REG interrupt map 0x3FF002D8 R/W
DPORT_APP_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF002DC R/W
DPORT_APP_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF002E0 R/W
DPORT_APP_RSA_INTR_MAP_REG interrupt map 0x3FF002E4 R/W
DPORT_APP_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF002E8 R/W
DPORT_APP_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF002EC R/W
DPORT_APP_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF002F0 R/W
DPORT_APP_WDG_INT_MAP_REG interrupt map 0x3FF002F4 R/W
DPORT_APP_TIMER_INT1_MAP_REG interrupt map 0x3FF002F8 R/W
DPORT_APP_TIMER_INT2_MAP_REG interrupt map 0x3FF002FC R/W
DPORT_APP_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00300 R/W
DPORT_APP_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00304 R/W
DPORT_APP_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00308 R/W
DPORT_APP_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0030C R/W
DPORT_APP_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00310 R/W
DPORT_APP_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00314 R/W
DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00318 R/W
DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0031C R/W
DPORT_APP_MMU_IA_INT_MAP_REG interrupt map 0x3FF00320 R/W
DPORT_APP_MPU_IA_INT_MAP_REG interrupt map 0x3FF00324 R/W
DPORT_APP_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00328 R/W
DMA registers
selects DMA channel for
DPORT_SPI_DMA_CHAN_SEL_REG 0x3FF005A8 R/W
SPI1, SPI2, and SPI3
MPU/MMU registers
determines the virtual
DPORT_PRO_CACHE_CTRL_REG address mode of the 0x3FF00040 R/W
external SRAM
PRO cache MMU
DPORT_PRO_CACHE_CTRL1_REG 0x3FF00044 R/W
configuration
determines the virtual
DPORT_APP_CACHE_CTRL_REG address mode of the 0x3FF00058 R/W
external SRAM
APP cache MMU
DPORT_APP_CACHE_CTRL1_REG 0x3FF0005C R/W
configuration
page size in the MMU for the
DPORT_IMMU_PAGE_MODE_REG 0x3FF00080 R/W
internal SRAM 0
page size in the MMU for the
DPORT_DMMU_PAGE_MODE_REG 0x3FF00084 R/W
internal SRAM 2
DPORT_AHB_MPU_TABLE_0_REG MPU for configuring DMA 0x3FF000B4 R/W

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Name Description Address Access

DPORT_AHB_MPU_TABLE_1_REG MPU for configuring DMA 0x3FF000B8 R/W
DPORT_AHBLITE_MPU_TABLE_UART_REG MPU for peripherals 0x3FF0032C R/W
DPORT_AHBLITE_MPU_TABLE_SPI1_REG MPU for peripherals 0x3FF00330 R/W
DPORT_AHBLITE_MPU_TABLE_SPI0_REG MPU for peripherals 0x3FF00334 R/W
DPORT_AHBLITE_MPU_TABLE_GPIO_REG MPU for peripherals 0x3FF00338 R/W
DPORT_AHBLITE_MPU_TABLE_RTC_REG MPU for peripherals 0x3FF00348 R/W
DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG MPU for peripherals 0x3FF0034C R/W
DPORT_AHBLITE_MPU_TABLE_HINF_REG MPU for peripherals 0x3FF00354 R/W
DPORT_AHBLITE_MPU_TABLE_UHCI1_REG MPU for peripherals 0x3FF00358 R/W
DPORT_AHBLITE_MPU_TABLE_I2S0_REG MPU for peripherals 0x3FF00364 R/W
DPORT_AHBLITE_MPU_TABLE_UART1_REG MPU for peripherals 0x3FF00368 R/W
DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG MPU for peripherals 0x3FF00374 R/W
DPORT_AHBLITE_MPU_TABLE_UHCI0_REG MPU for peripherals 0x3FF00378 R/W
DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG MPU for peripherals 0x3FF0037C R/W
DPORT_AHBLITE_MPU_TABLE_RMT_REG MPU for peripherals 0x3FF00380 R/W
DPORT_AHBLITE_MPU_TABLE_PCNT_REG MPU for peripherals 0x3FF00384 R/W
DPORT_AHBLITE_MPU_TABLE_SLC_REG MPU for peripherals 0x3FF00388 R/W
DPORT_AHBLITE_MPU_TABLE_LEDC_REG MPU for peripherals 0x3FF0038C R/W
DPORT_AHBLITE_MPU_TABLE_EFUSE_REG MPU for peripherals 0x3FF00390 R/W
DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG MPU for peripherals 0x3FF00394 R/W
DPORT_AHBLITE_MPU_TABLE_PWM0_REG MPU for peripherals 0x3FF0039C R/W
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG MPU for peripherals 0x3FF003A0 R/W
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG MPU for peripherals 0x3FF003A4 R/W
DPORT_AHBLITE_MPU_TABLE_SPI2_REG MPU for peripherals 0x3FF003A8 R/W
DPORT_AHBLITE_MPU_TABLE_SPI3_REG MPU for peripherals 0x3FF003AC R/W
DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG MPU for peripherals 0x3FF003B0 R/W
DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG MPU for peripherals 0x3FF003B4 R/W
DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG MPU for peripherals 0x3FF003B8 R/W
DPORT_AHBLITE_MPU_TABLE_EMAC_REG MPU for peripherals 0x3FF003BC R/W
DPORT_AHBLITE_MPU_TABLE_PWM1_REG MPU for peripherals 0x3FF003C4 R/W
DPORT_AHBLITE_MPU_TABLE_I2S1_REG MPU for peripherals 0x3FF003C8 R/W
DPORT_AHBLITE_MPU_TABLE_UART2_REG MPU for peripherals 0x3FF003CC R/W
DPORT_AHBLITE_MPU_TABLE_PWR_REG MPU for peripherals 0x3FF003E4 R/W
MMU register 1 for internal
DPORT_IMMU_TABLE0_REG 0x3FF00504 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE1_REG 0x3FF00508 R/W
SRAM 0
MMU register 1 for Internal
DPORT_IMMU_TABLE2_REG 0x3FF0050C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE3_REG 0x3FF00510 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE4_REG 0x3FF00514 R/W
SRAM 0

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Name Description Address Access

MMU register 1 for internal
DPORT_IMMU_TABLE5_REG 0x3FF00518 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE6_REG 0x3FF0051C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE7_REG 0x3FF00520 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE8_REG 0x3FF00524 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE9_REG 0x3FF00528 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE10_REG 0x3FF0052C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE11_REG 0x3FF00530 R/W
SRAM 0
MMU register 1 for Internal
DPORT_IMMU_TABLE12_REG 0x3FF00534 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE13_REG 0x3FF00538 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE14_REG 0x3FF0053C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE15_REG 0x3FF00540 R/W
SRAM 0
MMU register 1 for Internal
DPORT_DMMU_TABLE0_REG 0x3FF00544 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE1_REG 0x3FF00548 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE2_REG 0x3FF0054C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE3_REG 0x3FF00550 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE4_REG 0x3FF00554 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE5_REG 0x3FF00558 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE6_REG 0x3FF0055C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE7_REG 0x3FF00560 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE8_REG 0x3FF00564 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE9_REG 0x3FF00568 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE10_REG 0x3FF0056C R/W
SRAM 2

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Name Description Address Access

MMU register 1 for internal
DPORT_DMMU_TABLE11_REG 0x3FF00570 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE12_REG 0x3FF00574 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE13_REG 0x3FF00578 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE14_REG 0x3FF0057C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE15_REG 0x3FF00580 R/W
SRAM 2
APP_CPU controller registers
DPORT_APPCPU_CTRL_REG_A_REG reset for APP_CPU 0x3FF0002C R/W
DPORT_APPCPU_CTRL_REG_B_REG clock gate for APP_CPU 0x3FF00030 R/W
DPORT_APPCPU_CTRL_REG_C_REG stall for APP_CPU 0x3FF00034 R/W
DPORT_APPCPU_CTRL_REG_D_REG boot address for APP_CPU 0x3FF00038 R/W
Peripheral clock gating and reset registers
DPORT_PERI_CLK_EN_REG clock gate for peripherals 0x3FF0001C R/W
DPORT_PERI_RST_EN_REG reset for peripherals 0x3FF00020 R/W
DPORT_PERIP_CLK_EN_REG clock gate for peripherals 0x3FF000C0 R/W
DPORT_PERIP_RST_EN_REG reset for peripherals 0x3FF000C4 R/W
DPORT_WIFI_CLK_EN_REG clock gate for Wi-Fi 0x3FF000CC R/W
DPORT_WIFI_RST_EN_REG reset for Wi-Fi 0x3FF000D0 R/W
MMU/MPU Access Exception Registers
DPORT_MEM_ACCESS_DBUG0_REG SRAM MMU exception flag 0x3FF003E8 RO
DPORT_MEM_ACCESS_DBUG1_REG SRAM MPU exception flag 0x3FF003EC RO
PRO CACHE MMU exception
DPORT_PRO_CACHE_DBUG0_REG 0x3FF003F0 RO
flag
APP CACHE MMU exception
DPORT_APP_CACHE_DBUG0_REG 0x3FF00418 RO
flag
SRAM MMU exception
DPORT_MMU_ACCESS_ILLEGAL_INT_EN_REG 0x3FF00598 R/W
interrupt enable register
SRAM MPU exception
DPORT_MPU_ACCESS_ILLEGAL_INT_EN_REG 0x3FF0059C R/W
interrupt enable register
CACHE MMU exception
DPORT_CACHE_ACCESS_ILLEGAL_INT_EN_REG 0x3FF003A0 R/W
interrupt enable register

12.5 Registers
The addresses in parenthesis besides register names are the register addresses relative to the DPORT base
address provided in Table 3.3-6 Peripheral Address Mapping in Chapter 3 System and Memory. The absolute
register addresses are listed in Section 12.4 Register Summary.

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Register 12.1. DPORT_PRO_BOOT_REMAP_CTRL_REG (0x000)

AP
EM
_R
OT
BO
O_
R
d)

_P
ve

RT
r
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PRO_BOOT_REMAP Remap mode for PRO_CPU. (R/W)

Register 12.2. DPORT_APP_BOOT_REMAP_CTRL_REG (0x004)

AP
EM
_R
OOT
_B
PP
)
ed

_A
rv

RT
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APP_BOOT_REMAP Remap mode for APP_CPU. (R/W)

Register 12.3. DPORT_PERI_CLK_EN_REG (0x01C)

N_ A
RI N_ A

S
_E SH
PE E S

AE
T_ RI_ _R
OR PE _EN
DP RT_ ERI
)
ed

O P
DP RT_
rv
se

O
(re

DP

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PERI_EN_RSA Set the bit to enable the clock of RSA module. Clear the bit to disable the
clock of RSA module. (R/W)

DPORT_PERI_EN_SHA Set the bit to enable the clock of SHA module. Clear the bit to disable the
clock of SHA module. (R/W)

DPORT_PERI_EN_AES Set the bit to enable the clock of AES module. Clear the bit to disable the
clock of AES module. (R/W)

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Register 12.4. DPORT_PERI_RST_EN_REG (0x020)

ST HA
RI ST_ A

ES
PE R RS

_A
_R S
T_ RI_ T_
OR PE _RS
DP RT_ ERI
d)

O P
ve

DP RT_
r
se

O
(re

DP
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PERI_RST_RSA Set the bit to reset RSA module. Clear the bit to release RSA module. (R/W)

DPORT_PERI_RST_SHA Set the bit to reset SHA module. Clear the bit to release SHA module. (R/W)

DPORT_PERI_RST_AES Set the bit to reset AES module. Clear the bit to release AES module. (R/W)

Register 12.5. DPORT_APPCPU_CTRL_REG_A_REG (0x02C)

NG
I
E TT
ES
R
U_
CP
PP
)
ed

A
T_
rv

OR
se
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

DPORT_APPCPU_RESETTING Set to 1 to reset APP_CPU. Clear the bit to release APP_CPU. (R/W)

Register 12.6. DPORT_APPCPU_CTRL_REG_B_REG (0x030)

N
E _E
AT
KG
CL
U_
CP
PP
d)

_A
ve

RT
r
se

O
(re

DP

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APPCPU_CLKGATE_EN Set to 1 to enable the clock of APP_CPU. Clear the bit to disable
the clock of APP_CPU. (R/W)

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Register 12.7. DPORT_APPCPU_CTRL_REG_C_REG (0x034)

ALL
ST
RUN
U_
CP
PP
d)

_A
ve

RT
r
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APPCPU_RUNSTALL Set to 1 to put APP_CPU into stalled state. Clear the bit to release
APP_CPU from stalled state. (R/W)

Register 12.8. DPORT_APPCPU_CTRL_REG_D_REG (0x038)

31 0

0x000000000 Reset

DPORT_APPCPU_CTRL_REG_D_REG When APP_CPU is booted up with ROM code, it will jump to

the address stored in this register. (R/W)

Register 12.9. DPORT_CPU_PER_CONF_REG (0x03C)

L
SE
D_
IO
ER
P UP
_C
PU
)
ed

C
T_
rv

OR
se
(re

DP

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CPU_CPUPERIOD_SEL Select CPU clock. Refer to Table 7.2-2 for details. (R/W)

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Register 12.10. DPORT_PRO_CACHE_CTRL_REG (0x040)

EN H_ NE
LE A
NA

E_ US DO
AB EN
_E

CH FL H_
M

CA E_ US
LE LIT
RA

O_ CH FL
NG SP
L

_I
_H

PR CA E_
SI _
M

O_ AM

T_ O_ CH
RA

PR DR

OR PR CA
_D

T_ O_

DP T_ O_
RO

OR PR

OR PR
)

)
ed

ed

ed

ed
P
T_

DP RT_

DP T_
rv

rv

rv

rv
OR

OR
se

se

se

se
O
(re

(re

(re

(re
DP

DP

DP
31 17 16 15 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

DPORT_PRO_DRAM_HL Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external

flash. (R/W)

DPORT_PRO_CACHE_FLUSH_DONE PRO_CPU cache-flush done. (RO)

DPORT_PRO_CACHE_FLUSH_ENA Flushes the PRO_CPU cache. (R/W)

DPORT_PRO_CACHE_ENABLE Enables the PRO_CPU cache. (R/W)

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Register 12.11. DPORT_PRO_CACHE_CTRL1_REG (0x044)

O_ CH M K_ OM M
PR CA E_ S R A
CA E_ AS DR 0
T_ O_ CH MA _D DR

E_ AS IRO 1
M K_ M0
R

0
CH M K_ AM

IR 1
CL

K_ AM
AM
OR PR CA E_ ASK PS
A_

AS IR
DP RT_ RO_ ACH _M K_O
PD _I
U_ U

O P C E AS
M MM

DP RT_ RO_ ACH _M

CM E_

O P C E
O_ CH

DP RT_ RO_ ACH

PR CA

O P C
T_ O_

DP T_ O_
OR PR

OR PR
d)

)
ed
ve

DP RT_

DP RT_
rv
r
se

se
O

O
(re

(re
DP

DP
31 14 13 12 11 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Reset

DPORT_PRO_CACHE_MMU_IA_CLR Clears PRO cache MMU error flag. (R/W)

DPORT_PRO_CMMU_PD Disables PRO cache MMU. (R/W)

DPORT_PRO_CACHE_MASK_OPSDRAM Disables access from APP_CPU DRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_DROM0 Disables access from PRO_CPU DROM0 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_DRAM1 Disables access from PRO_CPU DRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IROM0 Disables access from PRO_CPU IROM0 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IRAM1 Disables access from PRO_CPU IRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IRAM0 Disables access from PRO_CPU IRAM0 to PRO cache.

1: Disable
0: Enable
(R/W)

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Register 12.12. DPORT_APP_CACHE_CTRL_REG (0x058)

EN H_ NE
LE A
NA

E_ US DO
AB EN
_E

CH FL H_
M

CA E_ US
LE LIT
RA

P_ CH FL
NG SP
L

_I
_H

AP CA E_
SI _
AM

P_ AM

T_ P_ CH
rv _DR

AP DR

OR AP CA
T_ _

DP T_ P_
P

P
(re _AP

OR AP

OR AP
)

OR )

)
ed

ed

ed
e

DP T_

DP T_
rv

rv

rv
T
OR

OR
se

se

se

se
(re

(re

(re
DP

DP

DP
31 15 14 13 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

DPORT_APP_DRAM_HL Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external

flash. (R/W)

DPORT_APP_CACHE_FLUSH_DONE APP_CPU cache-flush done. (RO)

DPORT_APP_CACHE_FLUSH_ENA Flushes the APP_CPU cache. (R/W)

DPORT_APP_CACHE_ENABLE Enables the APP_CPU cache. (R/W)

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Register 12.13. DPORT_APP_CACHE_CTRL1_REG (0x05C)

AP CA E_ SK RO AM
CA E_ S R 0
T_ P_ CH MA _D DR

E_ AS IRO 1
M K_ M0
R

0
P_ CH MA _D M
CH M K_ AM

IR 1
CL

K_ AM
AM
OR AP CA E_ SK PS
A_

AS IR
DP RT_ PP_ CH MA K_O
PD _I
U_ U

O A CA E_ S
M MM

DP RT_ PP_ CH MA
CM E_

O A CA E_
P_ CH

DP RT_ PP_ CH
AP CA

O A CA
T_ P_

DP RT_ PP_
OR AP
d)

)
ed

O A
ve

DP RT_

DP RT_
rv
r
se

se
O

O
(re

(re
DP

DP
31 14 13 12 11 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Reset

DPORT_APP_CACHE_MMU_IA_CLR Clears APP cache MMU error flag. (R/W)

DPORT_APP_CMMU_PD Disables APP cache MMU. (R/W)

DPORT_APP_CACHE_MASK_OPSDRAM Disables access from PRO_CPU DRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_DROM0 Disables access from APP_CPU DROM0 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_DRAM1 Disables access from APP_CPU DRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IROM0 Disables access from APP_CPU IROM0 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IRAM1 Disables access from APP_CPU IRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IRAM0 Disables access from APP_CPU IRAM0 to APP cache.

1: Disable
0: Enable
(R/W)

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Register 12.14. DPORT_CACHE_MUX_MODE_REG (0x07C)

E
OD
_M
UX
M
E_
CH
CA
)
ed

T_
rv

OR
se
(re

DP
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)

Register 12.15. DPORT_IMMU_PAGE_MODE_REG (0x080)

E
OD
_M
GE
ed _PA
U
M
)

(re _IM

)
ed
rv

rv
T
OR
se

se
(re

DP
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)

Register 12.16. DPORT_DMMU_PAGE_MODE_REG (0x084)

E
OD
_M
GE
PA
U_
M
(re _DM
)

)
ed

ed
rv

rv
T
OR
se

se
(re

DP

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)

Register 12.17. DPORT_AHB_MPU_TABLE_0_REG (0x0B4)

31 0

0xFFFFFFFF Reset

DPORT_AHB_MPU_TABLE_0_REG MPU for DMA. (R/W)

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Register 12.18. DPORT_AHB_MPU_TABLE_1_REG (0x0B8)

1
T_
RAN
_G
SS
E
CC
_A
HB
)
ed

A
T_
rv

OR
se
(re

DP
31 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1FF Reset

DPORT_AHB_ACCESS_GRANT_1 MPU for DMA. (R/W)

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Register 12.19. DPORT_PERIP_CLK_EN_REG (0x0C0)

DP T_ NT LK N EN
DP RT_ HCI RO EN K_E
DP RT_ S1_ A_ EN EN

OR PC _C _E LK_

se I2 1_ E EN
O TW 1_ EN EN

O TI C K_ EN
O I2 DM K_ _

O U RG K_ L
DP RT_ ME CL 1_C
DP RT_ I_ CL CLK

(re RT_ RT LK_ LK_

DP RT_ WM K_ K_

DP RT_ ME LK_ EN
DP RT_ I3_ CL K_

DP RT_ DC CLK _C

DP RT_ I2 T0_ EN

K_ N
DP RT_ C_ LK_ EN

EN
DP RT_ HCI LK_ N
DP RT_ MT_ LK N

) CL EN
DP RT_ WM T1_ N

EN
DP rve S0 CLK N
DP RT_ US RO N

O d _CL _E
OR I2 0_ EN
O TI E_ UP

O LE 1_ UP
O P CL CL

O U C _E
O R _C _E
O SP 0_ CL

O SP EX K_
O SP 2_ _

O UA _C C
O P EX E
O I2 _C _

O EF RG E

K_
ed 1_ _
DP RT_ RT EM

DP RT_ AI CLK

DP T_ C_ CL

rv I0 LK
O UA _M

se SP _C
DP T_ RT

(re RT_ RT
OR UA

O UA
d)

se d)

DP RT_ )

DP RT_ )
O d
ve

(re rve
DP rve
r
se

se
(re

(re

31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

11111 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 Reset

Set the following bit to enable the clock of the corresponding module. Clear the bit to disable the
clock of the corresponding module.

DPORT_UART_MEM_CLK_EN Shared memory of UART0 ~ 2. To use any UART peripherals, enable

the clock for UART memory. (R/W)

DPORT_UART2_CLK_EN UART2 module. (R/W)

DPORT_SPI_DMA_CLK_EN SPI_DMA module. (R/W)

DPORT_I2S1_CLK_EN I2S1 module. (R/W)

DPORT_PWM1_CLK_EN PWM1 module. (R/W)

DPORT_TWAI_CLK_EN TWAI module. (R/W)

DPORT_I2C_EXT1_CLK_EN I2C1 module. (R/W)

DPORT_PWM0_CLK_EN PWM0 module. (R/W)

DPORT_SPI3_CLK_EN SPI3 module. (R/W)

DPORT_TIMERGROUP1_CLK_EN TIMG1 module. (R/W)

DPORT_EFUSE_CLK_EN eFuse module. (R/W)

DPORT_TIMERGROUP_CLK_EN TIMG0 module. (R/W)

DPORT_UHCI1_CLK_EN UDMA1 module. (R/W)

DPORT_LEDC_CLK_EN LEDC module. (R/W)

DPORT_PCNT_CLK_EN PCNT module. (R/W)

DPORT_RMT_CLK_EN RMT module. (R/W)

DPORT_UHCI0_CLK_EN UDMA0 module. (R/W)

DPORT_I2C_EXT0_CLK_EN I2C0 module. (R/W)

DPORT_SPI2_CLK_EN SPI2 module. (R/W)

Continued on the next page...

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Chapter 12 DPort Registers GoBack

Register 12.19. DPORT_PERIP_CLK_EN_REG (0x0C0)

Continued from the previous page...

DPORT_UART1_CLK_EN UART1 module. (R/W)

DPORT_I2S0_CLK_EN I2S0 module. (R/W)

DPORT_UART_CLK_EN UART0 module. (R/W)

DPORT_SPI01_CLK_EN SPI0 and SPI1 module. (R/W)

Register 12.20. DPORT_PERIP_RST_EN_REG (0x0C4)

ST

ST
DP RT_ ME RS 1_R
DP RT_ I_ RS RST

DP RT_ DC RST _R

(re RT_ RT ST ST
DP RT_ WM T T

DP RT_ I3_ RS T
O P RS RS

O TI E_ UP

P
O SP 0_ RS
O SP 2_ _

O UA _R R
U
O U RG T
O I2 DM T

O TI R T

O SP EX T
DP RT_ RT EM

DP rve S0 RST
DP T_ AI ST

DP RT_ I2 T0_
DP RT_ S1_ A_

T
DP RT_ MT_ ST
DP T_ NT ST
DP RT_ WM T1_

DP RT_ US RO

DP RT_ HCI RO

DP RT_ C_ RS

rv I0 ST
DP RT_ C_ ST

T
DP RT_ ME ST

DP T_ CI T

) RS
O d _RS
OR TW 1_R

OR UH RS
O UA _M

R
OR PC _R

se SP _R
O I2 0_
O EF RG
O I2 _R

se I2 1_
O P EX

O LE _

ed 1_
_
1
DP T_ RT

(re RT_ RT
OR UA

O UA
)

se d)

DP RT_ )

DP RT_ )
ed

O d

R
(re rve
DP rve
rv
se

se

O
(re

(re

31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Set each bit to reset the corresponding module. Clear the bit to release the corresponding module. For the list
of modules, please refer to register 12.19.

Register 12.21. DPORT_WIFI_CLK_EN_REG (0x0CC)

EN

N
_E
T_

E
OS
IO EN

AV
_H

SL
SD C_

IO
K_ A
CL EM

SD
I_ _

K_
IF K
W CL

CL
T_ FI_

I_
IF
)

)
OR WI

W
ed

ed

ed
DP RT_

T_
rv

rv

rv
OR
se

se

se
O
(re

(re

(re
DP

DP

31 15 14 13 12 5 4 3 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset

DPORT_WIFI_CLK_EMAC_EN Set the bit to enable the clock of Ethernet MAC module. Clear the bit
to disable the clock of Ethernet MAC module. (R/W)

DPORT_WIFI_CLK_SDIO_HOST_EN Set the bit to enable the clock of SD/MMC module. Clear the
bit to disable the clock of SD/MMC module. (R/W)

DPORT_WIFI_CLK_SDIOSLAVE_EN Set the bit to enable the clock of SDIO module. Clear the bit to
disable the clock of SDIO module. (R/W)

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Register 12.22. DPORT_WIFI_RST_EN_REG (0x0D0)

T
ST RS
_R T_
T_ IO ST
IO OS
OR SD _R
SD _H
DP T_ AC
OR EM
d)

)
ed
ve

DP RT_

rv
r
se

se
O
(re

(re
DP
31 8 7 6 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_EMAC_RST Set the bit to reset Ethernet MAC module. Clear the bit to release Ethernet MAC
module. (R/W)

DPORT_SDIO_HOST_RST Set the bit to reset SD/MMC module. Clear the bit to release SD/MMC
module. (R/W)

DPORT_SDIO_RST Set the bit to reset SDIO module. Clear the bit to release SDIO module. (R/W)

Register 12.23. DPORT_CPU_INTR_FROM_CPU_n_REG (n: 0-3) (0xDC+4*n)

n
PU_
_C
M
RO
_F
TR
IN
U_
P
)
ed

_C
rv

RT
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CPU_INTR_FROM_CPU_n Interrupt in both CPUs. (R/W)

Register 12.24. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 0-2) (0xEC+4*n)

31 0

0x000000000 Reset

DPORT_PRO_INTR_STATUS_REG_n_REG PRO_CPU interrupt status. (RO)

Register 12.25. DPORT_APP_INTR_STATUS_REG_n_REG (n: 0-2) (0xF8+4*n)

31 0

0x000000000 Reset

DPORT_APP_INTR_STATUS_REG_n_REG APP_CPU interrupt status. (RO)

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Register 12.26. DPORT_PRO_MAC_INTR_MAP_REG (0x104)

Register 12.27. DPORT_PRO_MAC_NMI_MAP_REG (0x108)

Register 12.28. DPORT_PRO_BB_INT_MAP_REG (0x10C)

Register 12.29. DPORT_PRO_BT_MAC_INT_MAP_REG (0x110)

Register 12.30. DPORT_PRO_BT_BB_INT_MAP_REG (0x114)

Register 12.31. DPORT_PRO_BT_BB_NMI_MAP_REG (0x118)

Register 12.32. DPORT_PRO_RWBT_IRQ_MAP_REG (0x11C)

Register 12.33. DPORT_PRO_RWBLE_IRQ_MAP_REG (0x120)

Register 12.34. DPORT_PRO_RWBT_NMI_MAP_REG (0x124)

Register 12.35. DPORT_PRO_RWBLE_NMI_MAP_REG (0x128)

Register 12.36. DPORT_PRO_SLC0_INTR_MAP_REG (0x12C)

Register 12.37. DPORT_PRO_SLC1_INTR_MAP_REG (0x130)

Register 12.38. DPORT_PRO_UHCI0_INTR_MAP_REG (0x134)

Register 12.39. DPORT_PRO_UHCI1_INTR_MAP_REG (0x138)

Register 12.40. DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (0x13C)

Register 12.41. DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (0x140)

Register 12.42. DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (0x144)

Register 12.43. DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (0x148)

Register 12.44. DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (0x14C)

Register 12.45. DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (0x150)

Register 12.46. DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (0x154)

Register 12.47. DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (0x158)

Register 12.48. DPORT_PRO_GPIO_INTERRUPT_MAP_REG (0x15C)

Register 12.49. DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (0x160)

Register 12.50. DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (0x164)

Register 12.51. DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (0x168)

Register 12.52. DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (0x16C)

Register 12.53. DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x170)

Register 12.54. DPORT_PRO_SPI_INTR_0_MAP_REG (0x174)

Register 12.55. DPORT_PRO_SPI_INTR_1_MAP_REG (0x178)

Register 12.56. DPORT_PRO_SPI_INTR_2_MAP_REG (0x17C)

Register 12.57. DPORT_PRO_SPI_INTR_3_MAP_REG (0x180)

Register 12.58. DPORT_PRO_I2S0_INT_MAP_REG (0x184)

Register 12.59. DPORT_PRO_I2S1_INT_MAP_REG (0x188)

Register 12.60. DPORT_PRO_UART_INTR_MAP_REG (0x18C)

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Register 12.61. DPORT_PRO_UART1_INTR_MAP_REG (0x190)

Register 12.62. DPORT_PRO_UART2_INTR_MAP_REG (0x194)

Register 12.63. DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (0x198)

Register 12.64. DPORT_PRO_EMAC_INT_MAP_REG (0x19C)

Register 12.65. DPORT_PRO_PWM0_INTR_MAP_REG (0x1A0)

Register 12.66. DPORT_PRO_PWM1_INTR_MAP_REG (0x1A4)

Register 12.67. DPORT_PRO_LEDC_INT_MAP_REG (0x1B0)

Register 12.68. DPORT_PRO_EFUSE_INT_MAP_REG (0x1B4)

Register 12.69. DPORT_PRO_TWAI_INT_MAP_REG (0x1B8)

Register 12.70. DPORT_PRO_RTC_CORE_INTR_MAP_REG (0x1BC)

Register 12.71. DPORT_PRO_RMT_INTR_MAP_REG (0x1C0)

Register 12.72. DPORT_PRO_PCNT_INTR_MAP_REG (0x1C4)

Register 12.73. DPORT_PRO_I2C_EXT0_INTR_MAP_REG (0x1C8)

Register 12.74. DPORT_PRO_I2C_EXT1_INTR_MAP_REG (0x1CC)

Register 12.75. DPORT_PRO_RSA_INTR_MAP_REG (0x1D0)

Register 12.76. DPORT_PRO_SPI1_DMA_INT_MAP_REG (0x1D4)

Register 12.77. DPORT_PRO_SPI2_DMA_INT_MAP_REG (0x1D8)

Register 12.78. DPORT_PRO_SPI3_DMA_INT_MAP_REG (0x1DC)

Register 12.79. DPORT_PRO_WDG_INT_MAP_REG (0x1E0)

Register 12.80. DPORT_PRO_TIMER_INT1_MAP_REG (0x1E4)

Register 12.81. DPORT_PRO_TIMER_INT2_MAP_REG (0x1E8)

Register 12.82. DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (0x1EC)

Register 12.83. DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (0x1F0)

Register 12.84. DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (0x1F4)

Register 12.85. DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (0x1F8)

Register 12.86. DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (0x1FC)

Register 12.87. DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (0x200)

Register 12.88. DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (0x204)

Register 12.89. DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (0x208)

Register 12.90. DPORT_PRO_MMU_IA_INT_MAP_REG (0x20C)

Register 12.91. DPORT_PRO_MPU_IA_INT_MAP_REG (0x210)

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Register 12.92. DPORT_PRO_CACHE_IA_INT_MAP_REG (0x214)

AP
M
*_
O_
PR
d)
ve

T_
r

OR
se
(re

DP
31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 Reset

DPORT_PRO_*_MAP Interrupt map. (R/W)

Register 12.93. DPORT_APP_MAC_INTR_MAP_REG (0x218)

Register 12.94. DPORT_APP_MAC_NMI_MAP_REG (0x21C)

Register 12.95. DPORT_APP_BB_INT_MAP_REG (0x220)

Register 12.96. DPORT_APP_BT_MAC_INT_MAP_REG (0x224)

Register 12.97. DPORT_APP_BT_BB_INT_MAP_REG (0x228)

Register 12.98. DPORT_APP_BT_BB_NMI_MAP_REG (0x22C)

Register 12.99. DPORT_APP_RWBT_IRQ_MAP_REG (0x230)

Register 12.100. DPORT_APP_RWBLE_IRQ_MAP_REG (0x234)

Register 12.101. DPORT_APP_RWBT_NMI_MAP_REG (0x238)

Register 12.102. DPORT_APP_RWBLE_NMI_MAP_REG (0x23C)

Register 12.103. DPORT_APP_SLC0_INTR_MAP_REG (0x240)

Register 12.104. DPORT_APP_SLC1_INTR_MAP_REG (0x244)

Register 12.105. DPORT_APP_UHCI0_INTR_MAP_REG (0x248)

Register 12.106. DPORT_APP_UHCI1_INTR_MAP_REG (0x24C)

Register 12.107. DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (0x250)

Register 12.108. DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (0x254)

Register 12.109. DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (0x258)

Register 12.110. DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (0x25C)

Register 12.111. DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (0x260)

Register 12.112. DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (0x264)

Register 12.113. DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (0x268)

Register 12.114. DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (0x26C)

Register 12.115. DPORT_APP_GPIO_INTERRUPT_MAP_REG (0x270)

Register 12.116. DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (0x274)

Register 12.117. DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (0x278)

Register 12.118. DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (0x27C)

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Register 12.119. DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (0x280)

Register 12.120. DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (0x284)

Register 12.121. DPORT_APP_SPI_INTR_0_MAP_REG (0x288)

Register 12.122. DPORT_APP_SPI_INTR_1_MAP_REG (0x28C)

Register 12.123. DPORT_APP_SPI_INTR_2_MAP_REG (0x290)

Register 12.124. DPORT_APP_SPI_INTR_3_MAP_REG (0x294)

Register 12.125. DPORT_APP_I2S0_INT_MAP_REG (0x298)

Register 12.126. DPORT_APP_I2S1_INT_MAP_REG (0x29C)

Register 12.127. DPORT_APP_UART_INTR_MAP_REG (0x2A0)

Register 12.128. DPORT_APP_UART1_INTR_MAP_REG (0x2A4)

Register 12.129. DPORT_APP_UART2_INTR_MAP_REG (0x2A8)

Register 12.130. DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (0x2AC)

Register 12.131. DPORT_APP_EMAC_INT_MAP_REG (0x2B0)

Register 12.132. DPORT_APP_PWM0_INTR_MAP_REG (0x2B4)

Register 12.133. DPORT_APP_PWM1_INTR_MAP_REG (0x2B8)

Register 12.134. DPORT_APP_LEDC_INT_MAP_REG (0x2C4)

Register 12.135. DPORT_APP_EFUSE_INT_MAP_REG (0x2C8)

Register 12.136. DPORT_APP_TWAI_INT_MAP_REG (0x2CC)

Register 12.137. DPORT_APP_RTC_CORE_INTR_MAP_REG (0x2D0)

Register 12.138. DPORT_APP_RMT_INTR_MAP_REG (0x2D4)

Register 12.139. DPORT_APP_PCNT_INTR_MAP_REG (0x2D8)

Register 12.140. DPORT_APP_I2C_EXT0_INTR_MAP_REG (0x2DC)

Register 12.141. DPORT_APP_I2C_EXT1_INTR_MAP_REG (0x2E0)

Register 12.142. DPORT_APP_RSA_INTR_MAP_REG (0x2E4)

Register 12.143. DPORT_APP_SPI1_DMA_INT_MAP_REG (0x2E8)

Register 12.144. DPORT_APP_SPI2_DMA_INT_MAP_REG (0x2EC)

Register 12.145. DPORT_APP_SPI3_DMA_INT_MAP_REG (0x2F0)

Register 12.146. DPORT_APP_WDG_INT_MAP_REG (0x2F4)

Register 12.147. DPORT_APP_TIMER_INT1_MAP_REG (0x2F8)

Register 12.148. DPORT_APP_TIMER_INT2_MAP_REG (0x2FC)

Register 12.149. DPORT_APP_TG_T0_EDGE_INT_MAP_REG (0x300)

Register 12.150. DPORT_APP_TG_T1_EDGE_INT_MAP_REG (0x304)

Register 12.151. DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (0x308)

Register 12.152. DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (0x30C)

Register 12.153. DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (0x310)

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Register 12.154. DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (0x314)

Register 12.155. DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (0x318)

Register 12.156. DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (0x31C)

Register 12.157. DPORT_APP_MMU_IA_INT_MAP_REG (0x320)

Register 12.158. DPORT_APP_MPU_IA_INT_MAP_REG (0x324)

Register 12.159. DPORT_APP_CACHE_IA_INT_MAP_REG (0x328)

AP
_M
_*
PP
d)

A
ve

T_
r

OR
se
(re

DP
31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 Reset

DPORT_APP_*_MAP Interrupt map. (R/W)

Register 12.160. DPORT_AHBLITE_MPU_TABLE_UART_REG (0x32C)

Register 12.161. DPORT_AHBLITE_MPU_TABLE_SPI1_REG (0x330)

Register 12.162. DPORT_AHBLITE_MPU_TABLE_SPI0_REG (0x334)

Register 12.163. DPORT_AHBLITE_MPU_TABLE_GPIO_REG (0x338)

Register 12.164. DPORT_AHBLITE_MPU_TABLE_RTC_REG (0x348)

Register 12.165. DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (0x34C)

Register 12.166. DPORT_AHBLITE_MPU_TABLE_HINF_REG (0x354)

Register 12.167. DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (0x358)

Register 12.168. DPORT_AHBLITE_MPU_TABLE_I2S0_REG (0x364)

Register 12.169. DPORT_AHBLITE_MPU_TABLE_UART1_REG (0x368)

Register 12.170. DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (0x374)

Register 12.171. DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (0x378)

Register 12.172. DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (0x37C)

Register 12.173. DPORT_AHBLITE_MPU_TABLE_RMT_REG (0x380)

Register 12.174. DPORT_AHBLITE_MPU_TABLE_PCNT_REG (0x384)

Register 12.175. DPORT_AHBLITE_MPU_TABLE_SLC_REG (0x388)

Register 12.176. DPORT_AHBLITE_MPU_TABLE_LEDC_REG (0x38C)

Register 12.177. DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (0x390)

Register 12.178. DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (0x394)

Register 12.179. DPORT_AHBLITE_MPU_TABLE_PWM0_REG (0x39C)

Register 12.180. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (0x3A0)

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Register 12.181. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (0x3A4)

Register 12.182. DPORT_AHBLITE_MPU_TABLE_SPI2_REG (0x3A8)

Register 12.183. DPORT_AHBLITE_MPU_TABLE_SPI3_REG (0x3AC)

Register 12.184. DPORT_AHBLITE_MPU_TABLE_SYSCON_REG (0x3B0)

Register 12.185. DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (0x3B4)

Register 12.186. DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (0x3B8)

Register 12.187. DPORT_AHBLITE_MPU_TABLE_EMAC_REG (0x3BC)

Register 12.188. DPORT_AHBLITE_MPU_TABLE_PWM1_REG (0x3C4)

Register 12.189. DPORT_AHBLITE_MPU_TABLE_I2S1_REG (0x3C8)

Register 12.190. DPORT_AHBLITE_MPU_TABLE_UART2_REG (0x3CC)

Register 12.191. DPORT_AHBLITE_MPU_TABLE_PWR_REG (0x3E4)

IG
NF
CO
T_
AN
GR
S_
ES
C
AC
*_
E_
T
LI
HB
)
ed

A
T_
rv

OR
se
(re

DP
31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_AHBLITE_*_ACCESS_GRANT_CONFIG MPU for peripherals. (R/W)

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Register 12.192. DPORT_MEM_ACCESS_DBUG0_REG (0x3E8)

AL
IT
_H

EG

Y
EN
TI

LL
UL

D
I
S_

S_
M

ES

ES
U_

CC

CC
M
_M

_A

_A
EM

EM

EM
d)

d)
M

M
ve

ve
T_

T_

T_
r

r
OR

OR

OR
se

se
(re

(re
DP

DP

DP
31 30 29 26 25 14 13 10 9 0

0 0 0 0 0 0 0 0 0 0 Reset

DPORT_MEM_MMU_MULTI_HIT Indicates configuration errors of SRAM MMU.

Bit 0: APP CPU hits multiple entries when accessing SRAM0
Bit 1: PRO CPU hits multiple entries when accessing SRAM0
Bit 2: APP CPU hits multiple entries when accessing SRAM2
Bit 3: PRO CPU hits multiple entries when accessing SRAM2
(RO)

DPORT_MEM_ACCESS_ILLEGAL CPU address overflow when accessing SRAM (related to page

size).
Bit 0-1: reserved
Bit 2: APP CPU address overflow when accessing SRAM0
Bit 3: PRO CPU address overflow when accessing SRAM0
Bit 4-7: reserved
Bit 8: APP CPU address overflow when accessing SRAM2
Bit 9: PRO CPU address overflow when accessing SRAM3.
Bit 10-11: reserved
(RO)

DPORT_MEM_ACCESS_DENY CPU’s access to SRAM is denied.

Bit 0: APP CPU’s access to SRAM0 is denied
Bit 1: PRO CPU’s access to SRAM0 is denied
Bit 2: APP CPU’s access to SRAM2 is denied
Bit 3: PRO CPU’s access to SRAM2 is denied
(RO)

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Register 12.193. DPORT_MEM_ACCESS_DBUG1_REG (0x3EC)

L
D_ NY

S
GA

IS
E

LE

M
S_ _D

S_
IL
SS

ES
CE

PI

CC
T_ _AC

_A
S
CE

EM
OR MA
AC
d)

M
ed
D
ve

T_

T_
rv
r

OR

OR
se

se
(re

(re
DP

DP

DP
31 9 8 7 6 5 4 3 0

0 0 0 0 0 Reset

DPORT_DMA_ACCESS_DENY DMA’s access to SRAM is denied. (RO)

DPORT_ACCESS_PID_ILLEGAL CPU’s access to the PID controller is illegal.

Bit 0: APP CPU’s illegal access to the PID controller
Bit 1: PRO CPU’s illegal access to the PID controller
(RO)

DPORT_MEM_ACCESS_MISS CPU’s access to SRAM is denied.

Bit 0: APP CPU’s access to SRAM0 is denied
Bit 1: PRO CPU’s access to SRAM0 is denied
Bit 2: APP CPU’s access to SRAM2 is denied
Bit 3: PRO CPU’s access to SRAM2 is denied
(RO)

Register 12.194. DPORT_PRO_CACHE_DBUG0_REG (0x3F0)

L
GA

L
LE

A
EG
IL
S_

ILL
ES

U_
CC

M
_M
_A
HE

HE
AC

AC
_C

_C
RO

RO
)
ed

P
T_

T_
rv

OR

OR
se
(re

DP

DP

30 6 6 1 0

0 0 0 Reset

DPORT_PRO_CACHE_ACCESS_ILLEGAL PRO CPU’s illegal access to CACHE address region.

Bit 0: APP CPU’s illegal access to L VAddrRAM (low-high mode) address region
Bit 1: PRO CPU’s illegal access to V AddrRAM address region
Bit 2: PRO CPU’s illegal access to V Addr3 address region
Bit 3: PRO CPU’s illegal access to V Addr2 address region
Bit 4: PRO CPU’s illegal access to V Addr1 address region
Bit 5: PRO CPU’s illegal access to V Addr4 address region
(RO)

DPORT_PRO_CACHE_MMU_ILLEGAL PRO CPU’s access to invalid CACHE entry. (RO)

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Register 12.195. DPORT_APP_CACHE_DBUG0_REG (0x418)

L
GA

L
LE

GA
IL

LE
S_

IL
ES

U_
CC

M
_M
_A
HE

HE
AC

AC
_C

_C
PP

PP
d)

_A
ve

T_

RT
r

OR
se

O
(re

DP

DP
30 6 6 1 0

0 0 0 Reset

DPORT_APP_CACHE_ACCESS_ILLEGAL APP CPU’s illegal access CACHE address region.

Bit 0: PRO CPU’s illegal access R VAddrRAM (low-high mode) address region
Bit 1: APP CPU’s illegal access V AddrRAM address region
Bit 2: APP CPU’s illegal access V Addr3 address region
Bit 3: APP CPU’s illegal access V Addr2 address region
Bit 4: APP CPU’s illegal access V Addr1 address region
Bit 5: APP CPU’s illegal access V Addr4 address region
(RO)

DPORT_APP_CACHE_MMU_ILLEGAL APP CPU’s access to invalid CACHE entry. (RO)

Register 12.196. DPORT_IMMU_TABLEn_REG (n: 0-15) (0x504+4*n)

En
BL
TA
U_
M
M
)
ed

I
T_
rv

OR
se
(re

DP

31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset

DPORT_IMMU_TABLEn Configures Internal SRAM MMU. When n is 0 ~ 9, reset value is 0. When n

is 10 ~ 15, reset values are 10, 11, 12, 13, 14, 15, respectively. (R/W)

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Register 12.197. DPORT_DMMU_TABLEn_REG (n: 0-15) (0x544+4*n)

En
BL
TA
U_
M
M
d)

D
ve

T_
r

OR
se
(re

DP
31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset

DPORT_DMMU_TABLEn Configures Internal SRAM MMU. When n is 0 ~ 15, reset values are 0 ~ 15,
respectively. (R/W)

Register 12.198. DPORT_MMU_ACCESS_ILLEGAL_INT_EN_REG (0x598)

N
N

_E
EG T_E

NT
N

_I
_I

AL
NY
_P DE

LL
SS S_

_I
S

ID
CE
T_ _AC
CE
A
DP _DM

AC
)

)
ed

ed
rv

rv
T
OR

OR
se

se
(re

(re
DP
31 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_DMA_ACCESS_DENY_INT_EN Enables the DMA’s access to SRAM denied interrupt. (R/W)

DPORT_ACCESS_PID_ILLEGAL_INT_EN Enables the CPU’s illegal access to the PID controller in-
terrupt.
Bit 0: Enables the APP CPU’s illegal access to the PID controller interrupt
Bit 1: Enables the PRO CPU’s illegal access to the PID controller interrupt
(R/W)

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Register 12.199. DPORT_MPU_ACCESS_ILLEGAL_INT_EN_REG (0x59C)

EN
N
_E

T_

EN
NT

IN

T_
I

L_
T_

IN
A
HI

Y_
EG
_

EN
TI

LL
UL

_D
_I
M

SS

SS
U_

E
CC

CC
M
_M

_A

_A
EM

EM

EM
)

d)
M

_M

M
ed

ve
T_

T_
rv

RT

r
OR

OR
se

se
O
(re

(re
DP

DP

DP
31 24 23 20 19 8 7 4 3 0

0 0 0 0 0 0 0 0 0 0 Reset

DPORT_MEM_MMU_MULTI_HIT_INT_EN Enables the SRAM MMU configuration error interrupt.

Bit 0: Enables multiple entry hit interrupt when APP CPU accesses SRAM0
Bit 1: Enables multiple entry hit interrupt when PRO CPU accesses SRAM0
Bit 2: Enables multiple entry hit interrupt when APP CPU accesses SRAM2
Bit 3: Enables multiple entry hit interrupt when PRO CPU accesses SRAM2
(R/W)

DPORT_MEM_ACCESS_ILLEGAL_INT_EN Enables CPU address overflow interrupt when accessing

SRAM (related to page size).
Bit 0-1: reserved
Bit 2: Enables address overflow interrupt when APP CPU accesses SRAM0
Bit 3: Enables address overflow interrupt when PRO CPU accesses SRAM0
Bit 4-7: reserved
Bit 8: Enables address overflow interrupt when APP CPU accesses SRAM2
Bit 9: Enable address overflow interrupt when PRO CPU accesses SRAM3
Bit 10-11: reserved
(R/W)

DPORT_MEM_ACCESS_DENY_INT_EN Enables the CPU’s access to SRAM denied interrupt.

Bit 0: Enables denied interrupt when APP CPU accesses SRAM0
Bit 1: Enables denied interrupt when PRO CPU accesses SRAM0
Bit 2: Enables denied interrupt when APP CPU accesses SRAM2
Bit 3: Enable denied interrupt when PRO CPU accesses SRAM2
(R/W)

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Register 12.200. DPORT_CACHE_ACCESS_ILLEGAL_INT_EN_REG (0x3A0)

EN
E
T_

T_

EN
_E
IN

IN

T_
NT
L_

L_

IN
_I
A

GA

L_
EG

AL

LE

GA
LL

EG

IL

LE
I
S_

S_
IL

IL
S

U_

ES

U_
CE

CC
M

M
AC

_M

_M
_A
E_

HE

HE

HE
H
AC

AC

AC

AC
_C

_C

_C

_C
RO

RO

PP

PP
d)

d)

)
ed
P

A
ve

ve
T_

T_

T_

T_

rv
r

r
OR

OR

OR

OR
se

se

se
(re

(re

(re
DP

DP

DP

DP
31 28 27 22 21 20 14 13 8 7 6 0

0 0 0 0 0 0 0 Reset

DPORT_PRO_CACHE_ACCESS_ILLEGAL_INT_EN Enables the PRO CPU’s illegal access to CACHE

address region interrupt.
Bit 0: Enables the APP CPU’s illegal access to L VAddrRAM (low-high mode) address region inter-
rupt
Bit 1: Enables the PRO CPU’s illegal access to V AddrRAM address region interrupt
Bit 2: Enables the PRO CPU’s illegal access to V Addr3 address region interrupt
Bit 3: Enables the PRO CPU’s illegal access to V Addr2 address region interrupt
Bit 4: Enables the PRO CPU’s illegal access to V Addr1 address region interrupt
Bit 5: Enables the PRO CPU’s illegal access to V Addr4 address region interrupt
(RO)

DPORT_PRO_CACHE_MMU_ILLEGAL_INT_EN Enables the PRO CPU’s access to invalid CACHE en-

try. (RO)

DPORT_APP_CACHE_ACCESS_ILLEGAL_INT_EN Enables the APP CPU’s illegal access to CACHE

address region interrupt.
Bit 0: Enables the PRO CPU’s illegal access to R VAddrRAM (low-high mode) address region inter-
rupt
Bit 1: Enables the APP CPU’s illegal access to V AddrRAM address region interrupt
Bit 2: Enables the APP CPU’s illegal access to V Addr3 address region interrupt
Bit 3: Enables the APP CPU’s illegal access to V Addr2 address region interrupt
Bit 4: Enables the APP CPU’s illegal access to V Addr1 address region interrupt
Bit 5: Enables the APP CPU’s illegal access to V Addr4 address region interrupt
(RO)

DPORT_APP_CACHE_MMU_ILLEGAL_INT_EN Enables the APP CPU’s access to invalid CACHE en-

try. (RO)

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Register 12.201. DPORT_SPI_DMA_CHAN_SEL_REG (0x5A8)

EL
EL

EL
_S
_S

_S
AN
AN

AN
CH
CH

CH
A_
A_

A_
M
M

DM
D
_D

2_

I1_
I3

PI
P

SP
_S

_S

I_
PI

PI

SP
d)

S
ve

T_

T_

T_
r

OR

OR

OR
se
(re

DP

DP

DP
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_SPI_SPI3_DMA_CHAN_SEL Selects the DMA channel for SPI3. (R/W)

DPORT_SPI_SPI2_DMA_CHAN_SEL Selects the DMA channel for SPI2. (R/W)

DPORT_SPI_SPI1_DMA_CHAN_SEL Selects the DMA channel for SPI1. (R/W)

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Chapter 13

Process ID Controller (PID)

13.1 Overview
The ESP32 is a dual core device and is capable of running and managing multiple processes. The PID
Controller supports switching of PID when a process switch occurs. In addition to PID management, the PID
Controller also facilitates management of nested interrupts by recording execution status just before an
interrupt service routine is executed. This enables the user application to manage process switches and
nested interrupts more efficiently.

13.2 Features
The PID Controller features:

• Process management and priority

• Process PID switch

• Interrupt information recording

• Nested interrupt management

13.3 Functional Description

Eight processes run on the CPU, and are assigned with PID of 0 ~ 7 respectively. Among the eight processes,
processes with PID of 0 or 1 are elevated processes with higher authority compared to processes with PID
ranging from 2 ~ 7.

A CPU process switch may occur in two cases:

• An interrupt occurs and the CPU fetches an instruction from the interrupt vector. Instruction fetch or
execution from interrupt vector is always treated as a process with PID of 0, irrespective of which
process was being executed on the CPU when the interrupt occurred.

• A currently active process explicitly performs a process switch. Only elevated processes with PID of 0 or
1 may perform a process switch.

13.3.1 Interrupt Identification

Interrupts are classified into seven priority levels: Level 1, Level 2, Level 3, Level 4, Level 5, Level 6 (Debug),
and NMI. Each level of interrupt is assigned an interrupt vector entry address. The PID Controller recognizes
CPU instruction fetch from an interrupt vector entry address and automatically switches PID to 0. If CPU only
accesses the interrupt vector entry address, PID Controller performs no action.

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PIDCTRL_INTERRUPT_ENABLE_REG determines whether the PID Controller identifies and registers an interrupt
of certain priority. When a bit of register PIDCTRL_INTERRUPT_ENABLE_REG is 1, PID Controller will take action
when CPU fetches instruction from the interrupt vector entry address of the corresponding interrupt.
Otherwise, PID Controller performs no action. The registers PIDCTRL_INTERRUPT_ADDR_1_REG ~
PIDCTRL_INTERRUPT_ADDR_7_REG define the interrupt vector entry address for all the interrupt priority levels.
For details please refer to Table 13.3-1.

Table 13.3-1. Interrupt Vector Entry Address

PIDCTRL_INTERRUPT_ENABLE_REG bit
Priority level Interrupt vector entry address
controlling interrupt identification
Level 1 1 PIDCTRL_INTERRUPT_ADDR_1_REG
Level 2 2 PIDCTRL_INTERRUPT_ADDR_2_REG
Level 3 3 PIDCTRL_INTERRUPT_ADDR_3_REG
Level 4 4 PIDCTRL_INTERRUPT_ADDR_4_REG
Level 5 5 PIDCTRL_INTERRUPT_ADDR_5_REG
Level 6 ( Debug 6 PIDCTRL_INTERRUPT_ADDR_6_REG
)
NMI 7 PIDCTRL_INTERRUPT_ADDR_7_REG

13.3.2 Information Recording

When PID Controller identifies an interrupt, it records three items of information in addition to switching PID to
0. The recorded information includes the priority level of current interrupt, previous interrupt status of the
system and the previous process running on the CPU.

PID Controller records the priority level of the current interrupt in register PIDCTRL_LEVEL_REG. For details
please refer to Table 13.3-2.

Table 13.3-2. Configuration of PIDCTRL_LEVEL_REG

Value Priority level of the current interrupt

0 No interrupt
1 Level 1
2 Level 2
3 Level 3
4 Level 4
5 Level 5
6 Level 6
7 NMI

PID Controller also records in register PIDCTRL_FROM_n_REG the status of the system before the interrupt
occurred. The bit width of register PIDCTRL_FROM_n_REG is 7. The highest four bits represent the interrupt
status of the system before the interrupt indicated by the register occurred. The lowest three bits represent
the process running on the CPU before the interrupt indicated by the register occurred. For details please
refer to Table 13.3-3.

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Table 13.3-3. Configuration of PIDCTRL_FROM_n_REG

[6:3] Previous interrupt [2:0] Previous process

0 No interrupt 0 Process with PID of 0
1 Level 1 Interrupt 1 Process with PID of 1
2 Level 2 Interrupt 2 Process with PID of 2
3 Level 3 Interrupt 3 Process with PID of 3
4 Level 4 Interrupt 4 Process with PID of 4
5 Level 5 Interrupt 5 Process with PID of 5
6 Level 6 Interrupt 6 Process with PID of 6
7 Level 7 Interrupt 7 Process with PID of 7

PID Controller possesses registers PIDCTRL_FROM_1_REG ~ PIDCTRL_FROM_7_REG, which correspond to

the interrupts of Level 1, Level 2, Level 3, Level 4, Level 5, Level 6 (Debug), and NMI respectively. This enables
the system to implement interrupt nesting. Please refer to Table 13.3-1 for examples.

If the configuration of register PIDCTRL_INTERRUPT_ENABLE_REG prevents PID Controller from identifying an

interrupt, PID Controller will not record any information, and PIDCTRL_LEVEL_REG and
PIDCTRL_FROM_n_REG will remain unchanged.

13.3.3 Proactive Process Switching

As mentioned before, only an elevated process with PID of 0/1 can initiate a process switch. The new process
may have any PID from 0 ~ 7 after the process switch. The key for successful proactive process switching is
that when the last command of the current process switches to the first command of the new process, PID
should switch from 0/1 to that of the new process.

The software procedure for proactive process switching is as follows:

1. Mask all the interrupts except NMI by using software.

2. Set register PIDCTRL_NMI_MASK_ENABLE_REG to 1 to generate a CPU NMI Interrupt Mask signal.

3. Configure registers PIDCTRL_PID_DELAY_REG and PIDCTRL_NMI_DELAY_REG.

4. Configure register PIDCTRL_PID_NEW_REG.

5. Configure register PIDCTRL_LEVEL_REG and PIDCTRL_FROM_n_REG.

6. Set register PIDCTRL_PID_CONFIRM_REG and register PIDCTRL_NMI_MASK_DISABLE_REG to 1.

7. Revoke the masking of all interrupts but NMI.

8. Switch to the new process and fetch instruction.

Though we can deal with interrupt nesting, an elevated process should not be interrupted during the process
switching, and therefore the interrupts have been masked in step 1 and step 2.

In step 3, the configured values of registers PIDCTRL_PID_DELAY_REG and PIDCTRL_NMI_DELAY_REG will

affect step 6.

In step 4, the configured value of register PIDCTRL_PID_NEW_REG will be the new PID after step 6.

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Figure 13.3-1. Interrupt Nesting

If the system is currently in a nested interrupt and needs to revert to the previous interrupt, register
PIDCTRL_LEVEL_REG must be restored based on the information recorded in register PIDCTRL_FROM_n_REG
in step 5.

In step 6, after the values of register PIDCTRL_PID_CONFIRM_REG and register

PIDCTRL_NMI_MASK_DISABLE_REG are set to 1, PID Controller will not immediately switch PID to the value of
register PIDCTRL_PID