Day 6 – Arithmetic Logic Unit
(RTL Module)
Submitted By
Rudraksh Pachauri
[Link] EC (VLSI)
GLA University
Contents
1. Description 3
2. RTL Code (System Verilog) 3
3. Testbench Code 4
4. Truth Table 4
5. Simulation Result 4
6. Schematic 5
7. Applications 5
8. Advantages 5
9. Disadvantages 5
10. Conclusion 6
Description
An ALU (Arithmetic Logic Unit) is the heart of any processor
or digital system. It performs arithmetic and logic operations
on input operands.
In this design, I implemented a 6-bit ALU in System Verilog,
capable of executing the following operations based on a 3-bit
opcode:
• 000: Addition
• 001: Subtraction
• 010: Bitwise AND
• 011: Bitwise OR
• 100: Bitwise XOR
• 101: Bitwise NOT (on A only)
• 110: A left shift
• 111: A right shift
The ALU takes two 6-bit inputs A and B, a 3-bit control input
opcode, and produces a 6-bit result along with a zero_flag
output (set when result is zero).
RTL Code (System Verilog)
module alu_6bit (
input logic [5:0] A,
input logic [5:0] B,
input logic [2:0] opcode,
output logic [5:0] result,
output logic zero_flag
);
always_comb begin
case (opcode)
3'b000: result = A + B; // Addition
3'b001: result = A - B; // Subtraction
3'b010: result = A & B; // Bitwise AND
3'b011: result = A | B; // Bitwise OR
3'b100: result = A ^ B; // Bitwise XOR
3'b101: result = ~A; // Bitwise NOT on A
3'b110: result = A << 1; // Logical left shift
3'b111: result = A >> 1; // Logical right shift
default: result = 6'b000000;
endcase
end
assign zero_flag = (result == 6'b000000);
endmodule
Testbench Code
module tb_alu_6bit;
logic [5:0] A, B;
logic [2:0] opcode;
logic [5:0] result;
logic zero_flag;
alu_6bit uut (
.A(A),
.B(B),
.opcode(opcode),
.result(result),
.zero_flag(zero_flag)
);
initial begin
$display("Opcode | A B => Result ZeroFlag");
$display("------------------------------------------");
A = 6'b000101; B = 6'b000011;
opcode = 3'b000; #10; $display("ADD | %b %b => %b
%b", A, B, result, zero_flag);
opcode = 3'b001; #10; $display("SUB | %b %b => %b
%b", A, B, result, zero_flag);
opcode = 3'b010; #10; $display("AND | %b %b => %b
%b", A, B, result, zero_flag);
opcode = 3'b011; #10; $display("OR | %b %b => %b
%b", A, B, result, zero_flag);
opcode = 3'b100; #10; $display("XOR | %b %b => %b
%b", A, B, result, zero_flag);
opcode = 3'b101; #10; $display("NOT A | %b => %b
%b", A, result, zero_flag);
opcode = 3'b110; #10; $display("LSHIFT | %b => %b
%b", A, result, zero_flag);
opcode = 3'b111; #10; $display("RSHIFT | %b => %b
%b", A, result, zero_flag);
$finish;
end
endmodule
Truth Table
Input Operations Description
000 A+B Addition
001 A-B Subtraction
010 A&B Bitwise AND
011 A|B Bitwise OR
100 A^B Bitwise XOR
101 ~A Bitwise NOT on A
110 A<<1 Logical Left Shift
111 A>>1 Logical Right Shift
Simulation
Schematic
Applications
• Central Processing Units (CPUs)
• Embedded controllers
• Signal processing systems
• Hardware arithmetic blocks
• Digital calculators
Advantages
• Fast execution of basic arithmetic and logic operations
• Can be parameterized for larger widths
• Purely combinational – no clock needed
• Easily extendable to add new operations
Disadvantages
• Requires significant logic resources as width increases
• No overflow detection or signed arithmetic support in
basic design
• Needs extra flags and modules for real-world CPU
integration
Conclusion
The 6-bit ALU built today forms a miniature brain capable of
performing a variety of operations — from addition to bit-level
manipulation. Designing this in System Verilog helped me understand
how control signals (opcodes) steer the functionality of a data-path
and how multiple operations can be unified under a single module. It’s
an essential building block in any processor or embedded system.
