Hindawi Publishing Corporation

Advances in Electrical Engineering

Volume 2014, Article ID 374741, 5 pages
[Link]

Research Article
Multiobjective Genetic Algorithms Program for
the Optimization of an OTA for Front-End Electronics

Abdelghani Dendouga,1 Slimane Oussalah,1 Damien Thienpont,2 and Abdenour Lounis3

1
Division Microelectronique et Nanotechnologie, Centre de Développement des Technologies Avancées (CDTA),
Cité é20 Août 1956, 16000 Algiers, Algeria
2
OMEGA Micro, Microelectronics Design Center, Polytechnic School, LLR Aile 4, 91128 Palaiseau Cedex, France
3
Laboratoire de l’Accélérateur Linéaire (LAL), Centre Scientifique d’Orsay, Université de Paris Sud XI, Bat 200, BP 34,
91898 Orsay Cedex, France

Correspondence should be addressed to Abdelghani Dendouga; adendouga@[Link]

Received 30 April 2014; Revised 7 July 2014; Accepted 8 July 2014; Published 13 August 2014

Academic Editor: Changhwan Shin

Copyright © 2014 Abdelghani Dendouga et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.

The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce
these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method
based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed
methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational
amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) based circuit applications.
Six performances are considered in this study, direct current (DC) gain, unity-gain bandwidth (GBW), phase margin (PM),
power consumption (P), area (A), and slew rate (SR). We used the Matlab optimization toolbox to implement the program. Also,
by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA) is simulated by using
Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company) RF 0.18 𝜇m
CMOS technology. A good agreement is observed between the program optimization and electric simulation.

1. Introduction This method uses a program based on multiobjective

optimization using a genetic algorithm to calculate the
Microelectronics industry is distinguished by the raising level
of integration and complexity. It aims at decreasing exponen- optimal transistors dimensions, length, and width of an
tially the minimum feature sizes used to design integrated operational amplifier (Figure 1) which is used as part of an
circuits [1]. The cost in time of design is a great problem to the electronic front-end for signal shaping stage. The method
continuation of this evolution. Senior designer’s knowledge which handles a wide variety of specifications and constraints
and skills are required to ensure a good analog integrated is extremely fast and results in globally optimal designs.
circuit design. To fulfill the given requirements, the designer The aim of this work is to design and optimize an
must choose the suitable circuit architecture, although dif- operational amplifier circuit in sight of a front-end electronics
ferent tools which partially automated the topology synthesis of the semiconductor tracker (SCT) detector in ATLAS (A
appeared in the past [2, 3]. Toroidal LHC Apparatus) experiment. ATLAS is a parti-
Therefore, the use of multiple-objective optimization cle physics experiment at the Large Hadron Collider at
algorithms is of a great importance to the automatic CERN (the European Organization for Nuclear Research) in
design of operational amplifier. Accuracy, ease of use, gen- Switzerland.
erality, robustness, and reasonable run-time are necessary This paper is organized as follows. The amplifier structure
for a circuit synthesis solution to gain acceptance by using is analyzed in Sections 2 and 3. Section 4 describes the opti-
optimization methods [4–9]. mization approach proposed in this work. Section 5 presents
2 Advances in Electrical Engineering

Optimization VDD
Performances Optimal transistors
dimensions M3 M4
Ib
∙ DC gain Matlab
∙ Bandwidth M6
∙ Phase margin ∙ Li
∙ Slew rate Vout
Program ∙ Wi M1 M2
∙ Area
Vin− Vin+ CC
∙ Power
∙ ... CL

M8 M5 M7
Verification

Transistors Performances VSS

dimensions
∙ DC gain Figure 2: The two-stage operational amplifier architecture used in
Cadence
∙ Bandwidth this study is composed of eight CMOS transistors.
∙ Li ∙ Phase margin
∙ Wi CAD tools ∙ Slew rate
∙ Area
∙ Power where 𝑔𝑚 (𝑔𝑚1 𝑔𝑚6 ) is the transconductance of transistors
∙ ... (M 1 and M 6 ) and 𝑔𝑑𝑠 is the output conductance.
Figure 1: Operational amplifier design flow.
3.2. Unity-Gain Bandwidth. The unity-gain bandwidth is
given by the expression [1]
the obtained results, and there is a section for the comparison 𝑔𝑚1
of our work with other optimization approaches. Finally some GBW = , (2)
𝐶𝐶
concluding remarks are provided after evaluating our study
towards other works. where CC is the compensation capacitance.

2. Design Methodology 3.3. Phase Margin. The phase margin of operational amplifier
depends on the sum of phase shifts, at the unity-gain
Optimal design of analog circuits consists of finding a variable
frequency, contributed by the nondominant poles (𝑝1 and
set 𝑥 = {𝑥1 , 𝑥2 , . . . , 𝑥𝑛 } that optimizes performance functions,
𝑝2) and zeros (𝑧):
such as gain, offset, signal to noise ratio, and maximum
operating frequency, while meeting imposed specifications GBW
and/or inherent constraints, for example, saturation con- PM = ±180 − tan−1 ( )
𝑝1
ditions of transistors, technology limits, and impedance (3)
matching. Vector 𝑥 may encompass biases, lengths (L), and −1GBW GBW
widths (W) of MOS transistors, component values, and so − tan ( ) − tan−1 ( ).
𝑝2 𝑧
forth [5].
3.4. Slew Rate. For this operational amplifier, the slew rate is
3. Specifications given by
We concentrate on one operational amplifier topology and 𝐼5
the two-stage operational amplifier shown in Figure 2. The SR = , (4)
𝐶𝐶
main electrical parameters of the circuit are low frequency
voltage gain (𝐴 V ), gain-bandwidth product (GBW), slew- where 𝐼5 is the current that flows through transistor 𝑀5 .
rate (SR), dissipated power (𝑃diss ), phase margin (PM), and
area (A), among others. The design variables are the size 3.5. Power Consumption. For the two-stage operational
of transistor (width and length), the value of the passive amplifier, the power consumption has the form [10]
components (capacitors and resistors), and the value of bias
currents and bias voltages. For this particular two-stage 𝑃 = (𝑉DD − 𝑉SS ) (𝐼5 + 2𝐼7 ) . (5)
operational amplifier, there are fourteen design variables.
3.6. Area. The area A of the operational amplifier is given by
3.1. Open-Loop DC Gain. For the two-stage op-amp, the the sum of transistors and capacitors areas:
open-loop voltage gain is given by [3]
𝑘
𝑔𝑚1 𝑔𝑚6 Area = ∑𝑊𝑖 ⋅ 𝐿 𝑖 . (6)
𝐴V = ⋅ , (1)
𝑔𝑑𝑠2 + 𝑔𝑑𝑠4 𝑔𝑑𝑠7 + 𝑔𝑑𝑠6 𝑖=1
Advances in Electrical Engineering 3

4. Optimization Begin

To make the system power level, it is obviously important to

size the different constituent blocks. At this level, the perfor-
mance of each unit becomes constraints to be respected. The Initial population
performances are bound by a set of equations which depends
on the considered characteristics (gain, SR, etc.). The set of
equations is nonlinear, and there is no systematic analytical Evaluation
method to solve it. In addition, the solution is not unique.
For this reason, the best way is to use an optimizer that
will help automate the resolution of equations (synthesis of Reproduction
analog circuits). It is important to note that, in the design
of analog circuits, compromises are made because there
are many performance parameters used to describe them. Crossing
Nonlinear relationships between them make them a more
delicate design.
Optimal design of analog circuits is to find a set of Mutation
variables 𝑥 = {𝑥1 , 𝑥2 , . . . , 𝑥𝑛 } that optimizes performance,
such as gain, offset, and signal to noise ratio, while respecting
the imposed specifications and/or constraints [6].
In the program, every individual is presented by a binary Test stop
code string. From Figure 2, we can see that there are 8 No
transistors and a biasing current to be adjusted. As a total, Yes
there are 10 parameters to be adjusted and each gene of the
chromosome stands for one parameter. Thus, the parameter Stop
vector is compressed to [8] [𝑊1 , 𝐿 1 , 𝑊3 , 𝐿 3 , 𝑊5 , 𝐿 5 , 𝑊7 , 𝐿 7 ,
Figure 3: Basic procedures of genetic algorithms.
𝑊8 , 𝐿 8 ].
Genetic algorithms start with an initial population of
randomly generated individuals. Each individual in the
population represents a possible solution to the problem of
the study. Individuals evolve through successive iterations, next generation and several stopping criteria of the algorithm
called generations. In every generation, each individual in are possible: the number of generations can be fixed a priori
the population is evaluated using a measure of fitness. Then, (time constant) or the algorithm can be stopped when the
the population of the next generation is created by genetic population does not evolve fast enough.
operators. The procedure continues until the stop condition
is satisfied (Figure 3).
A weighted approach is used to optimize operational
5. Results
amplifiers. It uses adaptive weights along the optimization Six performances are considered in this program. They are
process to determine the overall fitness of an individual [7]: the DC gain, bandwidth of unity-gain, phase margin, power
𝑛
consumption, area, and slew rate. The optimization process
𝐹 =∑ 𝜔𝑖 ⋅ 𝑓𝑖 , (7) optimizes the individual to improve its fitness score. This
𝑖=1 process will continue until the total number of generations
is reached.
where 𝜔𝑖 is the weight coefficient of every subobjective, 𝑓𝑖 is Also, by using variables obtained from GA, the OTA
the overall fitness of every performance considered, and 𝑖 is circuit is simulated by using Cadence Virtuoso Spectre in
the number of the performances considered. TSMC 0.18 𝜇m CMOS process and simulation results are
We used the Matlab optimization toolbox to implement shown in Table 2 and Figure 4.
optimization by MOGA. It starts by generating a random Table 2 shows the performance of the design obtained by
population of individuals. To pass from one generation 𝑘 to Matlab optimization tools. The objective was to maximize
generation 𝑘 + 1, the following operations are performed. At the unity-gain bandwidth and minimize power consumption
first, the population is reproduced by good selection where subject to the other given constraints. The simulation results
individuals with the best evaluations tend to reproduce more confirm the efficiency of GA in determining the device sizes
often than those with bad evaluations. This population is in an analog circuit.
applied to cross pairs of individuals (parents) of a certain According to the simulation results, the performance of
proportion of the population (probability 𝑃𝑐 , usually around the operational amplifier optimized by the proposed method
0.6) to produce new children. A mutation operator is applied represents a good method to optimize an analog circuit.
to a certain proportion of the population (probability 𝑃𝑚 , After introducing the transistors dimensions (Table 1) in
the 𝑃𝑐 generally much lower). Finally, the new individuals Spectre and making the different simulations, we pass to the
are evaluated and incorporated into the population of the layout of the circuit which is represented in Figure 5 and the
4 Advances in Electrical Engineering

100 50
70 0
−50
Gain (dB)

Phase (deg)
40
10 −100

−20 −150

−50 −200

−80 −250
1.E + 00

1.E + 01

1.E + 02

1.E + 03

1.E + 04

1.E + 05

1.E + 06

1.E + 07

1.E + 08

1.E + 00

1.E + 01

1.E + 02

1.E + 03

1.E + 04

1.E + 05

1.E + 06

1.E + 07

1.E + 08
Frequency (Hz) Frequency (Hz)
(a) (b)

Figure 4: Gain and phase simulation of the obtained transistors dimensions.

Table 1: Optimal transistors dimensions.

Variable Value (𝜇m)

𝑊1 = 𝑊2 1.34
𝐿1 = 𝐿2 1.5
𝑊3 = 𝑊4 8.5
𝐿3 = 𝐿4 1.11
𝑊5 1.4
𝐿5 0.44
𝑊6 48
𝐿6 0.92
𝑊7 6
𝐿7 0.8
𝑊8 23.5
𝐿8 0.68

Table 2: Simulation results in Matlab and Spectre.

Performances Specifications MOGA program Spectre

DC gain (dB) ≥70 76 75
Figure 5: Layout of the operational amplifier.
Unity gain (MHz) Max 1.5 1.11
Phase margin (∘ ) ≥60 70 64
Slew rate (V/𝜇s) Max 2.25 2.19
Area (𝜇m2 ) Min 559 678
Power (mW) ≤0.5 0.047 0.051 6. Comparison
The lack of detail necessary to compare the results (such as
limits of design variables, the supply voltage, bias current,
capacitive load time, and circuit optimization) makes the
postlayout simulations. Figure 4 represents the simulation of comparison of our work with other optimization approaches
gain and phase of the circuit. presented a difficult task [11].
The results given in the two Tables 1 and 2, respec- Kubar and Jakovenko [11] present comparisons with
tively, represent the dimensions and performance operational works using Miller two-stage OTA design example. These
amplifiers obtained for different constraints and conditions. works [10, 12] are using particle swarm optimization.
With constraints on the optimizer, the satisfactory results The differences between the work [9] and our case are that
(GWB aspects gain and PM) are obtained. However, the transistors of the current mirror (𝑀3 and 𝑀4) do not have
program happens to minimize power consumption and the same size. Table 3 presents results in comparison with our
layout area. design.
Advances in Electrical Engineering 5

Table 3 IEEE/ACM International Conference on Computer-Aided Design

(ICCAD ’98), pp. 296–303, San Jose, Calif, USA, November
Variable Lower bound Upper bound Our result Result [9]
1998.
𝑊1 (𝜇m) 5 100 1.34 87.1
[4] J. Tao, X. Chen, and Y. Zhu, “Constraint multi-objective auto-
𝐿 1 (𝜇m) 0.18 2 1.5 0.55 mated synthesis for CMOS operational amplifier,” in Life System
𝑊2 (𝜇m) 5 100 1.34 87.1 Modeling and Intelligent Computing, vol. 6329 of Lecture Notes
𝐿 2 (𝜇m) 0.18 2 1.5 0.55 in Computer Science, pp. 120–127, 2010.
𝑊3 (𝜇m) 3 200 8.5 400 [5] M. Takhti, A. Beirami, and H. Shamsi, “Multi-objective design
𝐿 3 (𝜇m) 0.18 2 1.11 8.4 automation of the folded-cascode OP-AMP using nsga-II strat-
egy,” in Proceedings of the International Symposium on Signals,
𝑊4 (𝜇m) 7 100 8.5 400
Circuits and Systems (ISSCS '09), pp. 1–4, Ias, i, Romania, July
𝐿 4 (𝜇m) 0.18 2 1.11 8.4 2009.
𝑊5 (𝜇m) 3 60 1.4 62.5 [6] M. Köppen, G. Schaefer, and A. Abraham, Intelligent Computa-
𝐿 5 (𝜇m) 0.18 2 0.44 0.55 tional Optimization in Engineering, Springer, 2011.
𝑊6 (𝜇m) 3 60 48 331.8 [7] P. Jianhai Yu and Z. Mao, “Automated design method for
𝐿 6 (𝜇m) 0.18 2 0.92 0.4 parameters optimization of CMOS analog circuits based on
𝑊7 (𝜇m) 3 60 6 62.5 adaptive genetic algorithm,” in Proceedings of the 7th Interna-
tional Conference on ASIC (ASICON ’07), pp. 1217–1220, Guilin,
𝐿 7 (𝜇m) 0.18 2 0.8 0.55
China, October 2007.
𝑊8 (𝜇m) 3 60 23.5 62.5
[8] S. Barra, A. Dendouga, S. Kouda, and N. Bouguechal, “Multi-
𝐿 8 (𝜇m) 0.18 2 0.68 0.55 Objective Genetic Algorithm optimization of CMOS oper-
ational amplifiers,” in Proceedings of the 24th International
Conference on Microelectronics (ICM ’12), pp. 1–4, Algiers,
7. Conclusion Algeria, December 2012.
[9] A. Dendouga, S. Oussalah, D. Thienpont, and A. Lounis, “Pro-
This work demonstrates the utility of an evolutionary algo- gram for the optimization of an OTA for front end electronics
rithm for automating electronic design using algorithms based on multi objective genetic algorithms,” in Proceedings
called MOGAs, which have the ability to deal with a problem of the IEEE 29th International Conference on Microelectronics
of multiobjective optimization with two or more goals and (MIEL ’14), pp. 443–446, Belgrade, Serbia, May 2014.
taking the constraints also into account. [10] P. P. Kumar and K. Duraiswamy, “An optimized device sizing of
In this paper, a program based on multiobjective genetic analog circuits using particle swarm optimization,” Journal of
algorithm has been developed for analog integrated circuits Computer Science, vol. 8, no. 6, pp. 930–935, 2012.
design. The genetic algorithm and equation-based optimiza- [11] M. Kubar and J. Jakovenko, “A powerful optimization tool for
tion are combined to produce an accurate tool in order to analog integrated circuits design,” Radioengineering, vol. 22, no.
determine the device sizes in an analog circuit. A MOGAs- 3, pp. 921–931, 2013.
based approach is proposed to optimize the performances of [12] S. L. Sabat, K. S. Kumar, and S. K. Udgata, “Differential evolution
two-stage OTAs. and swarm intelligence techniques for analog circuit synthesis,”
The results prove the effectiveness of the approach in the in Proceeding of the World Congress on Nature and Biologically
analog design where the design space is too complicated to Inspired Computing (NABIC '09), pp. 469–474, Coimbatore,
be done with the classical methods within a short time. It can India, December 2009.
be concluded that the proposed MOGAs-based approach is
efficient and gives promising results for circuits design and
optimization problems.

Conflict of Interests
The authors declare that there is no conflict of interests
regarding the publication of this paper.

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