Microprocessor [ECC15101]

8085 Instructions

Addressing Modes

The microprocessor has different ways of specifying the data for the
instruction. These are called “addressing modes”.

The 8085 has four addressing modes:

Direct LDA 4000

Register
Implied CMA
Immediate MVI B, 45
Indirect LDAX B

Load the accumulator with the contents of the memory location whose
address is stored in the register pair BC.
Addressing Modes

1. Direct Addressing Modes

In this mode of addressing the address of the operand (data) is given in the instruction itself.
STA 2400 – store the content of accumulator in the 32,00,24 memory location 2400 In 02 -
Read data from the Port C.
2. Register Addressing Modes
In this mode operand is in one of the general purpose registers or accumulator.
The opcode specifies the address of the register in addition to the operation to be performed.

MOV A,B ADD B

78 80
3. Register Indirect Addressing
In this mode the address of the operand is specified by the register pair.
LXI H, 2500 load H-L pair with 2500
MOV A,M move the content of the memory location, whose address is in the H-L pair
to the accumulator.

[MOV A,M – is an example for Register Indirect Addressing Mode]

LXI H, 2500
ADD M
HLT
Addressing Modes

4. Immediate Addressing Mode

In immediate addressing mode the operand is specified with in the
instruction itself.
MVI A,05
[3E, 05] ----------- code form
ADI 06
[C6, 06]
In the instructions the 2nd byte specifies data.
5.Implicit Addressing
Instruction which operate on the content of the accumulator. Such instructions
do not require the address of the operand.
CMA
RAL - rotate the content of the accumulator left on bit through
carry.
RAR - rotate the content of the accumulator right on bit through
carry.
RLC RRC
8085 Instructions

Data Formats
In an 8-bit microprocessor, data can be represented in one of four formats:
ASCII
BCD
Signed Integer
Unsigned Integer.

–It is important to recognize that the microprocessor deals with 0’s and 1’s.It
deals with values as strings of bits.
It is the job of the user to add a meaning to these strings.

Assume the accumulator contains the following value: 0100 0001.

There are four ways of reading this value: It is an unsigned integer expressed in
binary, the equivalent decimal number would be 65.
It is a number expressed in BCD (Binary Coded Decimal) format. That would make it,
41.
It is an ASCII representation of a letter. That would make it the letter A.
It is a string of 0’s and 1’s where the 0th and the 6th bits are set to 1 while all other bits are
set to 0.
8085 Instructions

Counters and Delays

• A loop counter is set up by loading a register with a certain value.

• Then using the DCR (to decrement) and INR (to increment) the contents of the
register are updated.
• A loop is set up with a conditional jump instruction that loops back or not depending
on whether the count has reached the termination count.
Sample: For implementing a
Using a single register, one can repeat a loop
loop Using DCR instruction
for a maximum count of 255 times.
MVI C, 15H
LOOP DCR C It is possible to increase this count by using a
JNZ LOOP register pair for the loop counter instead of the
single register.

A minor problem arises in how to test for the final

count since DCX and INX do not modify the flags.

However, if the loop is looking for when the count

becomes zero, we can use a small trick by Oring the
two registers in the pair and then checking the zero
flag.
 8085 Instructions

Counters and Delays

The following is an example of a loop set up with a register pair as the loop counter.

LOOP: LXI B, 1000H

DCX B
MOV A, C
ORA B
JNZ LOOP
Delays
Each instruction passes through different combinations of Fetch, Memory
Read, and Memory Write cycles.

Knowing the combinations of cycles, one can calculate how long such an
instruction would require to complete.

The table in Appendix F of the book contains a column with the title
B/M/T.
B for Number of Bytes, M for Number of Machine Cycles, T for Number of T-
State.
 8085 Instructions

Counters and Delays

Knowing how many T-States an instruction requires, and keeping in mind that a T-
State is one clock cycle long, we can calculate the time using the following
formula:
Delay = No. of T-States / Frequency

For example a “MVI” instruction uses 7 T-States. Therefore, if the Microprocessor

is running at 2 MHz, the instruction would require 3.5 μSeconds to complete.

Delay loops
We can use a loop to produce a certain amount of time delay in a program.
The following is an example of a delay loop:
MVI C, FFH 7 T-States
LOOP DCR C 4 T-States
JNZ LOOP 10 T-States
The first instruction initializes the loop counter and is executed only once requiring only 7
T-States.
The following two instructions form a loop that requires 14 T-States to execute and is
repeated 255 times until C becomes 0.
8085 Instructions

Counters and Delays

• We need to keep in mind though that in the last iteration of the loop, the JNZ
instruction will fail and require only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total delay to get an accurate delay
calculation.
• To calculate the delay, we use the following formula:
Tdelay = TO+ TL
Tdelay= total delay
TO= delay outside the loop
TL= delay of the loop

Using these formulas, we can calculate the time delay for the previous
example:
• TO = 7 T-States Delay of the MVI instruction

• TL = (14 X 255) -3 = 3567 T-States14 T-States for the 2 instructions repeated

255 times (FF16= 25510) reduced by the 3 T-States for the final JNZ.
Counters and Delays

LXI B, 1000H 10 T-States

Using the same formula from before, we can LOOP: DCX B 6 T-States
calculate: MOV A, C 4 T-States
TO= 10 T-States ORA B 4 T-States
The delay for the LXI instruction JNZ LOOP 10 T-States

TL= (24 X 4096) -3 = 98301 T-States

24 T-States for the 4 instructions in the loop repeated
4096 times (100016= 409610) reduced by the 3 T-States
for the JNZ in the last iteration.
Nested Loops
Nested loops can be easily setup in
Assembly language by using two registers
for the two loop counters and updating
the right register in the right loop.

In the figure, the body of loop2 can be before

or after loop
Counters and Delays

Instead (or in conjunction with) Register Pairs, a nested loop structure

can be used to increase the total delay produced.

MVI B, 10H 7 T-States

LOOP2
MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States

The calculation remains the same except that it the formula must be applied
recursively to each loop.
Start with the inner loop, then plug that delay in the calculation of the outer loop.

•Delay of inner loop TO1= 7 T-States MVI C, FFH instruction

TL1= (255 X 14) -3 = 3567 T-States 14 T-States for the DCR C and JNZ instructions repeated
255 times (FF16= 25510) minus 3 for the final JNZ
8085 Instructions

Counters and Delays

Delay Calculation of Nested Loops
Delay of outer loop
TO2= 7 T-States MVI B, 10H instruction

TL1= (16 X (14 + 3574)) -3 = 57405 T-States 14 T-States for the DCR B and JNZ
instructions and 3574 T-States for loop1 repeated 16 times (1016= 1610) minus 3 for the final
JNZ.

TDelay= 7 + 57405 = 57412 T-States

Total Delay TDelay= 57412 X 0.5 μSec = 28.706 mSec

The delay can be further increased by using register pairs for each of the loop
counters in the nested loops setup.

It can also be increased by adding dummy instructions (like NOP) in the body of
the loop.
8085 Timing Diagrams

Representation of Various Control signals generated during Execution of an

Instruction.

Following Buses and Control Signals must be shown in a Timing Diagram:

Higher Order Address Bus.

Lower Address/Data bus
ALE
RD
WR
IO/M

Instruction:A000h MOV A,B

Corresponding Coding: A000h 78

8085 Timing Diagrams
8085 Timing Diagrams
8085 Timing Diagrams
8085 Timing Diagrams
8085 Timing Diagrams
Stack and Subroutines

• The stack is an area of memory identified by the

programmer for temporary storage of information.

• The stack is a LIFO (Last In First Out) structure.

• The stack normally grows backwards into memory.

In other words, the programmer defines the bottom of the stack
and the stack grows up into reducing address range.

Given that the stack grows backwards into memory, it is customary to place
the bottom of the stack at the end of memory to keep it as far away from user
programs as possible.

In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
LXI SP, FFFFH
This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
Stack and Subroutines

Saving Information to Stack

Information is saved on the stack by PUSHing it on. It is retrieved from the stack by
POPing it off.

The 8085 provides two instructions: PUSH and POP for storing information on the
stack and retrieving it back.
Both PUSH and POP work with register pairs ONLY.

PUSH INSTRUCTION
PUSH B
- Decrement SP
- Copy the contents of register B to the memory location
pointed to by SP
-Decrement SP FFFC
FFFD F3
-Copy the contents of register C to the memory location
FFFE 12
pointed to by SP SP
FFFF

B C
F3 12
Stack and Subroutines

POP INSTRUCTION

POP D

Copy the contents of the memory location pointed to by the

FFFC
SP to register E
FFFD F3
Increment SP SP
FFFE 12
Copy the contents of the memory location pointed to by the
FFFF
SP to register D
Increment SP D E
F3 12

Operation of the Stack

During pushing, the stack operates in a “decrement then store” style. The stack pointer is decremented
first, then the information is placed on the stack.

During poping, the stack operates in a “use then increment” style. The information is retrieved from the
top of the the stack and then the pointer is incremented.

The SP pointer always points to “the top of the stack”.

Stack and Subroutines

LIFO
The order of PUSHs and POPs must be opposite of each other in order to
retrieve information back into its original location.

PUSH B
PUSH D
...
POP D
POP B

The PSW Register Pair

The 8085 recognizes one additional register pair called the PSW (Program Status
Word).This register pair is made up of the Accumulator and the Flags registers.

It is possible to push the PSW onto the stack, do whatever operations are needed,
then POP it off of the stack.

The result is that the contents of the Accumulator and the status of the Flags are returned
to what they were before the operations were executed.
Stack and Subroutines

Subroutines

A subroutine is a group of instructions that will be used repeatedly in different

locations of the program

Rather than repeat the same instructions several times, they can be grouped into a
subroutine that is called from the different locations.

In Assembly language, a subroutine can exist any where in the code.

However, it is customary to place subroutines separately from the main program.

The 8085 has two instructions for dealing with subroutines.

The CALL instruction is used to redirect program execution to the subroutine.

The RTE insutruction is used to return the execution to the calling routine.
Stack and Subroutines

Subroutines
CALL INSTRUCTION

CALL 4000H
Push the address of the instruction immediately following the CALL
onto the stack
Load the program counter with the 16-bit address supplied with the FFFC
CALL instruction. PC 20 03 FFFD 03

2000 FFFE 20
RTE INSTRUCTION SP
2003 FFFF
CALL 4000
RTE

Retrieve the return address from the top of

the stack
Load the program counter with the return
address. FFFC
FFFD 03
FFFE SP
4014 … 20
4015 RTE
FFFF

D E
20 03