7/30/25, 4:00 PM Ann Can Code, So Can You.: UVM AHB Driver Example.

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UVM AHB Driver Example.

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► 2017 (4)
////////// Sequence Item //////////
class ahb_seq_item extends uvm_sequence_item; ▼ 2016 (93)
`uvm_object_utils(ahb_seq_item) ► December (5)

// Master to Slave Data Flow ► November (12)

rand logic [31:0] HADDR; ▼ October (55)
rand logic [31:0] HWDATA;
rand logic HWRITE; UVM Virtual Sequence Example.
ahb_burst_e HBURST; UVM AHB Driver Example.

// Slave to Master Data Flow UVM APB Driver Example.

logic [31:0] HRDATA; UVM PCM Driver Example.
ahb_resp_e HRESP;
AMBA 101.
// Constructor UVM Coverage.
function new (string name);
super.new(name); SystemVerilog Question.
endfunction: new Randomization.

// Constraints UVM Report.

constraint addr_for_32bit {HADDR[1:0] == 0;} UVM Test Analysis.

endclass: ahb_seq_item SystemVerilog Demystified.

UVM Configuration DB Gotchas.

////////// AHB Interface ////////// UVM Configuration DB.

interface ahb_interface; SystemVerilog 101.

// TO both Master & Slave UVM Scoreboard Methodology.

logic HCLK; UVM / System Verilog - Threads
logic RESETn; and Synchronization.

// Master to Slave UVM - Scoreboard, Checking and

logic [31:0] HADDR; Reporting.
logic [31:0] HWDATA; UVM Connections.
logic HWRITE;
ahb_burst_e HBURST; Java Data Structure - Collections.
Java Data Structure - Arrays.
// Slave to Master
logic [31:0] HRDATA; Java - Test Yourself.
ahb_resp_e HRESP; UVM 101.
logic HREADY;
NCG 101.
endinterface: ahb_interface ARM 101.
Challenges in Embedded
////////// Pipelined UVM Driver ////////// Programming.
class ahb_pipelined_driver extends uvm_driver #(ahb_seq_item); JQuery 101.
`uvm_component_utils(ahb_pipelined_driver)
AJAX 101.
// Virtual Interface HTTP 101.
virtual ahb_interface ahb_if;
XPath Selectors.

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7/30/25, 4:00 PM Ann Can Code, So Can You.: UVM AHB Driver Example.
// Constructor Selenium 101.
function new (string name, uvm_component parent);
super.new(name, parent); Selenium Jump Start.
endfunction: new GitHub with me.

// Semaphore Declaration Software Testing.

semaphore pipeline_lock = new(1); Java Gotchas.

// Run Phase Task DOM 101.

task run_phase (uvm_phase phase); OVM - Agent, Monitor, Subscriber.

@(posedge ahb_if.HRESETn); OVM - Transactions.

@(posedge ahb_if.HCLK); OVM 101 - Standard Component
Phases.
fork
do_pipelined_transfer; UVM/OVM Questions.
do_pipelined_transfer; Sorting Algorithms.
join
OOP Programming Terms.
endtask: run_phase JavaScript Good Practices.

// do_pipelined_transfer task JavaScript and CSS.

task automatic do_pipelined_transfer; JavaScript Forms.

ahb_seq_item req; Summary Comments

Timer Summary.
forever begin
pipeline_lock.get(); JavaScript Events.
seq_item_port.get(req); OVM 101 - part 2.
accept_tr(req, $time);
void'(begin_tr(req, "pipelined_driver"); OVM 101.
ahb_if.HADDR <= req.HADDR; UVM/OVM primer.
ahb_if.HWRITE <= req.HWRITE;
ahb_if.HBURST <= req.HBURST; Java Math.
@(posedge ahb_if.HCLK); Java OOP.
while(!ahb_if.HREADY == 1) begin
@(posedge ahb_if.HCLK); Java Exceptions.
end
From Git to GitHub.
// Command phase ends here
// Unlock semaphore Git 101.
pipeline_lock.put();
► September (13)
// Data phase starts here
if (req.HWRITE == 0) begin ► August (3)
@(posedge ahb_if.HCLK);
► May (5)
while(ahb_if.HREADY != 1) begin
@(posedge ahb_if.HCLK);
end
req.HRDATA = ahb_if.HRDATA;
req.HRESP = ahb_if.HRESP;
end
else begin
ahb_if.HWDATA <= req.HWDATA;
@(posedge ahb_if.HCLK);
while(ahb_if.HREADY != 1) begin
@(posedge ahb_if.HCLK);
end
req.HRESP = ahb_if.HRESP;
end
// Return the Request as Response
seq_item_port.put(req);
end_tr(req);
end
endtask: do_pipelined_transfer

endclass: ahb_pipelined_driver

////////// Pipelined Sequence //////////

class ahb_pipelined_seq extends uvm_sequence #(ahb_seq_item);
`uvm_object_utils(ahb_pipelined_seq)

logic [31:0] addr[10]; // To save addresses

int count; // To ensure that the seq does'nt complete too early

// Constructor
function new (string name);
super.new(name);

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7/30/25, 4:00 PM Ann Can Code, So Can You.: UVM AHB Driver Example.
endfunction: new

// Task body()
task body;

ahb_seq_item req;
req = ahb_seq_item::type_id::create("req", this);
use_response_handler(1); // Enable Response Handler
count = 0;

for(int i=0; i<10; i++) begin

start_item(req);
assert(req.randomize()
with {MWRITE == 1; HBURST == SINGLE; HADDR
inside {[32'h0010_1000:32'h0010_1FFC]};});
addr[i] = req.HADDR;
finish_item(req);
end

foreach (addr[i]) begin

start_item(req);
req.HADDR = addr[i];
req.HWRITE = 0;
finish_item(req);
end

// Wait till last seq item is over

wait(count == 20);
endtask: body

// This response_handler function is enabled

// to keep the sequence response FIFO empty
function void response_handler(uvm_sequence_item response);
count++;
endfunction: response_handler

endclass: ahb_pipelined_seq

Posted by Ann at 10:57 PM

Labels: medium, uvm

1 comment:

Yuri Panchul February 9, 2019 at 5:31 PM

This code is not going to work with real AHB or AHB-Lite protocol device because AHB
protocol requires HTRANS signal that shows that the transfer is valid.

In addition, it is possible to rewrite this driver without any forks or semaphores, just by
using 1 (one) @(posedge ahb_if.HCLK) instead of 7. Pipelining will be still OK (data of
previous transaction is processed at the same clock cycle as the address of a new
transaction).

All you have to do is to maintain not a single variable req, but two variables - one for
address phase and another for data phase, and doing "req_data = req_adr; req_adr = null;"
when HREADY is 1.

Something like this (I did not compile the code, but this structure works and it has no
forks or locks):

// Run Phase Task

task run_phase (uvm_phase phase);

ahb_seq_item req_adr, req_data;

@(posedge ahb_if.HRESETn);

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7/30/25, 4:00 PM Ann Can Code, So Can You.: UVM AHB Driver Example.
req_adr = null;
req_data = null;

forever begin
@(posedge ahb_if.HCLK);

if (ahb_if.HREADY)
begin
if (req_data != null)
begin
if (! req_data.HWRITE)
begin
req_data.HRDATA = ahb_if.HRDATA;
req_data.HRESP = ahb_if.HRESP;
end

// Return the Request as Response

seq_item_port.put(req_data);
end_tr(req_data);
end

// Here is important part - we shift address phase transaction to data phase

req_data = req_adr;
req_adr = null;
end

if (req_adr == null)
begin
seq_item_port.try(req_adr); // Retrieve only if available

if (req_adr != null)
begin
accept_tr(req, $time);
void'(begin_tr(req, "pipelined_driver");
end
end

// Address phase, with req_adr transaction

if (req_adr != null)
begin
ahb_if.HTRANS <= NONSEQ;
ahb_if.HADDR <= req_adr.HADDR;
ahb_if.HWRITE <= req_adr.HWRITE;
ahb_if.HBURST <= req_adr.HBURST;
end
else
begin
ahb_if.HTRANS <= IDLE;
ahb_if.HWRITE <= '0;
end

// Data phase, with req_data transaction

if (req_data != null)
ahb_if.HWDATA <= req_data.HWDATA;
end
endtask: run_phase

endclass: ahb_pipelined_driver
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