Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

TPS54628 4.5-V to 18-V Input, 6-A Synchronous Step-Down Converter With Eco-Mode™
1 Features 3 Description
1• D-CAP2™ Mode Enables Fast Transient The TPS54628 device is an adaptive on-time D-
Response CAP2 mode synchronous-buck converter. The
TPS54628 enables system designers to complete the
• Low-Output Ripple and Allows Ceramic Output suite of various end-equipment power-bus regulators
Capacitor with a cost-effective, low-component count, low-
• Wide VIN Input Voltage Range: 4.5 V to 18 V standby current solution.
• Output Voltage Range: 0.76 V to 5.5 V The main control loop for the TPS54628 uses the
• Highly Efficient Integrated FETs Optimized D-CAP2 mode control that provides a fast transient
for Lower Duty-Cycle Applications response with no external compensation
– 36 mΩ (High-Side) and 28 mΩ (Low-Side) components. The adaptive on-time control supports
seamless transition between PWM mode at higher
• High Efficiency, Less Than 10 µA at Shutdown
load conditions and Eco-Mode operation at light
• High Initial Band-Gap Reference Accuracy loads. Eco-Mode allows the TPS54628 to maintain
• Adjustable Soft Start high efficiency during lighter load conditions. The
• Prebiased Soft Start TPS54628 also has a proprietary circuit that enables
the device to adopt to both low equivalent-series-
• 650-kHz Switching Frequency (fSW) resistance (ESR) output capacitors, such as
• Cycle-by-Cycle Overcurrent Limit POSCAP or SP-CAP, and ultra-low ESR ceramic
• Auto-Skip Eco-Mode™ for High Efficiency at Light capacitors.
Load The device operates from 4.5-V to 18-V VIN input.
The output voltage can be programmed between
2 Applications 0.76 V and 5.5 V. The device also features an
• Wide Range of Applications for Low-Voltage adjustable soft-start time. The TPS54628 is available
in the 8-pin SO PowerPAD package, and designed to
Systems:
operate from –40°C to 85°C.
– Digital-TV Power Supplies
– High-Definition Blu-Ray Disc™ Players Device Information(1)
– Networking Home Terminals PART NUMBER PACKAGE BODY SIZE (NOM)

– Digital Set-Top Boxes (STBs) TPS54628 SO PowerPAD (8) 4.89 mm × 3.90 mm

(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic Load Transient Response

Vout( 50mV/div)
TPS54628

Iout( 2A/div)

Copyright © 2016, Texas Instruments Incorporated 100us/div

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 12
2 Applications ........................................................... 1 8.1 Application Information............................................ 12
3 Description ............................................................. 1 8.2 Typical Application ................................................. 12
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 15
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 16
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 16
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 16
6.2 ESD Ratings ............................................................ 4 10.3 Thermal Considerations ........................................ 17
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 18
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ....................................... 18
6.5 Electrical Characteristics – DC ................................. 5 11.2 Receiving Notification of Documentation Updates 18
6.6 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 18
7 Detailed Description .............................................. 9 11.4 Trademarks ........................................................... 18
7.1 Overview ................................................................... 9 11.5 Electrostatic Discharge Caution ............................ 18
7.2 Functional Block Diagram ......................................... 9 11.6 Glossary ................................................................ 18
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 11 Information ........................................................... 18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (April 2013) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
• Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1

2 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

5 Pin Configuration and Functions

DDA Package
8-Pin SO PowerPAD
Top View

1 EN VIN 8

EXPOSED
THERMAL PAD
2 VFB VBST 7
TPS54628

DDA

3 VREG5 HSOP8
SW 6

4 SS GND 5

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 EN I Enable input control. EN is active high and must be pulled up to enable the device.
2 VFB I Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5-V power supply output. A capacitor (typically 1 µF) must be connected to GND. VREG5 is not active
3 VREG5 O
when EN is low.
4 SS I Soft-start control. An external capacitor must be connected to GND.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
5 GND —
a single point.
6 SW O Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and SW
7 VBST O
pins. An internal diode is connected between VREG5 and VBST.
8 VIN I Input voltage supply pin.
Exposed
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
— Thermal —
GND.
Pad

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VIN, EN –0.3 20
VBST –0.3 26
VBST (10-ns transient) –0.3 28
Input voltage VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5
SW –2 20
SW (10-ns transient) –3 22
VREG5 –0.3 6.5
Output voltage V
GND –0.3 0.3
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM) ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VIN Supply input voltage 4.5 18 V
VBST –0.1 24
VBST (10-ns transient) –0.1 27
VBST (vs SW) –0.1 6
SS –0.1 5.7
Input voltage EN –0.1 18 V
VFB –0.1 5.5
SW –1.8 18
SW (10-ns transient) –3 21
GND –0.1 0.1
VO Output voltage (VREG5) –0.1 5.7 V
IO Output current (IVREG5) 0 5 mA
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

4 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

6.4 Thermal Information

TPS54628
(1) DDA
THERMAL METRIC UNIT
(SO PowerPAD)
8 PINS
RθJA Junction-to-ambient thermal resistance 43.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.4 °C/W
RθJB Junction-to-board thermal resistance 25.6 °C/W
ψJT Junction-to-top characterization parameter 7.4 °C/W
ψJB Junction-to-board characterization parameter 25.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics – DC

Over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
IVIN Operating non-switching supply current 950 1400 µA
VFB = 0.8 V
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 3 10 µA
LOGIC THRESHOLD
EN high-level input voltage EN 1.6
VEN V
EN low-level input voltage EN 0.6
REN EN pin resistance to GND VEN = 12 V 200 400 800 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
772 mV
Eco-Mode operation
TA = 25°C, VO = 1.05 V,
VFBTH VFB threshold voltage 757 765 773 mV
continuous mode operation
TA = –40 to 85°C, VO = 1.05 V,
751 765 779 mV
continuous mode operation (1)
IVFB VFB input current VFB = 0.8 V, TA = 25°C 0 ±0.15 µA
VREG5 OUTPUT
TA = 25°C, 6 V < VIN < 18 V,
VVREG5 VREG5 output voltage 5.2 5.5 5.7 V
0 < IVREG5 < 5 mA
IVREG5 Output current VIN = 6 V, VREG5 = 4 V, TA = 25°C 20 mA
VOUT DISCHARGE
RDISCHG VOUT discharge resistance EN = 0 V, SW = 0.5 V, TA = 25°C 500 800 Ω
MOSFET
High-side switch resistance 25°C, VBST – SW = 5.5 V 36
RDS(on) mΩ
Low-side switch resistance 25°C 28
CURRENT LIMIT
IOCL Current limit L out = 1.5 µH (1) 6.7 7.3 8.9 A
THERMAL SHUTDOWN
Shutdown temperature 165
TSDN Thermal shutdown threshold (1) °C
Hysteresis 35
ON-TIME TIMER CONTROL
tON ON time VIN = 12 V, VO = 1.05 V 150 ns
tOFF(MIN) Minimum OFF time TA = 25°C, VFB = 0.7 V 260 310 ns

(1) Not production tested.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

Electrical Characteristics – DC (continued)

Over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT START
SS charge current VSS = 1 V 4.2 6 7.8 µA
ISS
SS discharge current VSS = 0.5 V 1.5 3.3 mA
HICCUP AND OVERVOLTAGE PROTECTION
VOVP Output OVP threshold OVP Detect (L > H) 125%
VHICCUP Output hiccup threshold Hiccup detect (H > L) 65%
THICCUPDELAY Output hiccup delay To hiccup state 250 µs
THICCUPENDELAY Output hiccup enable delay Relative to soft-start time ×1.7
UVLO
Wake-up VREG5 voltage 3.45 3.75 4.05
UVLO UVLO threshold V
Hysteresis VREG5 voltage 0.13 0.32 0.48

6 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

6.6 Typical Characteristics

VIN = 12 V, TA = 25°C (unless otherwise noted).

1,400 10
9

Ivccsdn - Shutdown Current (µA)

1,200
8
ICC - Supply Current (µA)

1,000 7
6
800
5
600
4

400 3
2
200
1
0 0
±50 0 50 100 150 ±50 0 50 100 150
TJ Junction Temperature (ƒC) C001 TJ Junction Temperature (ƒC) C002

Figure 1. Supply Current vs Junction Temperature Figure 2. VIN Shutdown Current vs

Junction Temperature
50 0.780
VIN = 18 V
0.775
40
EN Input Current (µA)

0.770
VFB Voltage (V)

30
0.765
20
0.760

10
0.755 IO = 10 mA
Io=10mA
Io=1A
IO = 1 A
0 0.750
0 5 10 15 20 ±50 0 50 100 150
EN Input Voltage (V) C003 TJ Junction Temperature (ƒC) C012

Figure 3. EN Current vs EN Voltage Figure 4. VFB Voltage vs Junction Temperature

1.100 1.080

1.070
VOUT - Output Voltage (V)

VOUT - Output Voltage (V)

1.075
1.060

1.050 1.050

1.040
1.025
VVin=5V
IN = 5 V
1.030 IOUT = 10 mA
Io=10mA
VVin=12V
IN = 12 V

VVin=18V
IN = 18 V
Io=1A
IOUT = 1 A
1.000 1.020
0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 5 10 15 20
IOUT - Output Current (A) C004 VIN - Input Voltage (V) C005

Figure 5. 1.05-V Output Voltage vs Output Current Figure 6. 1.05-V Output Voltage vs Input Voltage

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

Typical Characteristics (continued)

VIN = 12 V, TA = 25°C (unless otherwise noted).
100 100
VIN = 12 V VIN = 12 V
90
90
80
70
80
Efficiency (%)

Efficiency (%)
60
70 50
40
60
30
Vo=1.8V
Vo=1.8V 20
50 Vo=3.3V
Vo=3.3V
10
Vo=5V Vo=5V
40 0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.001 0.01 0.1
IOUT - Output Current (A) C008 IOUT - Output Current (A) C009

Figure 7. Efficiency vs Output Current Figure 8. Light Load Efficiency vs Output Current
900 900
850
IOUT = 1 A
fsw - Switching Frequency (kHz)

800

fsw - Switching Frequency (kHz)

800
700
750
600
700
500
650 Vo=1.05V
V O = 1.05 V
400
600 Vo=1.2V
V O = 1.2 V
V O = 1.5 V
Vo=1.5V 300
550
V O = 1.8 V
Vo=1.8V
500 V 200 VVo=1.05V
O = 1.05 V
O = 2.5 V
Vo=2.5V
450 V O = 3.3 V
Vo=3.3V 100 VVo=1.8V
O = 1.8 V
V O= 5 V
Vo=5V VVo=3.3V
400 O = 3.3 V
0
0 5 10 15 20 0.0 0.1 1.0 10.0
VIN - Input Voltage (V) C010
IO - Output Current (A) C011

Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Output Current
7.00

6.00

5.00
Output Current (A)

4.00

3.00
VO=1.05V
2.00 VO=1.8V

1.00 VO=3.3V
VO=5V
0.00
-50 0 50 100
Ta Ambient Temperature (ºC) C013

Figure 11. Output Current vs Ambient Temperature

8 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

7 Detailed Description

7.1 Overview
The TPS54628 is a 6-A Eco-Mode™ synchronous step-down (buck) converter with two integrated N-channel
MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces
the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the
use of low-ESR output capacitors including ceramic and special polymer types.

7.2 Functional Block Diagram

EN EN
1
Logic
VIN

VIN
-35% + 8
HICCUP
-
VREG5
VBST
Control Logic 7
+
OV
+25% -
1 shot
SW VO
6
Ref + XCON
ON
VREG5
SS + PWM Ceramic
Capacitor
VFB
2 -
5
+ SW GND
ZC
- PGND
SGND
VREG5
3
+ SW
OCP
- PGND
SS SS VIN
PGND 4 Softstart

HICCUP
VREG5 OV Protection
SGND UVLO Logic
UVLO
TSD

REF Ref

Copyright © 2016, Texas Instruments Incorporated

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

7.3 Feature Description

7.3.1 Auto-Skip Eco-Mode™ Control
The TPS54628 is designed with Auto-Skip Eco-Mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
1 (VIN - VOUT )×VOUT
I OUT ( LL ) = ×
2 × L × fsw VIN (1)

7.3.2 Soft Start and Prebiased Soft Start

The soft-start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start-up.
The equation for the slow-start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 µA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) = =
ISS (μA) 6 (2)
The TPS54628 contains a unique circuit to prevent current from being pulled from the output during start-up if the
output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low-side FET gate driver pulses with a narrow on time. It then increments that on time on a cycle-by-
cycle basis until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal
mode operation.

7.3.3 Output Discharge Control

TPS54628 discharges the output when EN is low, or the controller is turned off by the UVLO protection. The
internal low-side MOSFET is not turned on for the output discharge operation to avoid the possibility of causing
negative voltage at the output.

7.3.4 Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. The TPS54628 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on time is set to a fixed value and the current is monitored in
the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.

10 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

Feature Description (continued)

There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall. When the VFB voltage becomes lower than 65% of the target voltage, the UVP
comparator detects it. If the undervoltage condition persists for 250 µs, the device shuts down and restarts in
hiccup mode after 7 times the SS period. When the overcurrent condition is removed, the output voltage returns
to the regulated value. This protection is non-latching.

7.3.5 Overvoltage Protection

TPS54628 detects overvoltage and undervoltage conditions by monitoring the feedback voltage (VFB). This
function is enabled after approximately 1.7 times the soft-start time. When the feedback voltage becomes higher
than 125% of the target voltage, the OVP comparator output goes high and both the high-side MOSFET driver
and the low-side MOSFET driver turn off. This function is non-latch operation.

7.3.6 UVLO Protection

Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54628 is shut off. This protection is non-latching.

7.3.7 Thermal Shutdown

TPS54628 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.

7.4 Device Functional Modes

7.4.1 PWM Operation
The main control loop of the TPS54628 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the ESR-
induced output ripple from D-CAP2™ mode control.

7.4.2 PWM Frequency and Adaptive On-Time Control

TPS54628 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54628 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54628 is designed to provide up to a 6-A output current from an input voltage source ranging from 4.5 V
to 18 V. The output voltage is configurable from 0.76 V to 5.5 V. A simplified design procedure for a 1.05-V
output is shown in Figure 12.

8.2 Typical Application

U1
TPS54628DDA

Copyright © 2016, Texas Instruments Incorporated

Figure 12. Simplified Application Schematic Example

8.2.1 Design Requirements

To begin the design process, the user must know the following application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
æ ö
V = 0.765 x çç1 + R1÷÷
OUT çè ÷
R2 ø (3)

12 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

Typical Application (continued)

To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.

8.2.2.2 Output Filter Selection

The output filter used with the TPS54628 is an LC circuit. This LC filter has double pole at Equation 4.
1
F =
P 2p L x COUT
OUT (4)
At low frequencies, the overall loop gain is set by the output setpoint resistor divider network and the internal
gain of the TPS54628. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero, but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, use the
values recommended in Table 1.

Table 1. Recommended Component Values

OUTPUT C4 (pF) (1) L1 (µH) C8 + C9 (µF)
VOLTAGE R1 (kΩ) R2 (kΩ)
(V) MIN TYP MAX MIN TYP MAX MIN MAX

1 6.81 22.1 5 150 220 1 1.5 4.7 22 68

1.05 8.25 22.1 5 150 220 1 1.5 4.7 22 68
1.2 12.7 22.1 5 100 1 1.5 4.7 22 68
1.5 21.5 22.1 5 68 1 1.5 4.7 22 68
1.8 30.1 22.1 5 22 1.2 1.5 4.7 22 68
2.5 49.9 22.1 5 22 1.5 2.2 4.7 22 68
3.3 73.2 22.1 2 22 1.8 2.2 4.7 22 68
5 124 22.1 2 22 2.2 3.3 4.7 22 68

(1) Optional

Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feedforward capacitor (C4) in parallel
with R1. The feedforward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (5)
I
lpp
I =I +
Ipeak O 2 (6)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (7)
For this design example, the calculated peak current is 6.51 A and the calculated RMS current is 6.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.6 A and an RMS current rating of
11 A.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

The capacitor value and ESR determines the amount of output voltage ripple. The TPS54628 is intended for use
with ceramic or other low-ESR capacitors. TI recommends the value range from 22 µF to 68 µF. Use Equation 8
to determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(8)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.

8.2.2.3 Input Capacitor Selection

The TPS54628 requires an input decoupling capacitor and a bulk capacitor is required depending on the
application. TI recommends using a ceramic capacitor over 10 µF for the decoupling capacitor. An additional
0.1-µF capacitor (C3) from pin 8 to ground is optional to provide additional high-frequency filtering. The capacitor
voltage rating must be greater than the maximum input voltage.

8.2.2.4 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends using a ceramic capacitor.

8.2.2.5 VREG5 Capacitor Selection

A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI
recommends using a ceramic capacitor.

14 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

8.2.3 Application Curves

Vout( 50mV/div)
EN(10V/div)

Iout( 2A/div) VREG5(5V/div)

Vout(0.5V/div)

100us/div 1ms/div

Figure 13. 1.05-V Load Transient Response Figure 14. Start-Up Waveform

Vo=1.05V Vo(10mV/div) VO = 50 mV / div (-950 mV dc offset)

SW = 10 V / div

SW( 5V/div)

400ns/div

Time = 1 µsec / div

(IO = 6 A) (IO = 30 mA)
Figure 15. Voltage Ripple at Output Figure 16. DCM Voltage Ripple at
Output

Vo=1.05V VIN(50mV/div)

SW( 5V/div)

400ns/div

(IO = 6 A)
Figure 17. Voltage Ripple at Input

9 Power Supply Recommendations

The input voltage range is from 4.5 V to 18 V. The input power supply and the input capacitors must be placed
as close to the device as possible to minimize the impedance of the power-supply line.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

10 Layout

10.1 Layout Guidelines

The following lists the grounding and PCB circuit layout considerations:
1. The TPS54628 can supply large load currents up to 6 A, so heat dissipation may be a concern. The top-side
area adjacent to the TPS54628 must be filled with ground as much as possible to dissipate heat.
2. The bottom-side area directly below the IC must a dedicated ground area. It must be directly connected to
the thermal pad of the device using vias as shown. The ground area must be as large as practical. Additional
internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor must be placed near the device, and connected PGND.
11. Output capacitor must be connected to a broad pattern of the PGND.
12. Voltage feedback loop must be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND must be as broad as possible.
16. VIN Capacitor must be placed as near as possible to the device.

10.2 Layout Example

VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR

TO ENABLE EN VIN
CONTROL BOOST
FEEDBACK
RESISTORS VFB VBST CAPACITOR

VREG5 SW
BIAS SS GND
OUTPUT
INDUCTOR
VOUT
CAP
SLOW
START
CAP
EXPOSED
THERMAL PAD
Connection to
AREA OUTPUT
POWER GROUND FILTER
on internal or CAPACITOR
bottom layer

ANALOG
GROUND
TRACE POWER GROUND

VIA to Ground Plane

Figure 18. PCB Layout
16 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 TPS54628
www.ti.com SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016

10.3 Thermal Considerations

This 8-pin SO PowerPAD package incorporates an exposed thermal pad that is designed to be directly to an
external heat sink. The thermal pad must be soldered directly to the printed-board (PCB). After soldering, the
PCB can be used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be
attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004).
The exposed thermal pad dimensions for this package are shown in Figure 19.

Figure 19. Thermal Pad Dimensions

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS54628
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016 www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• PowerPAD™ Made Easy (SLMA004)
• TPS54628EVM-052, 6-A, Regulator Evaluation Module (SLVU888)

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
D-CAP2, Eco-Mode, E2E are trademarks of Texas Instruments.
Blu-Ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: TPS54628

 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPS54628DDA Active Production SO PowerPAD 75 | TUBE Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 150 54628
(DDA) | 8
TPS54628DDA.A Active Production SO PowerPAD 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 150 54628
(DDA) | 8
TPS54628DDAR Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 150 54628
(DDA) | 8
TPS54628DDAR.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 150 54628
(DDA) | 8

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jun-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54628DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jun-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54628DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jun-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54628DDA DDA HSOIC 8 75 508 7.77 2540 NA
TPS54628DDA DDA HSOIC 8 75 517 7.87 635 4.25
TPS54628DDA.A DDA HSOIC 8 75 517 7.87 635 4.25
TPS54628DDA.A DDA HSOIC 8 75 508 7.77 2540 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated