Systematic Roadmap for Embedded Computer
Architecture
Phase 1 – Memory Fundamentals (Weeks 1–4)
Goal: Build strong foundations in memory + move into embedded-specific memory usage.
1. Classical Basics
- Memory hierarchy: registers → cache → RAM → Flash → external memory.
- Direct-mapped, set-associative, fully-associative caches.
- Virtual vs physical memory.
Resource: Patterson & Hennessy (Computer Organization and Design, ARM edition).
2. Embedded Memory Management
- STM32 memory map: Flash, SRAM, peripheral address space.
- Linker scripts: how .text, .data, .bss, .heap, .stack are placed.
- Stack frames: how function calls + interrupts use the stack.
- Memory Protection Unit (MPU) vs Memory Management Unit (MMU).
Projects:
- Modify STM32 linker script → place variables in specific memory regions.
- Write a small program showing stack growth during nested calls + interrupts.
Phase 2 – Advanced Peripherals & Interconnects (Weeks 5–8)
Goal: Go beyond GPIO/SPI/I²C into system-level bus & peripheral interactions.
1. Bus Architectures
- AMBA family: AXI, AHB, APB.
- How peripherals connect to memory/CPU.
- DMA and bus arbitration (CPU vs DMA).
2. Peripheral Interfaces at System Level
- Memory-mapped I/O vs IO-mapped I/O (you already know 8255/8259 → now focus on ARM’s
AMBA).
- Performance impact of bus contention.
Projects:
- Implement a DMA-based SPI transfer. Measure CPU load with and without DMA.
- Draw STM32 bus matrix map and analyze which peripherals share the same bus.
Phase 3 – Interrupts (Weeks 9–10)
Goal: Move from “what an interrupt is” → “how it’s managed in depth.”
1. Advanced Interrupt Controllers
- NVIC (Nested Vectored Interrupt Controller).
- Interrupt priorities, nesting, latency.
- Context saving: how CPU saves registers on stack during an ISR.
2. Advanced Concepts
- Vector tables in Flash vs RAM relocation.
- ARM GIC (Generic Interrupt Controller) for Cortex-A multicore systems.
Projects:
- Configure STM32 with nested interrupts (e.g., USART interrupt pre-empted by a timer interrupt).
- Measure ISR latency using GPIO toggles + logic analyzer/oscilloscope.
Phase 4 – RTOS Memory & Scheduling (Weeks 11–16)
Goal: Combine basics (what an RTOS is) with internals (how memory is managed).
1. RTOS Basics
- Tasks, scheduling policies, context switching.
- Task stacks and their memory requirements.
2. RTOS Internals (Advanced)
- FreeRTOS heap allocators (heap_1–heap_5).
- MPU-based task isolation.
- Context switching: saving/restoring registers + PC + SP.
Projects:
- Write a FreeRTOS application with 3 tasks using different heap allocators → compare RAM
usage.
- Enable MPU in FreeRTOS, isolate task stacks → try an illegal access, watch system trap it.
- Implement your own simple round-robin scheduler (no RTOS).
Phase 5 – OS & Embedded Linux (Weeks 17–22)
Goal: Bridge the gap from RTOS to embedded Linux (Cortex-A class).
1. OS Memory Management (Basics)
- Virtual memory, paging, page tables.
- Address translation.
2. Embedded Linux
- Device tree: how memory & peripherals are described.
- Writing kernel modules → memory-mapped drivers.
- MMU and page table setup in ARMv7/ARMv8.
Projects:
- Run Linux on a Raspberry Pi or QEMU.
- Write a kernel module that memory-maps a hardware register to user space.
- Explore /proc/[pid]/maps → see how Linux manages process memory.
Phase 6 – Capstone Projects (Weeks 23–28)
Goal: Integrate all concepts into system-level embedded projects.
- Build a custom memory allocator (malloc/free) for STM32.
- Implement a bare-metal bootloader (reset vector → relocate vector table → jump to app).
- Run FreeRTOS + DMA peripherals → analyze bus contention and memory usage.
- Write a Linux kernel driver for a peripheral (using memory-mapped I/O).
Final Flow:
1. Memory basics (both paths)
2. Peripherals (second path)
3. Interrupts (second path)
4. RTOS (both paths)
5. OS/Linux (both paths)
6. Capstone projects (second path)
Roadmap Flowchart
