Preliminary Data Sheet No.
PD-6043/PD-6044-H
IR2101/IR2102
HIGH AND LOW SIDE DRIVER
Features Product Summary
• Floating channel designed for bootstrap operation
Fully operational to +600V
VOFFSET 600V max.
Tolerant to negative transient voltage
dV/dt immune
IO+/- 100 mA / 210 mA
• Gate drive supply range from 10 to 20V
VOUT 10 - 20V
• Undervoltage lockout
• 5V Schmitt-triggered input logic ton/off (typ.) 130 & 90 ns
• Matched propagation delay for both channels
• Outputs in phase with inputs Delay Matching 30 ns
Description
Packages
The IR2101/IR2102 is a high voltage, high speed
power MOSFET and IGBT driver with independent
high and low side referenced output channels. Pro-
prietary HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. The logic
input is compatible with standard CMOS or LSTTL out-
puts. The output drivers feature a high pulse current
buffer stage designed for minimum driver cross-con-
duction. The floating channel can be used to drive an
N-channel power MOSFET or IGBT in the high side
configuration which operates up to 600 volts.
Typical Connection
up to 600V
VCC
VCC VB
HIN HIN HO
LIN LIN VS TO
LOAD
COM LO
IR2102 up to 600V
IR2101 V CC
VCC VB
HIN HIN HO
LIN LIN VS TO
LOAD
COM LO
IR2101/IR2102
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High Side Floating Supply Voltage -0.3 625
VS High Side Floating Supply Offset Voltage VB - 25 VB + 0.3
VHO High Side Floating Output Voltage V S - 0.3 VB + 0.3
V
VCC Low Side and Logic Fixed Supply Voltage -0.3 25
VLO Low Side Output Voltage -0.3 VCC + 0.3
VIN Logic Input Voltage (HIN & LIN) -0.3 VCC + 0.3
dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns
PD Package Power Dissipation @ TA ≤ +25°C (8 Lead DIP) — 1.0
W
(8 Lead SOIC) — 0.625
RθJA Thermal Resistance, Junction to Ambient (8 Lead DIP) — 125
°C/W
(8 Lead SOIC) — 200
TJ Junction Temperature — 150
TS Storage Temperature -55 150 °C
TL Lead Temperature (Soldering, 10 seconds) — 300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
VB High Side Floating Supply Absolute Voltage VS + 10 VS + 20
VS High Side Floating Supply Offset Voltage Note 1 600
VHO High Side Floating Output Voltage VS VB
V
VCC Low Side and Logic Fixed Supply Voltage 10 20
VLO Low Side Output Voltage 0 VCC
VIN Logic Input Voltage (HIN & LIN) (IR2101) & (HIN & LIN) (IR2102) 0 VCC
TA Ambient Temperature -40 125 °C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS.
2
IR2101/IR2102
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, C L = 1000 pF and TA = 25°C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-On Propagation Delay — 130 200 VS = 0V
toff Turn-Off Propagation Delay — 90 200 VS = 600V
tr Turn-On Rise Time — 100 150 ns
tf Turn-Off Fall Time — 50 80
MT Delay Matching, HS & LS Turn-On/Off — 30 —
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN , VTH and IIN parameters are referenced to
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “1” Input Voltage (IR2101)
2.7 — — VCC = 10V to 20V
Logic “0” Input Voltage (IR2102)
V
VIL Logic “0” Input Voltage (IR2101)
— — 0.8 VCC = 10V to 20V
Logic “1” Input Voltage (IR2102)
VOH High Level Output Voltage, VBIAS - VO — — 100 IO = 0A
mV
VOL Low Level Output Voltage, VO — — 100 IO = 0A
ILK Offset Supply Leakage Current — — 50 VB = VS = 600V
IQBS Quiescent VBS Supply Current — 20 50 VIN = 0V or 5V
IQCC Quiescent VCC Supply Current — 140 240 VIN = 0V or 5V
IIN+ Logic “1” Input Bias Current µA VIN = 5V (IR2101)
— 20 40
VIN = 0V (IR2102)
IIN- Logic “0” Input Bias Current VIN = 0V (IR2101)
— — 1.0
VIN = 5V (IR2102)
VCCUV+ VCC Supply Undervoltage Positive Going 8.3 8.9 9.5
Threshold
V
VCCUV- VCC Supply Undervoltage Negative Going 7.5 8.2 8.6
Threshold
IO+ Output High Short Circuit Pulsed Current 100 125 — VO = 0V, VIN = 5V
PW ≤ 10 µs
mA
IO- Output Low Short Circuit Pulsed Current 210 250 — VO = 15V, VIN = 0V
PW ≤ 10 µs
3
IR2101/IR2102
Functional Block Diagram
VB
Q
HV
LEVEL PULSE R HO
SHIFT
FILTER S
HIN
PULSE VS
GEN
UV
DETECT VCC
LIN
LO
COM
IR2101/IR2101S
VB
Q
HV
v cc LEVEL
SHIFT
PULSE R HO
FILTER S
HIN
PULSE VS
GEN
UV
vcc DETECT VCC
LIN
LO
COM
IR2102/IR2102S
4
IR2101/IR2102
Lead Definitions
Symbol Description
HIN Logic input for high side gate driver output (HO), in phase (IR2101)
HIN Logic input for high side gate driver output (HO), out of phase (IR2102)
LIN Logic input for low side gate driver output (LO), in phase (IR2101)
LIN Logic input for low side gate driver output (LO), out of phase (IR2102)
VB High side floating supply
HO High side gate drive output
VS High side floating supply return
VCC Low side and logic fixed supply
LO Low side gate drive output
COM Low side return
Lead Assignments IR2101
8 Lead DIP 8 Lead SOIC
IR2101 IR2101S
1 14 1 14
2 VCC 13 2 VCC 13
3 HIN VB 12 3 HIN VB 12
4 LIN HO 11 4 LIN HO 11
5 COM VS 10 5 COM VS 10
6 LO 9 6 LO 9
7 8 7 8
14 Lead DIP 14 Lead SOIC
IR2101P1 IR2101S1
5
IR2101/IR2102
Lead Assignments IR2102
8 Lead DIP 8 Lead SOIC
IR2102 IR2102S
1 14 1 14
2 VCC 13 2 VCC 13
3 HIN VB 12 3 HIN VB 12
4 LIN HO 11 4 LIN HO 11
5 COM VS 10 5 COM VS 10
6 LO 9 6 LO 9
7 8 7 8
14 Lead DIP 14 Lead SOIC
IR2102P1 IR2102S1
6
IR2101/IR2102
Device Information
Process & Design Rule HVDCMOS 4.0 µm
Transistor Count 168
Die Size 67 X 91 X 26 (mil)
Die Outline
Thickness of Gate Oxide 800Å
Connections Material Poly Silicon
First Width 4 µm
Layer Spacing 6 µm
Thickness 5000Å
Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 9 µm
Thickness 20,000Å
Contact Hole Dimension 5 µm X 5 µm
Insulation Layer Material PSG (SiO2)
Thickness 1.5 µm
Passivation Material PSG (SiO2)
Thickness 1.5 µm
Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic
Material Au (1.0 mil / 1.3 mil)
Leadframe Material Cu
Die Area Ag
Lead Plating Pb : Sn (37 : 63)
Package Types 8 Lead PDIP / SO-8
Materials EME6300 / MP150 / MP190
Remarks:
7
IR2101/IR2102
01-3003 01
8 Lead PDIP
01-0021 08
SO-8
8
IR2101/IR2102
01-3002 03
14 Lead PDIP
01-3063 00
14 Lead SOIC (narrow body) body)
9
IR2101/IR2102
HIN HIN
LIN LIN
50% 50%
HIN
LIN
HIN 50% 50%
LIN
HO ton tr toff tf
LO
90% 90%
HO
Figure 1. Input/Output Timing Diagram LO 10% 10%
Figure 2. Switching Time Waveform Definitions
HIN
LIN 50%
50%
HIN 50% 50%
LIN
LO HO
10%
MT MT
90%
LO HO
Figure 3. Delay Matching Waveform Definitions
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2 , Tel: (905) 453-2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-Chome, Toshima-ku, Tokyo Japan Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/ Data and specifications subject to change without notice. 4/98
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