Crash Course on Computer Organization and Architecture for Placements (Based on William
Stallings - COA 8th Edition)
1. CPU Architecture
Pages: Chapter 12-14 (pp. 432-554)
• Components: ALU, Control Unit, Registers
• Instruction Cycle: Fetch → Decode → Execute → Store
• Pipelining: Improves instruction throughput; has hazards:
• Data Hazards: Data dependency
• Control Hazards: Branching issues
• RISC vs CISC:
• RISC: Fewer, simpler instructions
• CISC: Complex instructions with varied lengths
• Superscalar: Multiple pipelines to issue more than one instruction per cycle
2. Instruction Set Architecture (ISA)
Pages: Chapter 10-11 (pp. 348-428)
• Instruction Types: Data Transfer, Arithmetic, Logic, Control
• Addressing Modes: Immediate, Direct, Indirect, Register, Indexed
• Instruction Format: Opcode + Operands; variable vs fixed-length
3. Memory Hierarchy
a. Cache Memory
Pages: Chapter 4 (pp. 110-151)
• Mapping Techniques:
• Direct Mapping: One cache line per block
• Associative Mapping: Any cache line for any block
• Set-Associative: n sets of lines
• Replacement Policies: LRU, FIFO, Random
• Multi-Level Caches: L1, L2, L3 for speed and size trade-offs
b. Main Memory
Pages: Chapter 5 (pp. 158-180)
• DRAM and SRAM: DRAM slower but cheaper
• DDR SDRAM: High-performance RAM for desktops/servers
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• Error Correction: Hamming codes, ECC
c. Virtual Memory
Pages: Chapter 8 (pp. 259-299)
• Concept: Uses disk as an extension of RAM
• Paging: Divides memory into equal pages
• Page Replacement: LRU, Optimal
4. Computer Arithmetic
Pages: Chapter 9 (pp. 305-344)
• Binary Number Systems: Fixed-point, 2’s complement for signed integers
• Floating-Point Representation: IEEE 754 standard
• Operations: Addition, subtraction, multiplication, division (with overflow and underflow
handling)
5. Input/Output (I/O) Systems
Pages: Chapter 7 (pp. 217-254)
• Types of I/O:
• Programmed: CPU handles all data transfer
• Interrupt-Driven: CPU responds only when needed
• DMA (Direct Memory Access): Device interacts with memory directly
• Buses: Shared communication link (e.g., PCI, USB)
6. Control Unit Design
Pages: Chapter 15-16 (pp. 559-625)
• Hardwired Control: Uses logic circuits
• Microprogrammed Control: Uses stored instructions (microinstructions)
7. Parallel Processing and Multicore
Pages: Chapter 17-18 (pp. 628-705)
• Multicore Processors: Multiple CPU cores on a single chip
• Multithreading: Executes multiple threads in parallel
• Cache Coherence Protocols: MESI (Modified, Exclusive, Shared, Invalid)
• Symmetric Multiprocessing (SMP): Multiple processors share the same memory
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8. Evolution and Performance
Pages: Chapter 2 (pp. 16-59)
• Generations of Computers: Vacuum tubes → Transistors → ICs → VLSI
• Amdahl's Law: Performance gain from improvement = 1 / [(1 - Fraction Enhanced) + (Fraction
Enhanced / Speedup)]
• Performance Metrics:
• Clock Speed: GHz (billions of cycles/sec)
• MIPS: Million Instructions Per Second
• Benchmarks: Real-world programs to measure system performance
9. Basic Concepts
Pages: Chapter 1 (pp. 8-15)
• Computer Organization vs Architecture:
• Architecture: Attributes visible to the programmer (e.g., instruction set, addressing modes).
• Organization: Hardware implementation (e.g., control signals, data paths).
• Functional Units: Processing, Storage, I/O, Control
• Von Neumann Architecture: Shared memory for instructions and data; control unit fetches and
executes instructions sequentially.
This document provides a compact, high-utility overview for placement prep. Read the relevant chapters
in the William Stallings COA book for further examples and diagrams to reinforce these points.
