200 Verilog Interview Questions
For RTL Design, ASIC & FPGA Roles
Free Resource
Curated by Industry VLSI Experts
Compiled by Kittu K Patel
How This Document Will Help You
• Interview Focused: Every question is selected based on frequently asked inter-
views in top VLSI companies.
• Tricky and Logical: Enhances your conceptual depth and problem-solving skill.
• Coverage: Covers RTL, behavioral, gate-level coding, synthesis, FSM, timing,
blocking vs non-blocking, and testbenches.
• Structured Progression: Questions are ordered from basics to advanced logic-
building.
• Designed for Print: Color-coded sections make it easy to revise and highlight
key topics.
Use Case:
• Freshers appearing in RTL or Verification roles.
• Working engineers brushing up for job switches.
• Mentors and educators for assessments.
Verilog Interview Questions
1. What is the difference between a blocking and non-blocking assignment
in Verilog?
Give one real-time example where this difference can break your design.
2. How can you infer a latch unintentionally in Verilog?
Give code snippet that creates a latch and how to correct it.
3. Can you assign a reg to a wire?
Explain with an example and explain synthesis behavior.
4. What will be the output of this code?
reg [3:0] a = 4’b0011;
reg [3:0] b = 4’b0101;
initial begin
a = b & a;
$display("%b", a);
end
Is it synthesizable?
5. Why always @(*) is preferred over always @ (a or b or c)?
Explain the design advantage and simulator behavior.
6. What is the difference between $display, $monitor and $strobe?
Which is best used inside clocked blocks and why?
7. Design a 3-input majority gate in Verilog using only assign statements.
8. Write a Verilog code to detect a rising edge of a signal.
How will you verify this in a testbench?
9. What is the default initial value of a register and wire in Verilog simu-
lation?
10. How does Verilog handle race conditions?
Describe a situation where two always blocks conflict.
11. What are the different modeling styles in Verilog?
List advantages and disadvantages of behavioral vs structural.
12. How can you implement a tristate buffer in Verilog?
What happens when two drivers try to drive the same net?
13. Why are delays () not synthesizable in Verilog?
Where can delays still be used in RTL flow?
14. Design a priority encoder using Verilog.
What changes in logic if it’s a one-hot encoder?
15. What is the difference between ’initial’ and ’always’ block?
Can both be used in synthesis?
16. Write a testbench to verify a D Flip-Flop with asynchronous reset.
17. What is the use of ’generate’ statement in Verilog?
Give an example with parameterized module.
18. How to implement a barrel shifter in Verilog?
What’s the advantage of using shift operators?
19. Why is blocking assignment not suitable in clocked always blocks?
20. What is the synthesis difference between ’if-else’ and ’case’ ?
21. What are system tasks and system functions?
Mention 3 each with use case.
22. Explain race condition with example Verilog code.
23. Why use ’parameter’ instead of ’define’ in RTL?
24. What is a full-adder? Design it in Verilog using gates.
25. Difference between a task and a function in Verilog?
26. How will you avoid latch inference in conditional code?
27. How to synthesize a finite state machine in Verilog?
Moore vs Mealy approach difference.
28. Design a binary up-down counter in Verilog with enable.
29. How to declare a memory array in Verilog and initialize it?
30. Write a Verilog code to find parity of 8-bit data.
31. Can we have multiple always blocks in a module?
When is it useful?
32. Write synthesizable code for 2:1 mux using ternary operator.
33. What’s the difference between $random and $urandom?
34. Why is ‘posedge clk’ preferred over ‘negedge clk’ in design?
35. What is the role of synthesis tools in Verilog flow?
36. Explain metastability and how to solve it in Verilog.
37. Write Verilog code for a one-pulse generator on rising edge.
38. How does synthesis interpret ’default’ case in FSM design?
39. Why is sensitivity list important in always blocks?
40. Create a pulse stretcher module using Verilog.
41. Write Verilog code for Gray to Binary converter.
42. What are logic levels in Verilog?
Explain 0,1,x,z and their behavior.
43. Write a Verilog task to add two vectors of N-bit width.
44. Differentiate between $time, $stime and $realtime.
45. Write code for an 8-bit shift register with parallel load.
46. Why FSMs must have reset state coded properly in Verilog?
47. Explain synthesis issues with incomplete case/if statements.
48. What happens if we assign value to wire in procedural block?
49. What are the common reasons for simulation-synthesis mismatch?
50. What is meant by timing violation in Verilog simulation?
51. Write a Verilog model for traffic light controller.
52. How to implement reset synchronizer in Verilog?
53. How many flip-flops needed to store a 32-bit bus? Why?
54. What is the issue in this code?
always @ (posedge clk or posedge rst)
if (rst)
q <= 0;
q <= d;
How to fix it?
55. Design a glitch-free multiplexer in Verilog.
56. Explain difference between f inishandstop in simulation.
57. What is race-around condition in flip-flop design?
58. Write a code for 4-bit synchronous counter using alwaysf f.
59. What is meant by blocking path and non-blocking path in STA?
60. How to declare and use a parameterized module in Verilog?
61. Explain concept of setup and hold time in digital design.
51. What are logic vectors in Verilog and how are they used?
Example with reg [7:0] and signed types.
52. Explain difference between signed and unsigned arithmetic in Verilog.
53. Why should default assignments be provided in combinational blocks?
54. Write a Verilog module for clock divider by 2 and by 10.
55. What are synthesis don’ts while writing Verilog code?
List top 5 rules.
56. What is implicit state encoding in FSM? When does synthesis infer it?
57. Write Verilog code to detect rising edge of a signal.
58. Write code for simple UART transmitter in Verilog.
59. How to handle back-to-back transactions in FIFO logic?
60. Explain difference between reg and wire in Verilog.
61. Write a testbench to verify 2:1 Mux behaviorally.
62. What is the difference between blocking and non-blocking assignments?
Give example with race condition.
63. What are four-level logic values in Verilog? How are they resolved?
64. Design a frequency divider by 4 using T flip-flop in Verilog.
65. Explain the purpose of ‘timescale directive in Verilog simulation.
66. How to write a generic N-bit adder using generate block?
67. What is a latch? How does it get inferred unintentionally?
68. Explain concept of clock gating and how to code it in Verilog.
69. Write a Verilog task to reverse a bit vector.
70. Explain difference between event-based and level-based sensitivity.
71. Design a simple FSM to detect “101” sequence in serial input.
72. What are advantages of parameterized designs in Verilog?
73. Write code for priority-based arbiter in Verilog.
74. What is $display vs $monitor in Verilog simulation?
75. How does the d̀efaultn ettypeaf f ectRT Lsynthesis?
76. What happens when multiple drivers assign value to the same net?
77. Write code to implement dual-port RAM in Verilog.
78. Why clock domain crossing is risky? What methods solve it?
79. Explain concept of pipeline register stages in Verilog RTL.
80. Write Verilog code to detect glitch on a signal.
81. What is the difference between full case and parallel case?
82. Why are constant functions used in SystemVerilog but not Verilog?
83. How to implement saturation arithmetic in Verilog?
84. Write a Verilog code to compute population count of 8-bit input.
85. How to verify overflow in signed multiplication?
86. Why should asynchronous reset be synchronized in RTL?
87. Design Verilog code for modulo-5 counter.
88. Explain shift-left and shift-right operation with example.
89. Write Verilog code for pipelined multiplier.
90. Why should blocking assignments not be used in FSM always blocks?
91. What is the use of readmemhandreadmemb in Verilog?
92. What is meant by signal aliasing and how to detect it in simulation?
93. Write a Verilog task that counts number of 1s in a vector.
94. What is code bloat in Verilog RTL design?
95. Why should ‘default’ case be used in case statements?
96. Difference between synthesis and simulation delays?
97. What are blocking constructs in Verilog simulator?
98. Write a Verilog code for 3-bit Johnson counter.
99. Explain bit slicing and part-select in Verilog.
100. What are packed vs unpacked arrays in Verilog?
101. What is implicit continuous assignment? Give example.
101. What is the difference between always and initial block?
102. Explain the purpose of delays (#) in Verilog and why they’re avoided in
RTL?
103. How does tool treat unconnected output ports during synthesis?
104. Write Verilog code to implement a simple ALU with add/sub/and/or.
105. What are non-synthesizable constructs in Verilog? Name 5.
106. How to avoid race condition in clocked process in Verilog?
107. What is edge-sensitive vs level-sensitive modeling?
108. Write Verilog to count number of high bits in a 16-bit input.
109. What is bus contention? How is it handled in RTL?
110. Explain parameter vs localparam. Where is each used?
111. Write code for a 2-bit comparator using behavioral style.
112. What is tri-state logic in Verilog? Where is it used?
113. Why are generate blocks used in RTL? Give an example.
114. What is difference between ‘ifdef and ‘define macros in Verilog?
115. What are timing checks in Verilog simulation?
116. Why are memory blocks modeled using arrays?
117. What is a Verilog netlist? What does it represent?
118. How do zero-delay paths affect simulation accuracy?
119. Write a testbench to verify 4-bit up/down counter.
120. What is ’Z’ in Verilog and when does it occur?
121. Why latches are dangerous in large digital systems?
122. Explain asynchronous FIFO — how to design and test it.
123. How are finite state machines implemented in Verilog?
124. What are simulation directives? Give examples.
125. Explain how to write clean and reusable RTL modules.
126. Write a Verilog task to rotate bits left/right.
127. What is metastability? How can it be reduced in design?
128. Why is reset logic crucial in Verilog designs?
129. How do testbenches differ from synthesizable modules?
130. What is the difference between module instantiation and macro usage?
131. Write a Verilog function to compute parity of 32-bit input.
132. What is a race condition and how can it be simulated?
133. How does timing analysis differ in synthesis and simulation?
134. What is meant by RTL-level vs gate-level code?
135. Write a simple memory controller skeleton in Verilog.
136. How are blocking delays modeled in testbench?
137. What is X-propagation in simulation? How is it debugged?
138. What is the purpose of covergroups in testbench (SystemVerilog)?
139. What’s the difference between event control vs procedural delay?
140. Write Verilog code to swap nibbles in a byte.
141. How to implement a ring counter using Verilog?
142. What is inferred memory in Verilog and how is it inferred?
143. What is difference between data hazards and control hazards in pipelin-
ing?
144. How to generate test vectors using randomization in testbench?
145. Explain what happens during reset de-assertion in simulation.
146. Write a Verilog module for basic I2C controller.
147. How to calculate fanout and what’s its impact on performance?
148. What is meant by logic synthesis in ASIC flow?
149. What is glitch filtering and how is it done in Verilog?
150. Explain the difference between a monitor and checker in testbench.
151. Explain what is ’initial’ block and why it’s avoided in synthesis.
152. How to implement debouncing logic for a push button?
153. Why would you use blocking assignment inside a task?
154. Write a Verilog code to detect a rising edge on a signal.
155. Explain the term “time unit” and “time precision” in Verilog.
156. Write a Verilog code to implement clock gating.
157. What are f inish,stop and displayusedf or?
158. How to parameterize a FIFO depth and width?
159. Write Verilog to detect 1011 sequence using Mealy FSM.
160. What is meant by ‘blocking’ in a pipeline stage?
161. How are FSMs modeled differently in behavioral and structural Verilog?
162. Write a Verilog task to calculate GCD of two 4-bit numbers.
163. How to insert assertions in Verilog code for debug?
164. Difference between sensitivity list @(*) and @(posedge clk)?
165. What is the role of handshake protocols in Verilog systems?
166. Write a Verilog code for modulo-10 counter with enable and reset.
167. What are blocking vs non-blocking assignments in testbenches?
168. Explain how dual-port RAM can be designed in Verilog.
169. What is meant by combinational loop and how to avoid it?
170. Write a Verilog function to reverse bits of a byte.
171. What is clock domain crossing and how is it handled?
172. Write Verilog code for priority encoder.
173. What are setup and hold violations and how are they debugged?
174. Difference between function and task in Verilog with example.
175. Write Verilog code to implement shift register with parallel load.
176. What’s the benefit of using ‘define in testbenches?
177. Write a self-checking testbench for a 4:1 multiplexer.
178. What is difference between blocking assignments in combinational logic
and sequential?
179. Explain what happens if sensitivity list is incomplete.
180. How to avoid latch inference in conditional assignments?
181. Write Verilog code to implement 3-stage synchronizer.
182. What are asynchronous resets? Why do we sync them?
183. Write Verilog to calculate Hamming weight of 8-bit input.
184. What is meant by hazard-free logic? How to design for it?
185. Difference between testbench and verification environment?
186. Explain use of ‘timescale directive in Verilog.
187. How to create reusable RTL components with parameters?
188. Write Verilog code for signed multiplication using shift-add.
189. What is meant by “don’t care” state and how is it handled in FSM?
190. Write a Verilog module to detect glitch pulses less than 1 cycle.
191. What are simulation-only constructs and when are they useful?
192. Explain how reset synchronizer works.
193. How to apply assertions for protocol verification in Verilog?
194. Write a code to detect overflow in signed adder.
195. Difference between design intent and implementation intent in Verilog.
196. Write Verilog code to check if a number is power of two.
197. How to model dual edge-triggered flip flop?
198. Explain clock skew and its impact on sequential logic.
199. Write Verilog code for Moore machine with binary output.
200. Explain how Verilog supports modular design.
201. Final tricky one: Write a Verilog code for barrel shifter using generate
block.
