3.

6 Multiple output problems

 Many real problems involve designing a system with more than one ouput
 With three inputs, A, B, C and two outputs, F, G
 Two separate problems
 A single system : sharing gates -> economize
 Ex 3.32

F(A, B, C) = m(0, 2, 6, 7) G(A, B, C) = m(1, 3, 6, 7)

• If we map each of these and solve them separately, we obtain

F = AC + AB G = AC + AB
 Ex 3.32 (Conti.)
 The right : independent of the two circuits
 The left: the gate count is reduced by sharing the term (AB)
 Ex 3.33
F(A, B, C) = m(0, 1, 6) G(A, B, C) = m(2, 3, 6)

Independent (In the top maps) : F = AB + ABC G = AB + BC

Share (the second pair of maps) : F = AB + ABC G = AB + ABC
 Ex 3.33 (Conti.)
 Independent :
F = AB + ABC G = AB + BC (6 gates : 4 AND, 2 OR, 13 inputs)

 Share :
F = AB + ABC G = AB + ABC (5 gates : 3 AND, 2 OR, 11 inputs)
 Ex 3.34

F(A, B, C) = m(2, 3, 7) G(A, B, C) = m(4, 5, 7)

• Using essential
prime implicants
f = ab + bc
g = ab + ac

• Share the term

f = ab + abc
g = ab + abc
 Ex 3.35 F(A, B, C, D) = m(4, 5, 6, 8, 12, 13)
G(A, B, C, D) = m(0, 2, 5, 6, 7, 13, 14, 15)

• We circled each of those prime implicants that was made essential by

a red
 Ex 3.35 (Conti.)

Share the term

F = ACD + ABD + BCD

G = ABD + BC + BCD
 Ex 3.35 (Conti.)

* Share the term

F = ACD + ABD + BCD
G = ABD + BC + BCD
(20 inputs, 7 gates)

 If we had minimized the functions individually,

F = ACD + ABD + BC

G = ABD + BC + BD
(21 inputs, 8 gates)
Ex 3.40 : An example of a system with don’t cares
F(A, B, C, D) = m(2, 3, 4, 6, 9, 11, 12) + d(0, 1, 14, 15)
G(A, B, C, D) = m(2, 6, 10, 11, 12) + d(0, 1, 14, 15)

• BD: the only prime implicant made essential by a 1 that is not

shared circled
Ex 3.40 (Conti.)

• share ABD
F = BD + ABD + AD
G = AC + ABD + CD
(17 inputs, 7 gates )
 Ex 3.40 (Conti.)

• share ACD
F = BD + ACD + BD
G = AC + ABD + ACD (18 inputs, 7 gates)
Circuit Conversion Using Alternative Gate
Symbols
Alternative Gate Symbols:
 Alternate symbol for inverters:

 The following gate symbols have been derived

using DeMorgan’s Laws.

13
Design of 2-Level NAND- and NOR-Gate Circuits

Procedure for Designing a Minimum Two-Level

NAND-NAND circuit:

14
Design of 2-Level, Multiple Output Circuits
Example 4:

15
Design of 2-Level, Multiple Output Circuits
Example 4 (continued):

16
Design of 2-Level, Multiple Output Circuits
Determination of Essential Prime Implicants
for Multiple-Output Realization:

F1(a, b, c, d) = m(1, 5, 9, 13,15)

F2(a, b, c, d) = m(4, 6, 12, 14, 15)

17
Design of 2-Level, Multiple Output Circuits
F1(a, b, c, d) = m(0, 2, 4, 5, 6, 14)
F2(a, b, c, d) = m(0, 1, 4, 6, 12, 14)

18
 Code Converters
1. Design a binary code {w, x, y, z} to excess-3 code {E3, E2, E1, E0} converter.

8-4-2-1
Decimal 6-3-1-1 Excess-3 2-out-of-5 Gray
Code
Digit Code Code Code Code
(BCD)
0 0000 0000 0011 00011 0000
1 0001 0001 0100 00101 0001
2 0010 0011 0101 00110 0011
3 0011 0100 0110 01001 0010
4 0100 0101 0111 01010 0110
5 0101 0111 1000 01100 1110
6 0110 1000 1001 10001 1010
7 0111 1001 1010 10010 1011
8 1000 1011 1011 10100 1001
9 1001 1100 1100 11000 1000
2. Design excess-3 code {E3, E2, E1, E0} to a binary code {w, x, y, z} converter.

8-4-2-1
Decimal 6-3-1-1 Excess-3 2-out-of-5 Gray
Code
Digit Code Code Code Code
(BCD)
0 0000 0000 0011 00011 0000
1 0001 0001 0100 00101 0001
2 0010 0011 0101 00110 0011
3 0011 0100 0110 01001 0010
4 0100 0101 0111 01010 0110
5 0101 0111 1000 01100 1110
6 0110 1000 1001 10001 1010
7 0111 1001 1010 10010 1011
8 1000 1011 1011 10100 1001
9 1001 1100 1100 11000 1000
3. Design a logic circuit to convert a binary code {w, x, y, z} to the below
Gray BCD code {G3, G2, G1, G0}.

8-4-2-1
Decimal 6-3-1-1 Excess-3 2-out-of-5 Gray
Code
Digit Code Code Code Code
(BCD)
0 0000 0000 0011 00011 0000
1 0001 0001 0100 00101 0001
2 0010 0011 0101 00110 0011
3 0011 0100 0110 01001 0010
4 0100 0101 0111 01010 0110
5 0101 0111 1000 01100 1110
6 0110 1000 1001 10001 1010
7 0111 1001 1010 10010 1011
8 1000 1011 1011 10100 1001
9 1001 1100 1100 11000 1000
① Construct a truth table.(5)

② Find SOP equations.(5)

G3 = ∑ m(5, 6, 7, 8, 9) + ∑ d(10, 11, 12, 13, 14, 15)
G2 = ∑ m(4, 5) + ∑ d(10, 11, 12, 13, 14, 15)
G1 = ∑ m(2, 3, 4, 5, 6, 7) + ∑ d(10, 11, 12, 13, 14, 15)
G0 = ∑ m(1, 2, 7, 8) + ∑ d(10, 11, 12, 13, 14, 15)
③Simplify the equations using K-map methods.(5)
④ Design optimal 2-level AND-OR circuit to realize G3, G2, G1 and G0.
4. Design a Gray BCD code to binary code converter.
 2.1 Truth table

y
e
00
01
11
10
10
10
10
11
01
00

C3 = ∑ m(8, 9) + ∑ d(4, 5, 7, 12, 13, 15)

C2 = ∑ m(6, 10, 11, 14) + ∑ d(4, 5, 7, 12, 13, 15)
C1 = ∑ m(2, 3, 10, 11) + ∑ d(4, 5, 7, 12, 13, 15)
C0 = ∑ m(1, 2, 8, 11, 14) + ∑ d(4, 5, 7, 12, 13, 15)
2.2. K-map & 2- level AND-OR circuit