Simple Universal Asynchronous Receiver and
Transmitter (UART).
Created by:
Kirollos Rafat Foad.
Introduction:
(A) . Why UART?
UART is considered a backbone component when it comes to the
implementation of network-on-chip (NoCs) and has many other advantages for
low-to-mid speed architectures.
(B) . How does it work?
Figure(1) UART Frame.
First of all, the Tx is on IDLE state where no communication occurs, then the sense
a start bit of logic zero means start communication so it goes to START state then
start to serially feed the data out of it (parallel to serial conversion) for (5-8) cycles
depending how many data bits within’ the frame and this state called DATA and
optionally send a parity bit (not implemented here). Eventually, Goes to STOP for
the stop bit (can be a bit and a half or even 2 bits).
On the other hand, the Rx is on IDLE state waiting there, then the sense a start bit
of logic zero means start communication so it goes to START state then start to do
the exact opposite of the Tx as it collects the serially transmitted data and grouping
them altogether throughout its DATA state.
(C) . How is it constructed?
The fun part takes place here, for the sake of simplicity and in our case it
decomposes of three components:
1. Baudrate Generator: Basically a timer oriented logic where we wait for an
internal counter to hit a specific value then raise the output to 1 for very short
period of time (sometimes referred to as a tick). The key importance of such
block is that it synchronizes sampling of incoming data as in UART, there’s no
shared clock line. In simple works, it orchestrates the flow between Tx and Rx
units. There are many know baudrates but the most familiar 9600,115200.
2. Transmitter Unit (Tx): The component responsible for sending the message
(frame) we want the other side receive. The following ASMD (Arithmetic State
Machine Diagram) shows how the Tx samples and send the data frame.
Figure(2) ASMD of UART Tx.
3. Receiver Unit (Rx): The component that will take the serial data coming from the
Tx and group them to ensure things make sense. Rx also has its own ASMD.
Key important aspect is that Rx uses oversampling (16x or 13x). Oversampling is
useful when dealing with nosiy systems (real-life). for the case of 16x it means
that the Rx units samples a single value for 16 clock cycles before the next one.
This comes from the fact that no synchronizing scheme between Tx and Rx
exsits.
Figure(3) ASMD of UART Rx.
Figure(4) Oversampling Done in the Rx Side.
Objective:
A. Design a simple UART with the three components mentioned.
B. Constructing a Baudrate Generator Unit, Tx Unit and Rx unit and integrate them
for a simple test-bench.
C. Explore the schematic of the design.
(A) RTL Code:
(1) Baudrate Generator:
(2) Tx Side:
(3) Rx Side:
Note: All the implementation is an easy one to one correspondence with the
ASMD. I encourage you to try it and maybe add to it to make it better.
(B) Simple Test-benches and results:
First test:
(C) Design Schematic:
Future Work:
Make the UART more advanced with the use of FIFO buffers.
Looking forward to Building my first network-on-chip (NoC) with use of UARTs and the
round robin arbiter I have implemented before ---> check the round robin arbiter
project: RoundRobinArbiter repo (Click Here).
