Memory Interfacing Requirements
Address Decoding Techniques
• Absolute decoding/Full decoding.
• Linear decoding/Partial decoding.
Absolute decoding
Memory Map
Linear decoding
Memory Map :
Fig. 6.4.2 shows the addressing of RAM with linear decoding technique. A 15 address line, is directly
connected to the chip select signal of EPROM and after inversion it is connected to the chip select
signal of the RAM. Therefore, when the status of A 15 line is 'zero', EPROM gets selected and when
the status of A15 line is 'one' RAM gets selected. The status of the other address lines is not considered,
since those address lines are not used for generation of chip select signals.
1. Interfacing Examples
Example 6.4.1 Design memory system for the 8085 microprocessor such that it should contain 8 kbyte of EPROM
(Erasable Programmable Read Only Memory) and 8 kbyte of RAM ( Read/Write Memory).
Solution : Fig. 6.4.3 shows the desired memory system using IC 2764 (8 K) EPROM and 6264 (8 K) RAM. Memory
requires 13 address lines (A0-A12) since 213 = 8 K. The remaining address lines (A13 - A15 ) are decoded to generate
chip select signals. IC 74LS138 is used as decoder. When ( A15 - A13 ) address lines are zero, the Yo output of
decoder goes low and selects the EPROM. This means that A15 - A13 address lines must be zero to read data from
EPROM. The address lines A12 – A0 select the particular memory location in the EPROM when A15 - A13 lines are
zero. Similarly, when address lines A15 - A13 are 001, the Y1 output of decoder goes low and selects the RAM. The
Table 6.4.3 shows the memory map for the designed circuit.
Memory Map :
Example 6.4.2 Design a microprocessor system for the 8085 microprocessor such that it should
contain 16 kbyte of EPROM and 4 kbyte of RAM using two 8 kbyte EPROMs (2764) and two 2 kbyte
RAMs (6116).
Solution : Fig. 6.4.4 (See on next page) shows the desired memory system using two (8 K × 8)
EPROM and two (2 K × 8) RAMs. EPROM memory is 8 K, so it requires 13 address lines (A 12 - A0)
whereas RAM memory is 2 K, so it requires 11 address lines (A10 - Ao). The remaining higher
address lines (A15 - A13) are used to generate chip-select signals. Table 6.4.4 shows the
memory map for the designed circuit.
Memory Map :
Example 6.4.3 Design a microprocessor system for the 8085 microprocessor such that it should
contain 2 kbyte of EPROM and 2 kbyte of RAM with starting addresses 0000H and 6000H
respectively.
Solution : Fig. 6.4.5 (See on next page) shows the desired memory system using 2 kbyte EPROM
and 2 kbyte RAM. Both EPROM and RAM are 2 K, so they require 11 address lines (A 10 – A0). The
remaining hi gher address lines (A15 - A11) are used to generate chip select signals.
The chip selection logic is designed to have starting address of EPROM, 0000H and starting address
of RAM, 6000H. This is implemented by selecting EPROM only when higher address lines (A 15 - A11)
are all zero, and selecting RAM only when higher address lines (A15 - A11) are 01100 (Binary). The
Table 6.4.5 shows the memory map for the designed circuit.
Memory Map :
Example 6.4.4 Interface a 8K × 8 EPROM IC and 2K × 8 RAM IC with 8085 such that the starting
address assigned to them are 0000H and 4000H respectively using address decoder having NAND
gate and inverters.
Solution : Fig. 6.4.6 shows the desired memory system using 8 K EPROM and 2 K RAM. EPROM requires 13
address lines (A, A12). Since 213 = 8K and RAM requires 11 address lines. (A0 - A10) since 211 = 2 K. The remaining
address lines (A15 - A13) are inverted and given as NAND input to generate chip select signal. So that
when (A15 - A13) address lines are zero, EPROM is selected. The address lines A0 - A12 select the particular memory
location in the EPROM when A15 - A13 lines are zero. Similarly, when address lines A11, A12, A13, A15 are zero and
A14 is one, RAM is selected.
Memory Map :
