University of Southern Denmark

High Efficiency Three-phase Power Factor Correction Rectifier using Wide Band-Gap Devices

Kouchaki, Alireza

Publication date:
2016

Document version:
Final published version

Citation for pulished version (APA):

Kouchaki, A. (2016). High Efficiency Three-phase Power Factor Correction Rectifier using Wide Band-Gap
Devices. Maersk Mc-Kinney Moller Institute.

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 High Efficiency Three-phase Power
Factor Correction Rectifier using Wide
Band-Gap Devices

Alireza Kouchaki
SDU Electrical Engineering
The Maersk Mc-Kinney Moller Institute

University of Southern Denmark

PhD thesis
December 2016
High efficiency Three-phase Power Factor Correction using Wide-Band
Gap devices
PhD Dissertation
Author:
Alireza Kouchaki
Supervisor:
Morten Nymand

SDU Electrical Engineering

The Maersk Mc-Kinney Moller Institute
University of Southern Denmark,
Campusvej 55,
DK-5230, Odense M,
Denmark

Website: http://www.sdu.dk/mmmi
Telephone: +45 65 50 35 41
Fax: +45 66 15 76 97

Publishing date: August 2016

Classification: Public

Edition 1st

Note: This thesis is submitted in partial fulfillment of the requirements for

obtaining the PhD degree at the University of Southern Denmark.

Copyright: Alireza Kouchaki, 2016

ii
 DedicatedtomywifeFarideh
forherendlessloveandsupport
&
tomypricelessparents.

iii
Preface
This thesis presents the work that author has carried out at faculty of Engineering, University
of Southern Denmark. This PhD project has started since December 2013 and finished in
November 2016. The thesis is submitted in partial fulfilment of the requirements for
obtaining the PhD degree. The general structure of this thesis is based on the published papers
that author has done during the PhD program.
This project is part of the Intelligent Efficient Power Electronics (IEPE) research center. IEPE
is a strategic research center between three universities- University of Southern Denmark,
Aalborg University, and Technical University of Denmark- and four Danish leading high
technology companies- Danfoss Drives, Grundfos A/S, KK Electronics, and Vestas. The
main objectives of IEPE are new hardware design methods, new device technologies,
increasing the conversion efficiency of the power electronics converters. Being part of the big
and sophisticated project such as IEPE gave the author this opportunity to start a constructive
collaboration with companies in line with the objectives of the project in Denmark, especially
Danfoss Drives A/S. The collaboration which has been conducted during the PhD work under
IEPE agreement has led to valuable technical achievements and personal experiences.
This specific PhD project was part of the platform demonstrator known as a three-phase
adjustable speed drives for motor and pumps which was led by Danfoss Drives A/S. As a
result, the project was productively connected to the activities at Danfoss Drives to reach to
the main goal of the work package. The main goal is connecting the power factor correction
rectifier to the variable speed drive in kW range using wide-band gap devices. Therefore, part
of the project as a plan was conducted in Danfoss Drives laboratory. In this regard, Danfoss
Drives A/S cooperation was outstanding throughout the last 9 months of the project. Author
would like to thank Danfoss Drives for their support, especially from Niels Gade, Andreas
Aupke, Radu Lazar, Marian Lungeanu, Marco Zuccherato, and many others from Danfoss
that gave the author lots of thoughts and technical tips.

iv
Acknowledgment
I would like to express my deepest gratitude to my supervisor Morten Nymand that gave me a
great opportunity to be part of IEPE project and his group. Thanks to him for his support,
expert guidance, and his understanding. Many thanks to Dr. Jacob L. Pedersen for his support
during this project.
I owe a great debt of gratitude to Radu Lazar from Danfoss Drives A/S. His support, his
knowledge, and his impressive delicacy and skill were definitely a key for finishing this
project. Working with Radu not only improved my technical understanding but also taught
me to be always hopeful and trying to do the best.
I would also like to present my gratitude to Prof. Stephen Dodds for his precious time and his
valuable comments on my thesis.
I am very thankful to have a good working environment and would like to thank all my
colleagues and friends at SDU. I would also like to give my special appreciation to all the
former and present colleagues at the Maersk Mc-Kinney Moller Institute especially to Rakesh
Ramachandran, Fazel Taeed, Ishtiyaq Ahmed Makda, and Karsten H. Andersen.
My special thanks to Jesper Nielsen for helping me with PCB and his great effort to realize
the hardware prototypes of the converter.
My colleague and my wife, Farideh Javidi! Without your support, your understanding, your
sacrifices and your love I would never be able to finish this work. Thank you for being with
me and giving me the energy to be the best.
And finally, I would like to thank all my family members and friends, too numerous to name,
for their encouragement and great support, without whom the successful completion of this
thesis would not have been possible.
I would like to thank my incredible parents for giving me their endless love, by my mother
language, Persian:

Ϟ߮Ξ৅΋άໆଘΫ̯߮Ϣଌ΋଒ΧϪর߮ଶॷ̵୓̵̫୆΋߮Ώϡ߮Ζশ୓̶ਗඟࢂϜΧ߮Ώϩϡหάඵෆ̵߮ωΧ߮Ώ ߰ΨҤΧϪরϢૼΫ߮Ϥ঍భ߮ΝϦૡঙϩϦ૙ࣂൕঙ଒ ϡ΋ϩ΋඼່ί̢߮ণϟৣ߮Νέ΋άන෤঳భ߮ϠϩΫΨ৮

 ΨϰণΫ

v
Abstract
Improving the conversion efficiency of power factor correction (PFC) rectifiers has become
compelling due to their wide applications such as adjustable speed drives, uninterruptible
power supplies (UPS), and battery chargers for electric vehicles (EVs). The attention to PFCs
has increased even more since grid regulations have become stricter in terms of injected
harmonic and power quality. Therefore, improving the efficiency and the power quality of
PFCs are the main objectives of this PhD work.
New wide band gap (WBG) power switches have better switching characteristics in
comparison with silicon power devices. Therefore, the PFC switching frequency using WBG
devices can potentially be increased. This advantage helps the reactive components to be
reduced in size. However, it also brings challenges such as identifying a proper material for
inductive components that has lower loss and layout design that has lower parasitic elements.
To fulfill the grid regulations (e.g. IEEE-519) high order filters are normally used. Achieving
an optimum filter design is vital for having an efficient converter. Reducing low frequency
harmonics can improve both the efficiency and also the power quality. Therefore, current
controllers are also important to be investigated in this project.
In this PhD research work, a comprehensive design of a two-level three-phase PFC rectifier
using silicon-carbide (SiC) switches to achieve high efficiency is presented. The work is
divided into two main parts: 1) Optimum hardware design using WBG devices to improve the
conversion efficiency and 2) Identifying the impact on the efficiency by current controller.
Part 1 is presented in Chapter 3. The converter topology is a two-level bidirectional boost
voltage source converter (VSC). SiC devices (i.e. MOSFET and diode) are used for designing
the converter. An analytical method for choosing the filter parameters to achieve an optimum
design is presented. The method is based on the working principle of the converter. It focuses
on analyzing the converter current and voltage for generalizing the filter design. The
switching frequency which leads to the maximum converter efficiency is analyzed and
selected. According to the selected switching frequency, an optimum LCL filter is designed
and the layout is optimized for a 5 kW three-phase PFC using SiC MOSFETs.
The second part is presented in Chapter 4. It is focused on current controller and its impact on
the efficiency. Two types of current controllers are studied: PI current controller in the
rotational reference frame and proportional-resonant (PR) current controller in the stationary
reference frame. For the PR controller, harmonic compensation is employed to improve the
power quality. To have similar harmonic performance the PI controller needs larger filter in
comparison with the PR controller. This eventually ends up with lower efficiency of the
converter with the PI current controller.
In this thesis, two sets of experiments are carried out:
x Verification of the designed filter and the controllers performance in Chapter 3 and
Chapter 4, respectively;

vi
 x Measurement and comparison of the converter efficiency for two types of controllers.
The highest efficiency is achieved at 50% of nominal load for the PR current controller. The
measured efficiency is 99.1% at 50% of nominal load and 98.95% at full load. The converter
with the PR controller is more efficient than the converter with the PI controller at low load.

vii
Resumé
Det er blevet interessant at optimere konverterings effektiviteten af Power factor Controllere
(PFC) pga. deres store udbredelse inden for motordrives, nødstrømsanlæg (UPS) og
batteriladere til el biler (EVs). Der er øget fokus på PFCere på grund af strengere regler for
ledningsbåret harmonisk støj og strømkvalitet på lysnettet (Grid). Derfor er det primære mål
med denne PhD at øge effektiviteten og strømkvalitet.
Pga. switching karakteristikken på de ny wide band gap (WBG) halvleder komponenter, kan
switching frekvensen øges i forhold til de traditionelle silicium (Si) baserede PFCere. Den
øgede switch frekvens muliggør design af mindre reaktive komponenter. Dette medfører også
nye udfordringer så som at finde egnede materialer til de induktive komponenter som har
lavere tab og lave et print layout med minimal parasitiske elementer. For at opfylde
regulativerne for lysnettet (f.eks. IEEE-519) benyttes traditionelt højere ordens filtre. At opnå
et optimalt filter design er vitalt for at have en effektiv konverter. Reduktion af lavfrekvent
harmonisk støj kan både forbedre effektiviteten og strøm kvaliteten. Derfor er strøm
kontrollerer også vigtige og vil blive undersøgt i dette projekt.
I denne PhD afhandling bliver et omfattende design af en højeffektiv two-level 3 faset PCF
som benytter siliciumkarbid (SiC) switching komponenter præsenteret. Den er opdelt i to
hoveddele. 1: Optimal hardware design ved brug af WBG, for at forbedre
konverteringseffektiviteten. Og 2: Identificere strømkontrollerens indflydelse på
konverteringseffektiviteten.
Første del bliver præsenteret i kapitel 3. Konverterens topologi er en two-level bidirectional
boost voltage source converter (VSC). Der benyttes SiC baserede halvleder komponenter
(MOSFET og diode). Der præsenteres en analytisk metode til at udvælge filterparametre for
at opnå et optimalt design. Metoden er baseret på konverterens virkemåde. Den fokuserer på
analysen af konverterens strøm og spænding, for at generalisere filterdesignet. Switching-
frekvensen som medfører den maksimale konverteringseffektivitet bliver analyseret og valgt.
På baggrund af den valgte switching frekvens bliver et optimalt LCL filter designe og layoutet
bliver optimeret til en 5kW 3 faset PFC som anvender SiC MOSFETs.
Anden del bliver præsenteret i kapitel 4. Her bliver der fokuseret på strømkontrollens
indflydelse på effektiviteten. Der bliver undersøgt to forskellige typer kontrollerer:
Proportional-Integral (PI) strømkontroller i det roterende reference system og proportional-
resonans (PR) strømkontroller i det faste reference system. For PR kontrolleren
implementeres harmonisk kompensering for at forbedre strømkvaliteten. Når PI kontrolleren
benyttes skal konverteren have et større filter end når PR kontrolleren benyttes for at op når
samme harmoniske egenskaber. Dette medfører at koncerten har en lavere effektivitet end
med PI kontrolleren.
I denne afhandling er der blevet udført to eksperimenter:
x Verifikation af det designede filter (kapitel 3) og kontrollerens ydeevne (kapitel 4).

viii
 x Måling og sammenligning af konverterens effektivitet med de to typer kontrollere.
Den højeste effektivitet er målt ved 50% af den nominelle belastning med PR
kontrolleren.
Den målte effektivitet er 99,1% ved 50% belastning og 98,95% ved fuld belastning.
Konverteren med PR kontroller er mere effektiv ved lav belastning end konverteren med PI
kontroller.

ix
Contents

High efficiency Three-phase Power Factor Correction using Wide-Band Gap devices ............ ii
Preface ....................................................................................................................................... iv
Acknowledgment ....................................................................................................................... v
Abstract ..................................................................................................................................... vi
Resumé ....................................................................................................................................viii
Contents ..................................................................................................................................... x
List of figures ..........................................................................................................................xiii
List of Tables ........................................................................................................................... xv
Abbreviations .......................................................................................................................... xvi
Nomenclature ......................................................................................................................... xvii
1. Introduction......................................................................................................................... 1
1.1. Background and Motivation ........................................................................................ 1
1.2. Project objectives and Contributions ........................................................................... 2
1.2.1. Research objectives and challenges ..................................................................... 2
1.2.2. Contributions ........................................................................................................ 3
1.3. Thesis overview ........................................................................................................... 4
1.4. List of publications ...................................................................................................... 4
2. State of the art ..................................................................................................................... 7
2.1. Three-phase voltage source converters ....................................................................... 7
2.2. Optimization on component level: inductor and core material ................................... 9
2.3. Filter design ............................................................................................................... 11
2.4. Summary ................................................................................................................... 12
3. Two-Level Three-phase Power Factor Correction Rectifier ............................................ 15
3.1. Introduction ............................................................................................................... 15
3.2. System description..................................................................................................... 15
3.3. Filter design ............................................................................................................... 16
3.3.1. Converter-side inductor...................................................................................... 17
3.3.2. Filter capacitor ................................................................................................... 21
3.3.3. Damping ............................................................................................................. 23

x
 3.3.4. Grid-side inductor .............................................................................................. 24
3.3.5. Filter comparison ............................................................................................... 26
3.4. Layout design ............................................................................................................ 27
3.5. DC link capacitor....................................................................................................... 27
3.6. Loss distribution ........................................................................................................ 28
3.6.1. Inductor loss ....................................................................................................... 28
3.6.2. Switching loss .................................................................................................... 29
3.7. Selection of switching frequency .............................................................................. 31
3.8. Conversion efficiency ................................................................................................ 31
3.9. Summary ................................................................................................................... 33
4. Control of Three-phase Power Factor Correction Rectifier.............................................. 35
4.1. System description..................................................................................................... 35
4.2. Current controller ...................................................................................................... 35
4.2.1. PI current control in the dq reference frame ...................................................... 37
4.2.1. PR control in the Įȕ reference frame ................................................................. 39
4.3. DC voltage control loop ............................................................................................ 45
4.4. Experimental results .................................................................................................. 47
4.4.1. PFC rectifier connected to Drive........................................................................ 47
4.4.2. Comparison of the controllers ............................................................................ 49
4.5. Summary ................................................................................................................... 54
5. Conclusion and Future work ............................................................................................. 55
5.1. Conclusion ................................................................................................................. 55
5.2. Future work ............................................................................................................... 57
References ................................................................................................................................ 58
A. Three-Level Three-Phase Power Factor Correction Rectifier .......................................... 63
A. 1. Introduction ............................................................................................................... 63
A. 2. Three-level ANPC ..................................................................................................... 64
A. 3. Hybrid three-level ANPC .......................................................................................... 64
A. 4. Loss distribution .......................................................................................................... 65
A. 4.1. Inductor design and loss calculation ..................................................................... 65
A. 4.3. Loss in the switches .............................................................................................. 66
A. 4.2. Total loss ............................................................................................................... 66

xi
 A. 5. Conclusion ................................................................................................................... 67
B. Appendix B ....................................................................................................................... 69
Appendix B1......................................................................................................................... 70
Appendix B2......................................................................................................................... 90
Appendix B3......................................................................................................................... 97
Appendix B4....................................................................................................................... 108
Appendix B5....................................................................................................................... 115
Appendix B6....................................................................................................................... 126
Appendix B7....................................................................................................................... 133
Appendix B8....................................................................................................................... 140

xii
List of figures
Fig. 1.1: The overview of the thesis structure (*These two papers are not listed in Appendix B
but listed in list of publications). ................................................................................................ 5
Fig. 2.1: The schematic of a two-level three-phase PFC rectifier with LCL filter..................... 8
Fig. 3.1: The schematic of a two-level three-phase PFC. ........................................................ 16
Fig. 3.2: The generic equivalent circuit of the filter. ............................................................... 17
Fig. 3.3: (a) Simplified schematic of three-phase grid-connected voltage source converter, (b)
the inductor current and voltage waveforms. ........................................................................... 18
Fig. 3.4: (a) current ripple at zero crossing and (b) current ripple at peak current. ................. 19
Fig. 3.5: The current ripple for THPWM (a) at zero crossing (ma = 2/¥3) and (b) at peak of
the current. ............................................................................................................................... 20
Fig. 3.6: The position of the sensors- single phase equivalent circuit of LCL filter (a) voltage
sensor at PCC, current sensor at converter-side (b) voltage and current sensor at PCC, (c) the
vector diagram of first sensor position and (d) the vector diagram of second sensor position.
.................................................................................................................................................. 22
Fig. 3.7: (a) LCL filter with resistive damping, (b) the corresponding root-locus for finding an
optimum damping resistor, (c) LCL filter with RC damping, (d) the corresponding root-locus
for three different scenarios where 1) Cf = 4Cd , 2) Cf = Cd, 3) Cf = 1/4Cd (in all scenarios
Cf+Cd is kept constant). ............................................................................................................ 24
Fig. 3.8: (a) current and voltage of damping branch and grid-side inductance and (b)
magnified maximum current ripple and corresponding inductance voltage of grid-side
inductance in one switching cycle............................................................................................ 25
Fig. 3.9: Single phase equivalent circuit of the filter at hth harmonic. ..................................... 26
Fig. 3.10: Schematic of the dc link capacitor. .......................................................................... 28
Fig. 3.11: (a) wiring of the core, and (b) the inductance change through fundamental
frequency of main current for different loads. ......................................................................... 29
Fig. 3.12: The loss distribution in the converter at full load for three difference frequencies. 32
Fig. 3.13: The loss distribution in 5 kW SiC based three-phase PFC based on different load.33
Fig. 4.1: General schematic of the converter with controller. .................................................. 36
Fig. 4.2: (a) The block diagram of the PFC current control and (b) realization of feedforward
effect as a block diagram for further analysis. ......................................................................... 37
Fig. 4.3: (a) the block diagram of the controller in the dq reference frame and (b) the block
diagram of the PI current controller. ........................................................................................ 38
Fig. 4.4: Simplified equivalent circuit of filter and grid impedance. ....................................... 39
Fig. 4.5: The converter and grid current with PI controller in dq reference frame. ................. 39
Fig. 4.6: (a) Implementation of the controller, (b) the current control loop, and (c) the
implementation of harmonic compensator in z-domain........................................................... 40

xiii
Fig. 4.7: The frequency response of the open loop system for PR controller (a) without and
(b) with feed forward (gcc = 0.8). ............................................................................................. 42
Fig. 4.8: (a) Oscillatory response, (b) more damped response of the grid current for different
proportional gains. ................................................................................................................... 42
Fig. 4.9: (a) the implemented compensation for harmonic compensator, (b) frequency
response of the open loop system without phase compensation and (c) frequency response
comparison for 13th harmonic. ................................................................................................. 44
Fig. 4.10: The block diagram of the dc link voltage control loop including the current
controller. ................................................................................................................................. 45
Fig. 4.11: The performance of dc link control loop (a) general step response for different grid
impedances, the transient response of the dc link for (b) 564 V, and (c) 650 V. ..................... 46
Fig. 4.12: : Reference converter voltage (vabc*-see Fig. 4.6(a)) and zero sequence offset. ...... 47
Fig. 4.13: The experimental results of connecting PFC to Drive, torque from 3 N.m to -3 N.m
(I: no torque, II: positive torque, III: negative torque). ............................................................ 48
Fig. 4.14: The experimental results of connecting PFC to Drive, changing torque 6 N.m to -6
N.m (I: negative torque, II: zero torque, III: positive torque). ................................................. 48
Fig. 4.15: Nonlinearities of the converter at low load and high voltage for the 4-wire PFC (a)
simulation results and (b) experimental results. ....................................................................... 49
Fig. 4.16: The experimental results of the grid current for different controllers and converter-
side inductors (a)-(d) 25% of nominal load and (e)-(h) for full load. ...................................... 50
Fig. 4.17: The harmonic evaluation of the controllers with two different inductance value (a)
Lc = 1 mH, (b) Lc = 580 ȝH. ..................................................................................................... 51
Fig. 4.18: The experimental setup for measuring the efficiency.............................................. 52
Fig. 4.19: The measured efficiency with and without diode at low load (25% < Load < 40%)
for the PR control (without including drive loss). ................................................................... 52
Fig. 4.20: The efficiency curve for PI and PR controller (a) with SiC Schottky diode and (b)
without SiC Schottky diode. .................................................................................................... 53
Fig. A.1: The schematic of three-level three-phase active NPC. ............................................. 64
Fig. A.2: (a) the schematic of one phase of three-level HANPC, (b) the build prototype of one
leg three-level HANPC. ........................................................................................................... 65
Fig. A.3: Loss distribution in the converter at full load. .......................................................... 67
Fig. A.4: Built prototype of a 10 kW GaN based three-level HANPC. ................................... 67

xiv
List of Tables
TABLE 2-1: Efficiency comparison of the recent stat of the art. .............................................. 9
TABLE 2-2: Comparison between magnetic core materials. .................................................. 11
TABLE 2-3: Filter parameters by different method for 5 kW, 50 kHz three-phase VSC. ...... 12
TABLE 3-1: General system specifications and base values for per-unit system. .................. 15
TABLE 3-2: Maximum current harmonic distortion in percentage of rated current according
to IEEE519. .............................................................................................................................. 16
TABLE 3-3: Comparison of designed filter between two presented methods in this work. ... 27
TABLE 3-4: Comparison between SiC and Si MOSFETs (1200 V, 30 A)............................. 30
TABLE 3-5: Designed inductor for 25 kHz, 50 kHz, and 75 kHz........................................... 32
TABLE 3-6: Specifications of the components used in the converter. .................................... 33
TABLE 4-1: The parameters of the dc link controller for 2 case studies. ............................... 46
TABLE A-1: Switching state of the generalized three-level converter. .................................. 64
TABLE A-2: The converter specifications .............................................................................. 65
TABLE A-3: The ac resistance of the copper winding for 136 ȝH inductor ........................... 66
TABLE A-4: The switching parameters of Si MOSFET and GaN FET. ................................ 67
TABLE A-5: Loss in the switches. .......................................................................................... 67

xv
Abbreviations
ADS Adjustable speed drives

ANPC Active Neutral Point Clamped

CHB Cascaded H-Bridge

CCM Continuous conduction mode

DSOGI Dual second order generalized integrator

EV Electric vehicle

FC Flying capacitor

FFT Fast Fourier transform

GaN Gallium-Nitride

HC Harmonic compensation

HGNPC Hybrid Generalized Neutral Point Clamped

mmf Magneto motive force

MOSFET Metal Oxide Semiconductor Field Effect Transistor

MPP MolyPermalloy powder cores

NPC Neutral point clamped

PCB Printed circuit board

PFC Power factor correction

PWM Pulse width modulation

Si Silicon

SiC Silicon-Carbide

SJ Super junction

SOGI Second order generalized integrator

SPWM Sinusoidal Pulse width modulation

SVM Space vector modulation

THPWM Third-Harmonic PWM

UPS Uninterruptible power supply

VSC Voltage source converter

WBG Wide-band gap

xvi
Nomenclature
ǻi Converter current ripple
ǻVripple AC voltage ripple of filter capacitor
școmp. Compensated phase delay
șI The angle of the converter current
șI,delay The delay introduced to the measured converter current
șV The angle of the PCC voltage
șV,delay The delay introduced to the measured PCC voltage
Ȝ Delay
Ȧg Fundamental angular frequency of grid
Ȧsw Angular frequency of switching
Cd Damping filter capacitance
Cd,max Maximum damping filter capacitance
Cd,min Minimum damping filter capacitance
Cdc DC link capacitance
Cf Filter capacitance
Coss Output switch capacitance
fg Grid frequency
fres Resonant frequency of the filter
fsw Switching frequency
gcc Gain of the feedforward voltage
h The harmonic number
I Converter current
Ic Filter shunt current
ID MOSFET Drain current
Ig Grid current
Iload Load current (DC)
Kcos,h The compensation gain for hth harmonic on the path of Į-axis
Ki Integral gain of the current controller
Ki,h Integral gain of the hth harmonic compensator
KP Proportional gain of the current controller
KP,dc Proportional gain of the dc link controller
Ksin,h The compensation gain for hth harmonic on the path of ȕ-axis
Lc Converter-side inductance
Lf Grid-side filter inductance
Lgrid Grid inductance

xvii
LT Total series inductances of the filter
m3 Modulation index of the injected third harmonic
ma Modulation index
Pcap MOSFET capacitor loss
PCond. Switch conduction loss
Pcopper Total copper loss
Pcore Inductor core loss
Pdrive MOSFET drive power
Qoss Output switch charge
QG MOSFET gate charge
Rd Damping resistor
Rdc DC copper resistance
RDS MOSFET drain source resistance
RLISN LISN resistance
Rload Load resistance
RT Total series resistances of the filter inductances
S Apparent power
ti,dc Integral gain of the dc link controller
Tin Inner time of dc voltage control loop
Ts Sampling time
Tsw Switching period
van Converter voltage
Vb Base voltage
Vdc DC link voltage
Vdrive MOSFET drive voltage
VDS MOSFET drain source voltage
vff Feedforward voltage
Vm Peak of voltage at point of common coupling (PCC)
VPCC Voltage at PCC
vxN AC link voltage of phase x
Yeq Equivalent admittance
Zb Base impedance
Zgrid Grid impedance

xviii
CHAPTER I- INTRODUCTION

1. Introduction
This thesis is to present the results obtained in the PhD project entitled as “high efficiency
three-phase power factor correction using wide band-gap devices” performed by the author
from December 2013 to November 2016. Many scientific results obtained in this project have
been published in peer reviewed journal and conference papers. The published papers are
included in Appendix B1-Appendix B8.
The main target of this report is to place the published papers in the context of the project
objectives and present a more coherent and complete overview of the work carried out over
three years.
It is intended that this thesis can serve as a design aid for three-phase power factor correction
rectifiers: Hardware and Control for achieving relatively high conversion efficiency
compared with the current state-of the art.

1.1. Background and Motivation

Three-phase ac-dc converters are widely used in adjustable speed drives (ADS),
uninterruptable power supplies (UPS), high voltage dc systems (HVDC), battery energy
storage systems, battery charger for electric vehicles (EVs), and power supplies used in
telecommunications. Conventional ac-dc converters, line-commutated rectifiers, are highly
non-linear and introduce high level of grid current harmonics and low power factor.
Traditionally, passive filters are used to reduce the current harmonics and improve the power
quality of the ac side. However, this solution requires a bulky passive filter which reduces the
conversion efficiency [1]-[4].

The international regulations, in term of power quality, have forced power electronics and
power systems engineers to develop active solutions. A new breed of rectifiers using new
solid-state force-commutating devices such as MOSFETs and IGBTs bring the following
advantages: (a) the current or voltage can be modulated, generating a smaller harmonic
contribution; (b) the power factor can be controlled; and (c) they can be built as voltage
source or current source rectifiers [1]-[4]. Such converters are generally identified using
different terms such as switched-mode rectifiers, power factor correction rectifiers (PFC), and
pulse width modulation (PWM) rectifiers. In this thesis, the term PFC is used as a general
name for such converters.
Recently, many promising PFC topologies using force-commutated devices have been
proposed and this topic has become an active research topic in power electronics due to the
PFCs unique characteristics. Three-phase two-level boost PFC is able to achieve the best
performance in terms of shaping the input current and allowing bidirectional power flow with
a minimum number of active switches [1]-[2].

To improve the conversion efficiency, each component needs to be optimized by both

selecting the material and the design. To minimize the loss in the switches, it is reasonable to

1
CHAPTER I- INTRODUCTION

use power devices which 1) introduce low on-resistance and 2) have a good transient
performance (i.e. low input and output capacitance charge). The first one contributes to
reduction of conduction loss and second one in reduction of switching loss.
Currently, the power semiconductor devices are based on the mature and well-established
silicon technology. However, silicon exhibits some limitations in terms of blocking
capability, thermal conductivity, capacitive charge, and saturated drift velocity [5]. Instead,
wide band-gap (WBG) technology becomes highly attractive compared to Si technology
because of their low switching losses, low conduction loss, high temperature capability.
Among the possible candidate silicon-carbide (SiC) and gallium-nitride (GaN) present better
tradeoff between the theoretical characteristics and the real commercial availability [5]-[7].
The improved switching characteristic of WBG devices compared to their Si counterparts
means that they may allow shorter switching times. Decreasing the transition time and
increasing the switching frequency allows smaller reactive components i.e. capacitors and
inductors. Design for higher frequency, however, will introduce new challenges regarding
layout design ensuring lower stray inductance for semiconductors and designing better
inductor regarding magnetic material and type of winding.
Therefore, passive components, especially inductors are among the most important in PFC
converters as they have a high impact on the efficiency and the performance of PFCs. High
switching frequency introduces corresponding high frequency current ripple in the PFC
inductors. Then analysis of the high frequency minor B-H loops caused by high frequency
current ripple makes core loss calculation even more complicated. The ac copper loss by the
skin and the proximity effects can also be a critical issue in designing the inductors to avoid
having large copper loss.
It can be concluded that in designing of PFCs either two-level or multilevel configurations,
there is a strong non-linear correlation between various parameters and components. For
instance, increasing the switching frequency decreases the size of the reactive components.
But it increases the switching loss. It may increase the core loss in the magnetic materials,
and it increases the ac copper loss. So, there should be a trade-off between these parameters.
There is an optimum point that the maximum efficiency is achieved. This PhD project
provides an answer to this question: through emerging high frequency WBG devices, thereby
revealing possible ways to increase the efficiency of three-phase PFCs?

1.2. Project objectives and Contributions

1.2.1. Research objectives and challenges

The primary objectives of the project are as follows:
x Increasing the conversion efficiency of a 5-10 kW three-phase power factor correction
rectifier;
x Improving the power quality of the converter;
x Providing bidirectional power flow;

2
CHAPTER I- INTRODUCTION

The primary topology for PFC is a two-level voltage source converter (VSC) using SiC
switches. Accordingly, the challenges towards the main objectives of the project are
addressed as follows:
x To present a general and straightforward method for designing the converter-side
inductor and calculating its power loss;

x To identify a core material for the inductor that yields a relatively low core loss;

x To derive a general design method to optimize the ac line filter based on the principle
of operation of the converter;

x To design a layout for the high frequency SiC switches that minimizes the parasitic
elements in the circuit;

x To identify better controller for PFC which has more impacts on the efficiency;

x To identify possible improvements that wide band-gap devices bring for PFC
converters.
1.2.2. Contributions
The contribution of this work can be split in two categories:
1) Design methodology

x A general method for choosing and designing the converter-side inductor has
been established;

x A general method for calculating core and copper losses for the converter-side
inductor (i.e. the boost inductor) is derived;

x A comparison of three wire and four wire PFC has been made regarding the
achievable efficiency;

x A general method for calculating the parameters of the ac line filter to

minimize its size and/or maximize its efficiency has been derived;

2) Control methodology

x The impact of feedforward compensation in control methods has been studied;

x The impact of two common control methods on the efficiency has been
investigated.

3
CHAPTER I- INTRODUCTION

1.3. Thesis overview

The thesis includes an extended summary and a collection of the published and submitted
scientific papers. Parts of the papers are used directly or indirectly in the extended summary
of the thesis. The purpose of this thesis is, therefore, to complement the already published
papers by providing a coherent presentation of the overall project and its results. Special
focus will be devoted to present a coherent derivation of the key fundamental theoretical
aspects of this project.
Since most of the experimental results are presented in the published material reproduced
Appendix B, only summaries of the results are given in the main body of the thesis with the
main purpose of extending the analysis of the experimental results to verify the validity of the
theoretical results. The content and structure of the thesis is depicted in Fig. 1.1.
In Appendix A, the next step of the project is briefly explained. The next step will be on using
commercially available GaN switches for PFC rectifier on the basis of multilevel converters.
In this appendix, the principle operation of the converter is explained and the design process
is optimized by following the same path for two-level PFC as explained in Chapter 3 and 4.
The inductor will be designed for the converter using the general approach which is presented
in Chapter 3. The layout design in this case will be more complicated in comparison with the
two-level PFC. The converter is a 10 kW hybrid three-level three-phase active neutral point
clamped (ANPC) which utilizes both GaN and Si switches. In this case, several challenges is
addressed and studied as follows:
x To identify a suitable topology which utilizes the best out of GaN switches which are
commercially available;

x To design a proper layout, especially for the GaN drivers;

x To extend the proposed methodology of two-level PFC (Chapter 3 and 4) to the new
topology;

x To compare the achieved results of two-level and multilevel with two different
technologies of WBG devices, SiC and GaN, respectively.

1.4. List of publications

Many of the scientific results obtained in the project have been published in the form of peer
reviewed conference and journal papers. The published papers form an integral part of this
thesis and are included in the Appendix B. The list of publications is arranged according to
the published year. They are listed as follows:

4
CHAPTER I- INTRODUCTION

Fig. 1.1: The overview of the thesis structure (*These two papers are not listed in Appendix B but listed in list of
publications).

1. A. Kouchaki, M. Nymand, "Analytical Design of Passive LCL Filter for Three-phase

Two-level Power Factor Correction Rectifiers," in IEEE Transactions on Power
Electronics, submitted, under review.
2. A. Kouchaki, R. Lazar, J.L. Pedersen, M. Nymand, "5 kW Bidirectional Grid-
Connected Drive using Silicon-Carbide Switches: Control," 2017 IEEE Applied
Power Electronics Conference and Exposition (APEC), Tampa, Florida, 2017.
3. A. Kouchaki, R. Lazar, J.L. Pedersen, M. Nymand, "High Frequency Three-Phase
PWM Grid Connected Drive Using Silicon-Carbide Switches," IEEE Southern Power
Electronics Conference (SPEC’16), 5-8 December 2016.
4. A. Kouchaki, M. Nymand, R. Lazar, "Non-iterative, Analytic-based Passive LCL
Filter Design Approach for Three-phase Two-level Power Factor Correction

5
CHAPTER I- INTRODUCTION

Converters", Power Electronics and Applications (EPE'16 ECCE-Europe), 2016 18th

European Conference on, Karlsruhe, 2016, pp. 1-10.
5. A. Kouchaki and M. Nymand, "LCL filter design for three-phase two-level power
factor correction using line impedance stabilization network," 2016 IEEE Applied
Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2016, pp.
2382-2388.
6. A. Kouchaki and M. Nymand, "Inductor design comparison of three-wire and four-
wire three-phase voltage source converters in power factor correction applications,"
Power Electronics and Applications (EPE'15 ECCE-Europe), 2015 17th European
Conference on, Geneva, 2015, pp. 1-10.
7. A. Kouchaki, N. F. Javidi, F. Haase and M. Nymand, "An analytical inductor design
procedure for three-phase PWM converters in power factor correction applications,"
2015 IEEE 11th International Conference on Power Electronics and Drive Systems,
Sydney, NSW, 2015, pp. 1013-1018.
8. F. Javidi, A. Kouchaki and M. Nymand, "A simple core loss modeling for three-
phase PWM voltage source converters," Industrial Electronics Society, IECON 2015 -
41st Annual Conference of the IEEE, Yokohama, 2015, pp. 003063-003068.
9. F. Haase, A. Kouchaki and M. Nymand, "Controller design and implementation of a
three-phase Active Front End using SiC based MOSFETs," 2015 9th International
Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Seoul, 2015,
pp. 2681-2687.
10. F. Haase, A. Kouchaki and M. Nymand, "A low cost rapid prototype platform for a
three phase PFC rectifier application," Industrial Technology (ICIT), 2015 IEEE
International Conference on, Seville, 2015, pp. 2024-2029.

6
CHAPTER II- STATE OF THE ART

2. State of the art

The purpose of this chapter is to present an overview of the present state of the art of three-
phase PWM power factor correction (PFC) rectifiers/three-phase voltage source converters
(VSCs). Recent published literature primarily in the form of journal papers, conference
papers and tutorial notes, has been searched and analyzed to establish the state of the art. The
main focus has been to identify publications presenting technical results, preferably supported
by experimental results and useful for or related to the overall specification defined for this
project.
For many years, ac-dc converters have vastly been investigated from different aspects such as
topology, switching patterns, control, design at the components level, harmonic analysis, and
etc. By emerging the new type of power semiconductors as wide band gap devices, the
attention on employing these switches for PFC applications or generally PWM VSCs is
increased. Consequently, a significant amount of scientific literature has been published on
the subject. To best be able to provide a fair comparison for this study, the following
categorization is presented for the state of the art:
x The overall optimization and design of ac-dc converters, which can be two-level or
multilevel with different topologies, the focus not being on the topology, but on the
conversion efficiency [16]-[29];

x Optimization at the component level including the inductor core material, the boost
inductor loss and/or size minimization [30]-[33] and [39]-[44];

x Filter design [45]-[65] and stability of grid-connected converters [66]-[76].

Although, this PhD work utilizes wide-band gap devices for implementation, the focus is not
on studying the technology behind these devices but on implementing and comparing the
attainable performance with the current state of the art in PFC rectifiers.
Papers published as part of this project are not, of course, included in the state-of-the-art
analysis but are attached in Appendix B.

2.1. Three-phase voltage source converters

Most research to date has focused on the efficiency of the converter only considering
switching and conduction losses. Unfortunately, very few papers have been published on
optimization of the whole converter with respect to high efficiency. Here, papers on
efficiency and the supporting experimental results will be discussed.
A 10 kW SiC based three-phase boost PFC with 6 discrete SiC switches has been made and
addressed in [16]. The optimum switching frequency is suggested to be 40 kHz. The
converter is connected via an LCL filter to the grid. The maximum efficiency in the rectifier
mode reported in this paper is 98.75% at half load and 98.65% at full load for 600 V dc link

7
CHAPTER II- STATE OF THE ART

voltage. The efficiency in the inverter mode is slightly lower than in the rectifier mode. Fig.
2.1 shows the schematic of a two-level three-phase boost PFC rectifier with an LCL filter.

In [17], a 10 kW two-level three-phase SiC based boost grid-connected converter has been
investigated. The converter is designed with an LCL filter for fulfilling the grid regulations. In
the design, the three-phase SiC MOSFET module has been used at a switching frequency of
16 kHz. A ferrite core is utilized for the high frequency converter-side inductor. The
measured efficiency shows a maximum of approximately 99% around 50% of the nominal
load. The dc link voltage is 580 V.
Paper [18] reports the design of a 5 kW fully SiC JFET-based three-phase boost converter
operating at 48 kHz. The maximum achieved efficiency is lower than 98%. Increasing the
load reduces the efficiency and this reaches a minimum of 97.5% at full load. This paper,
however, has not also specified the filter specifications and the associated losses.
Three different 10 kW converters have been designed with various criteria including size and
efficiency in [19]. The high efficiency converter design has already been explained in [17].
The minimum size is achieved by increasing the frequency to 80 kHz but the efficiency
reduces from 99.1% to 98.2 % while the power density increases from 0.94 kW/dm3 to 5.23
kW/dm3.
In [20], one diode at the output of the converter is added to improve reliability and provide
zero voltage transition. The test condition for a 5 kW converter using IGBT switches are: 180
V rms input, 350 V dc link output and 50 kHz switching. The maximum efficiency is 97%
and the minimum is 96.5%. According to the efficiency curve, it can be said that the
converter has been oversized because the maximum efficiency occurs at full load.

Fig. 2.1: The schematic of a two-level three-phase PFC rectifier with LCL filter.

8
CHAPTER II- STATE OF THE ART

TABLE 2-1: Efficiency comparison of the recent stat of the art.

DC link Switching Peak

Paper Power Topology Switch type
voltage (V) frequency (kHz) efficiency (%)
[21] 5 kW CoolMOS 400 18 98.8
Buck
[22] 1 7.5 kW IGBT 400 28 98.5
[16] 10 kW SiC MOSFET 600 40 98.75
[17] 10 kW SiC MOSFET2 580 16 99
[18] 5 kW Boost SiC JFET - 48 98
[19] 10 kW SiC MOSFET 600 80 98.2
[20] 3 5 kW IGBT 350 50 97
[24]5
3 kVA NPC SJ MOSFET4 720 20 99.3
[27]5
5 kW Six-pack SiC MOSFET2 650 10 98.5
1
The liquid cooling has been used in this converter.
2
Six-pack SiC MOSFET module has been used in this design.
3
A diode has been put in series at the dc output of the converter.
4
Super-junction.
5
Only switching device losses.

Paper [21] presents a 5 kW three-phase buck converter with a 400 V dc link voltage. The
reported conversion efficiency is 98.8% achieved with CoolMOS with a minimum of 97.6%
at 10% of full load.
A 7.5 kW three-phase buck converter with the output dc link voltage of a 400 V has been
reported in [22]. The efficiency at full load is 98.5 % with a liquid cooling system. The
switching frequency is set to 28 kHz using SiC switches. This paper also addresses the ac
inductor design including finding a suitable material for the inductor. According to the power
rating, inductance size, and the wire size different core materials have been compared. Nano-
crystalline core has been suggested for the high frequency inductor.
In [23], a 10 kW T-Type converter has been tested at switching frequency swept between 4-
48 kHz. The focus of this paper is on the switching and conduction loss and its comparison
with conventional three-phase converters.
TABLE 2-1 summarizes the useful information obtained from the literature search, with
focus on the converter specifications and the overall efficiency.

2.2. Optimization on component level: inductor and core material

Optimization of the converter efficiency requires optimization with respect to every

component. This section is focused on inductor design for grid-connected PWM voltage
source converters (VSCs).
The electrical and thermal performance of the hard switched boost PFC is heavily dependent
on the characteristics of the switching devices and boost inductor [30]. Magnetic and inductor
design entail trade-offs: a saving in one area can make things worse elsewhere with an overall
change in harmonics or efficiency. Thus choosing the optimum is critical for minimizing the

9
CHAPTER II- STATE OF THE ART

overall loss. Improving the efficiency of the inductor highly depends on core material and
inductor winding method.
There are various core materials that are commercially available such as ferrite, powder,
powder core, amorphous, Nano-crystalline, and etc. Any of these core materials has different
specifications and can be suitable for the PFC inductor according to the power level, current
ripple frequency, magnitude of current ripple.
In [31], three different core materials have been compared for the main inductor [Lc in Fig.
2.1] used in two-level three-phase PFCs: i) Ferrite (EPCOS), ii) Amorphous, and iii) Powder
core-Kool-Mȝ. The power rating of the converter is 20 kW and the switching frequency is
swept from 5 kHz to 80 kHz. Ferrite cores offer lower saturation flux density and low
maximum hot spot temperature. Although, ferrites do provide lower core loss, the energy
storage capability is the lowest compared to the others. In addition, the permeability and loss
of ferrites are highly dependent on the temperature [33].

An unidirectional 1.2 kW CCM single-phase boost rectifier has been designed in [30] to
compare the performance of two different core materials, ferrites and powder iron. Ferrites
are preferred for inductors subject to a large current ripple. The fringing fields near the air gap
impose an additional design constraint on the winding of the inductor. Powder iron cores also
suffer from thermal aging problems, unless the core loss is limited to very low values.
Powder cores suffer less from thermal aging and hot spotting in the core compared to powder
iron cores. MPP-Powder core has a better inductance independency to dc magnetization and
the lowest core loss among other powder cores such as Kool-Mȝ, High-Flux, and Mega-Flux
[32]-[34]. However, MPP cores have lower saturation flux density compared to the other
powder cores.
Amorphous shows a higher core loss than ferrite, despite offering higher saturation flux
density compared to ferrite and Kool-Mȝ. Like the Kool-Mȝ materials, amorphous also
features a soft roll-off of the B-H curve. This feature can be utilized to decrease the inductor
volume by means of allowing the inductance to fall by a certain percentage at peak current
[31]-[33].

In [33], it is concluded that the best trade-off between size and core loss is attainable using
the amorphous core. The Sendust (such as Kool-Mȝ) material can be adopted for high ripple
conditions since the loss remains relatively constant despite increasing the ripple of magnetic
field intensity. Moreover, the powder materials are good candidates for PWM filters,
especially at high ripple currents. However, this paper has not considered the effect of power
level on selecting the optimum material.
To summarize the literature review, TABLE 2-2 is listed the magnetic materials properties.
Although, TABLE 2-2 gives a clear picture on what type of material can lead to lower core
loss, the power level of the magnetic component can change the priorities. For instance,

10
CHAPTER II- STATE OF THE ART

TABLE 2-2: Comparison between magnetic core materials.

Core loss density(W/mm3)

Core type and manufacturer Material Bsat (T)
@0.1T, 50 kHz
MPP-60ȝ 0.7 357.1 f 1.12B 2.05= 255
Powder core- Magnetics [34] KoolMȝ-60 1 193 f 1.29B 2.01= 300
High Flux 1.5 492 f 1.32B 2.22=518
Ferrite- Ferroxcube [35] 3C92 0.46 60

Ferrite-TDK [36] PE90 0.43 25

Amorphous-Hitachi Metals [37] 2605SA1 1.56 46.7 f 1.51B 1.74= 313

Powder iron- Micrometals [38] Mix-26 1.38 1800

ferrite cores offer the lowest core loss density but depending on the number of turns it may
yield a larger copper loss. Or the core loss in ferrite core may drastically increase due to the
dc magnetization effect depending on the current ripple and power level. In Chapter 3, an
appropriate core material will be chosen to have a balance between the core and copper loss,
therefore to achieve an optimum design for the inductor.

2.3. Filter design

This section is divided into the following categorizations:

i) Filter parameter design including damping method (i.e. passive and active damping):
Filter design has largely been investigated for grid-connected VSCs. The main objective of
employing the filter is to fulfill the grid regulations (e.g. IEEE 519 [9] and [43]). Among
numerous papers in this area [45]-[65], several papers that are mostly related to the PhD work
have been selected and studied [45]-[50] in the following.

A general and step-by-step approach for designing LCL filter of grid-connected rectifiers has
been introduced in [45]. Control design and the impact of employing LCL filter on controller
and its performance are also discussed in this paper. The grid-side inductance value is chosen
as a function of the converter-side inductor. However, choosing the converter-side inductance
value is not explained. Another iteration based solution for designing LCL filter has been
developed in [46]. A margin for the converter and grid side inductance values is presented
according to the operation principle of the converter and the filter resonant is damped by an
active method. Optimization of LCL filters with passive damping in terms of loss and size has
been investigated in [48]-[51]. In [48] and [49], the damping branch is configured as shown
in Fig. 2.1 and the damping resistor is designed to reduce the power losses and provide a
proper damping. Different passive damping configurations are investigated in [50]. The
tradeoff between the effectiveness, the simplicity, and the power dissipation of different -

11
CHAPTER II- STATE OF THE ART

TABLE 2-3: Filter parameters by different method for 5 kW, 50 kHz three-phase VSC.

Converter-side Grid-side Filter Damping fres

Paper
inductor (ȝH) inductor (ȝH) capacitor (ȝF) resistor (Ÿ) (kHz)
[45] 600 600 5 2.5 4.11
[47] 600 200 5 8 5.82
[49] 763 300 5 12 4.85
[50] 540 540 5 18 4.33

damping configurations, the damping in this work will be as shown in Fig. 2.1. In TABLE
2-3, a summary of the presented papers is provided. The filter configuration with RdCd
passive damping is shown in Fig. 2.1. This table lists the calculated LCL filter parameters by
the papers for specific converter parameters which will also be studied in this PhD work. The
converter is a 5 kW three-phase VSC with 45 kHz switching frequency, 230 V line voltage,
and 700 V dc link voltage.
In Chapter 3, an LCL filter will be designed for the converter with the mentioned
specifications and will be compared with TABLE 2-3.

ii) Controller and Stability analysis:

After designing the filter, converter control stability by considering different grid conditions
needs to be studied [45]-[55],[60],[61],[72]-[77]. The stability analysis has been categorized
into two methods, impedance-base and passivity-based analysis [73]. According to these
different methods, the stability of the controller for employing active or passive damping is
also studied for different grid conditions in [61],[68],[76], and [77]. In this work, the
controller stability is analyzed using the impedance based analysis. Moreover the intention
for controller design in this work is not to improve the existing methods or suggest new
approaches. It mainly focuses on using the most suitable method for analyzing the impact of
different controllers on the conversion efficiency. Two controllers are used in this thesis, PI
controller in the rotational reference frame and PR controller in the stationary reference
frame. For design purpose, [45]-[46] for PI and [69] for PR are used.

2.4. Summary

The summary of the state of the art deduced from the literature search is as follows:
x The conversion efficiency of the most recent publications is studied and the
specifications of each converter are collected. This provides a fair comparison
between the current state of the art and this PhD research work.

x In many of the publications, comparisons between different core materials for

different applications have been made. The impact of the power range on the optimum
selection of these core materials for any specific application has to be considered.

12
CHAPTER II- STATE OF THE ART

According to the converter specifications in next chapter, using core characteristics

give an appropriate core material.

x Most often, the designing methods of LCL filters yield an oversized and the final
method is based on iteration. The current and voltage behavior of the filter parameters
based on the switching pattern of the converter has not been studied for identifying an
optimum filter in terms of loss/size.

x Due to the effectiveness, simplicity and relatively low power dissipated in the
damping of an LCL with a resistive-capacitive damping branch, in Chapter 3 the same
filter and damping will be used.

x Although the control of grid-connected converters is vastly studied in the literature,

the impact of different controllers and their parameter settings on the overall
efficiency of the converter has not been studied.

13
CHAPTER II- STATE OF THE ART

14
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

3. Two-Level Three-phase Power Factor Correction Rectifier

3.1. Introduction

In this chapter, two-level three-phase PWM voltage source converter (VSC) in power factor
correction applications (PFCs) is thoroughly analyzed to achieve high conversion efficiency.
After describing the system, step by step design of an LCL filter will be presented. The
objectives for designing the filter parameters are:
x To optimize the required filter parameters to have relatively small and high efficient
filter at operating switching frequency.
x To present a generalized model for filter design which can also be used for designing
a filter for a three-level converter [see Appendix A].

By obtaining the required filter parameters which successfully fulfill the grid regulations (see
section 3.2), the loss distribution in a silicon-carbide (SiC) based three-phase VSC will be
analyzed.

3.2. System description

In Fig. 3.1, the schematic of a two-level three-phase power factor correction rectifier (PFC) is
shown. The converter is a 5 kW SiC based two-level three-phase PWM PFC rectifier and its
specifications are listed in TABLE 3-1. The grid regulations have directed the grid connected
converters to provide a good current harmonic performance. Therefore, a high order filter
such as LCL filter is required to fulfill the grid regulations. The harmonic current injection
limit for grid-connected system where the rated voltage at point of common coupling (PCC)
[see Fig. 3.1] is 120 V to 69 kV is recommended by IEEE 519 standard. These current
harmonic limits are listed in TABLE 3-2.

The filter configuration shown in Fig. 3.1, consists of the converter-side inductor (Lc), the
grid side inductor (Lf), and the filter shunt branch shown with ZCf. All the inductances are
shown with impedance, because the resistive behavior of the reactive components is also
included in the analysis. The filter shunt branch can be replaced with different combination of
passive elements.
TABLE 3-1: General system specifications and base values for per-unit system.

Variable Description Value

Pnom Nominal power (kW) 5
Vac Phase source voltage- rms (V) 230
Vdc DC link voltage (V) 565-700
fg Grid frequency (Hz) 50
Zg Grid impedance (Ÿ) 20%×Zb1
1
The maximum grid impedance has been calculated by maximum short circuit current at PCC using IEEE-519 standard.

15
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

TABLE 3-2: Maximum current harmonic distortion in percentage of rated current according to IEEE519.

Harmonic order 5 7 11 13 17 19 23”h<35 h •35

Ih/Ig*,**(%) 4 4 2 2 1.5 1.5 0.6 0.3

*
Even harmonics are limited to 25% of the odd harmonics.
**
Ig: maximum grid current and Ih: grid current harmonic.

3.3. Filter design

In this section, filter parameters will analytically be designed to achieve an optimum filter as
well as a general method for designing filter.
For further analysis several assumptions have to be taken as follows:
1) The grid voltage is balance. Therefore, analysis is presented for only one phase (e.g.
phase ‘a’);
2) The switching frequency is much higher than the grid frequency (i.e. fsw >> fgrid);
3) The modulation scheme is sinusoidal pulse width modulation (SPWM);
4) The modulation is center-based pulse width modulation.
The equivalent single-phase circuit can be depicted as shown in Fig. 3.2. The filter voltage is
found as follows:
vfilter (t ) vPCC t  van t (3.1)
where vfilter and vPCC are the filter and PCC voltage, respectively. van can be expressed as a
function of the common mode voltage (vnN) and the ac link voltages.
1 2 1 1
van (t ) vaN t  vnN t vaN t  vbN t  vbN t (3.2)
3 3 3 3
where vxN is the ac link voltage of phase x (x = a, b, c).

Fig. 3.1: The schematic of a two-level three-phase PFC.

16
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

Fig. 3.2: The generic equivalent circuit of the filter.

The fast Fourier transform (FFT) of the ac link voltage for “phase a” is derived based on the
Bessel function for a naturally sampled SPWM (i and j are carrier and base-band index
variable, respectively) and based on (3.2) the converter voltage FFT can be derived as follows
[10]:

4Vdc f f
1 § S · § S·
van Vdc ma cos Z g t  ¦¦iJ ¨ i ma ¸ sin ¨ >i  j @ ¸Q (t ) (3.3)
S i 1 j f
n
© 2 ¹ © 2¹
where ma is the modulation index, Vdc is the dc link voltage, Ȧg is the fundamental angular
frequency, and Q(t) is as follows:
1
Q (t ) cos iZsw  jZ g t  P (t ) (3.4)
3
P (t ) cos iZ sw  jZ g t  cos iZ sw  jZ g t  2 nS / 3  cos iZ sw  jZ g t  2 nS / 3 (3.5)
Ȧsw is the switching or carrier angular frequency.
According to (3.3), it can be seen that the largest converter voltage harmonics happen at side-
band of carrier frequency where j = ±2 and i = 1 and this voltage reduces at multiple of carrier
frequency (i.e. i = 2, 3…). Therefore, the main concern for designing the filter is fsw±2fg [10].

3.3.1. Converter-side inductor

Since minimum required inductance value depends on modulation index, following analysis
is divided into linear modulation and overmodulation.

3.3.1.1. Linear modulation region

Generally, to fulfill the grid regulations, relying on converter-side inductor results to a bulky
and expensive solution which is out of the objective of this project. Therefore, increasing the
order of the filter could potentially reduce the overall size of the filter and accordingly losses.
If filter is designed correctly, the voltage after the converter-side inductor is essentially
sinusoidal and the amplitude is close to PCC voltage (very small voltage drop on Lf).
Therefore, it can be said that the converter-side inductor voltage is independent from the filter
configuration and converter voltage (i.e. van) determines the minimum required inductance
value [46]. Hence, the circuit shown in Fig. 3.1 can be simplified to Fig. 3.3(a) where vC is
the voltage across the shunt branch. Then, in (3.1) instead of filter voltage, inductor voltage

17
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

can be replaced and instead of vPCC, vC. Fig. 3.3(b) shows the inductor voltage and the
resultant current which flows through the inductor. As this figure indicates, inductor voltage
shows a repetitive pattern in each quarter of grid period. There are two time intervals that the
inductor voltage has similar behavior. Since, vC is sinusoidal, it can be concluded that this
pattern is generated by van.
The first interval is when the reference voltage of “phase a” is between the other phases (i.e.
0 < Ȧt < ʌ/3). The next interval is when the reference voltage of “phase a” is larger than the
other references (i.e. ʌ/3 < Ȧt < ʌ/2). Using the general expression of inductor voltage, the
average value of the current ripple can be found for region I and II. The detail procedure of
deriving the average current is explained in Appendix B1 and Appendix B2.
vLc (t ) vC t  van t (3.6)
vC t  van t
'i(t ) 't (3.7)
Lc
This observation also illustrates that in each time interval, there is a maximum current ripple.
For the first time interval, the maximum current ripple happens at zero crossing (i.e. Ȧt = 0).
The reference voltage of phase a, b, and c are 0, maVmsin(-2ʌ/3), and maVmsin(2ʌ/3),
respectively. The maximum current ripple for the second interval happens at peak current (i.e.
Ȧt = ʌ/2). Reference voltage of phase a is maVm and for phase b and c are -maVmsin(ʌ/6).

(a)

(b)
Fig. 3.3: (a) Simplified schematic of three-phase grid-connected voltage source converter, (b) the inductor
current and voltage waveforms.

18
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)
Fig. 3.4: (a) current ripple at zero crossing and (b) current ripple at peak current.

As a result, maximum current ripple in each interval is calculated as follows:

3 Vdc
Lc ma T kS , k  ^0,1, 2,...` (3.8)
12 f sw 'i
Vm S
Lc 1  ma 2 T 2k  1 , k  ^0,1, 2,...` (3.9)
2 f sw 'i 2
Maximum current ripple occurs at peak of the current when (3.10) is correct.

Vdc § 2 ·
d 3¨  1¸ (3.10)
Vm © ma ¹
By simplifying (3.10), the maximum current ripple happens at peak of the current when ma ”
0.845. The complete procedure of calculating the current ripple for this system is explained in
Appendix B1 and Appendix B2.

3.3.1.2. Overmodulation
The analysis provided in the previous section is focused on the linear modulation of SPWM.
Reducing dc link voltage is beneficial for both reducing the inductance value and therefore
reducing size of the filter and also reducing the switching loss. As it is seen from (3.8) and
(3.9), the inductance value is directly a function of dc link voltage. There are different
methods that expand the linearity of the modulation such as third harmonic injection PWM
(THPWM) and space vector PWM (SVPWM). Here, the current ripple at zero crossing and
peak current for THPWM is studied. The details of current ripple determination for THPWM
are fully explained in Appendix B1.
Similar to the analysis for linear modulation, the current ripple at zero crossing and peak of
the current are analyzed which is shown in Fig. 3.5(a) and (b), respectively.

19
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)
Fig. 3.5: The current ripple for THPWM (a) at zero crossing (ma = 2/¥3) and (b) at peak of the current.

According to the current ripple waveform shown in Fig. 3.5(a), the inductance value for
maximum modulation index in THPWM (ma=2/¥3) is found as:
Vdc
Lc (3.11)
6 f sw 'i
Interesting point that can be drawn from (3.11) is that if in (3.8) instead of modulation index
the maximum modulation index in THPWM or SVM is replaced (i.e. ma=2/¥3) then (3.11) is
obtained. Therefore, it can be concluded that (3.8) is a general equation for current ripple at
zero crossing of a two-level three-phase PFC using continues PWM such as SPWM,
THPWM or SVM.
The same procedure can be done for the peak current and its current ripple for THPWM as
following. To utilize the most of dc link m3 (which represents the modulation index for the
third harmonic) should be equal to one-sixth of modulation index and to have low switching
loss m3 is set to one-fourth of modulation index [10] and [78]-[80]. Therefore, to have a
general expression for current ripple at peak current the term m3 will be kept as it is. Fig.
3.5(b) shows the current ripple at peak current in one switching cycle.

By referring to Appendix B1, the current ripple for the peak current in THPWM is obtained
as follows:

3Vdc § m ·
'i ma ¨1  a  m3 ¸ (3.12)
6 Lc f sw © 2 ¹

20
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

Unlike (3.11) which is not dependent on the modulation index, (3.12) is a function of
modulation index. Moreover, comparing (3.11) and (3.12) demonstrates that the current
ripple at peak current for overmodulation is smaller than zero-crossing current ripple. This
confirms that since in overmodulation ma is larger than 0.845 then certainly the current ripple
at zero crossing is dominant.

3.3.1.3. Three-wire PFC and four-wire PFC

In line with the main objective of the project, the impact of connecting dc link midpoint to
star point of the filter on boost inductor size and converter efficiency is studied and presented
in Appendix B3. The conclusion of this comparison can be summarized as follows:
x Inductance value for the four-wire PFC is larger than the one for three-wire PFC.
x Maximum current ripple in three-wire PFC depends on modulation index for linear
modulation while in four-wire is not a function of modulation index.
x Current harmonic behavior of four-wire PFC is similar to the single phase PFC in
which the main harmonics happens at switching frequency.
x Minor B-H loops generated by the current ripple in inductors in both converters are
different and in four-wire it is easier to generalize the high frequency core losses.
More details on core loss calculation of four-wire PFC have been mentioned in
Appendix B8.
x The overall efficiency of the three-wire converter is higher than four-wire converter
with an identical current ripple limit.
3.3.2. Filter capacitor
Position of the current and voltage sensors in grid-connected voltage source converters can
affect the power factor and the control. Converter synchronizes itself with grid voltage, so
voltage sensor must be positioned on grid side [53]. However, current sensor can be
positioned either at grid side or converter side [53]. If the current sensor is positioned at the
grid side then the outcome of controller is a voltage and current in phase. On the other hand,
power factor cannot be one when current sensor position is at the converter side. But this
configuration provides a good fault protection for the converter. Besides, in controller which
will be explained later, the phase shift between grid voltage and current can be compensated
[12]. Fig. 3.6 shows single-phase diagram of an LCL filter for both sensors positions along
with their vector diagram. In the first case, the converter is seen as a capacitive load for grid
and in the second sensors position, it is pure resistive. For this PhD work, the sensors are
positioned as shown in Fig. 3.6(a).

The phase difference between Ig and VPCC can be achieved as follows (in steady-state
condition, fg = 50 Hz):

§ 1 · § C f Zg ·
I¨ ¸  jVPCC ¨
¨ 1  C L Z ¸¸
Ig (3.13)
¨ 1 C L Z ¸
2 2
© f f g ¹ © f f g ¹

21
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)

(c) (d)
Fig. 3.6: The position of the sensors- single phase equivalent circuit of LCL filter (a) voltage sensor at PCC,
current sensor at converter-side (b) voltage and current sensor at PCC, (c) the vector diagram of first sensor
position and (d) the vector diagram of second sensor position.

§ V ·
T current tan 1 ¨ C f Z g PCC ¸ (3.14)
© I ¹
This phase difference can be compensated using the control system, however as it is
mentioned in the literature the limit for the absorbed reactive power by filter capacitor is
considered 5% of apparent power [45].

Z g Z bC f ,max 0.05 , Z b Vb2 S (3.15)

where Zb, Vb , and S are the base impedance, voltage and apparent power, respectively.
For capacitor lower limit, high frequency current ripple which flows through the filter
capacitor needs to be calculated to define the minimum required filter capacitor. Ideally, the
current ripple flows through the filter capacitor. Therefore, the maximum converter current
ripple determines the minimum required capacitance value. The minimum required filter
capacitor can be obtained by (3.16) for peak current.

Vm
C f ,min 1  ma 1  ma 2 (3.16)
32 Lc f sw 2 'Vripple

In (3.16), Lc is replaced by (3.9), then (3.16) becomes as follows:

'i 1  ma
C f ,min (3.17)
'Vripple 16 f sw

Normally, current ripple is considered between 10-30% of nominal current and voltage ripple
is considered lower than 5% of nominal ac voltage. Replacing these values (k1 for current

22
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

ripple and k2 for voltage ripple, respectively) in (3.17) and normalized it with respect to Cf,max
then the following equation presents the normalized minimum required filter capacitor.

k1 1  ma
C f ,min Zg C f ,max (3.18)
16k2 f sw
From (3.18) it can be concluded that minimum required inductance is a function of switching
frequency and modulation index. The derivation method in details is presented in Appendix
B4 and Appendix B5.
3.3.3. Damping
From Fig. 3.2, the admittance from converter side point of view is obtained as follows:

i s 1
Yeq
van s Z Lg  Z L f ZC f  Z Lc (3.19)

Although putting a resistor in series with filter capacitor is completely against the objective of
the project, damping provided by the resistor can be extended by minor changes for other
shunt configurations [45],[50], and [57]. To simplify, the admittance can be written for a
simple damping resistor Rd in series with capacitor Cd as a function of the filter parameters
(the resistive elements of reactive components are neglected) [see Fig. 3.7(a)].

L f  Lg Cd s 2  Rd Cd s  1
Yeq (3.20)
Lc L f  Lg Cd s 3  Rd Cd Lc  L f  Lg s 2  Lc  L f  Lg s

The root-locus breakaway point of the transfer function when Rd is assumed to be a gain can
give the maximum damping resistance [see Fig. 3.7(b)]. The higher limit of damping
resistance can be found by calculating the breakaway point of root-locus as follows:

2 Lc Lg  L f Cd 2
Rd ,max (3.21)
Cd Lc  Lg  L f Cd Z n

And the lower limit is found when ȟ = ¥2/2 as follows:

2 Lc Lg  L f
Rd ,min (3.22)
Lc  Lg  L f Cd

To reduce the power loss in the damping branch, filter capacitor Cf will be paralleled with
RdCd which is shown in Fig. 3.7(c). Root-locus analysis shows increasing the filter capacitor
needs more damping resistor to damp the resonance which leads to higher loss. But the
attenuation after resonance frequency gets better.
Increasing the damping capacitor (Cd) leads to have more stable system and better transient
response with lower damping resistor. But attenuation after resonance frequency reduces. As-

23
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)

Three scenarios (Cf+Cd = cte):

1) Cf = 4Cd , 2) Cf = Cd, 3) Cf = 1/4Cd

(c) (d)
Fig. 3.7: (a) LCL filter with resistive damping, (b) the corresponding root-locus for finding an optimum damping
resistor, (c) LCL filter with RC damping, (d) the corresponding root-locus for three different scenarios where 1)
Cf = 4Cd , 2) Cf = Cd, 3) Cf = 1/4Cd (in all scenarios Cf+Cd is kept constant).

it is concluded in literature review as well ([47],[48],[50], and [57]), the best configuration is
to keep both filter and damping capacitors equal even-though it brings more losses compared
to the scenario where Cd is larger than Cf.
Power loss in the damping branch can be calculated using FFT of the current in the damping
branch. Calculation of loss in damping branch for both cases has been addressed in [57].

3.3.4. Grid-side inductor

Two methods are derived for calculating required grid-side filter inductance value.

3.3.4.1. LCL with resistive damping

The first method is using the filter configuration shown in Fig. 3.7(a). The capacitor ideally
draws all the high frequency current harmonics. If the damping resistor is correctly chosen,
the impedance of the damping branch is still smaller than the impedance of the grid-side filter
inductance at switching side-band frequency [Fig. 3.7(a)]. By adding the damping resistor,
the grid-side filter inductor voltage is influenced by the current ripple flowing through the

24
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)
Fig. 3.8: (a) current and voltage of damping branch and grid-side inductance and (b) magnified maximum
current ripple and corresponding inductance voltage of grid-side inductance in one switching cycle.

filter capacitor. As it can be seen in Fig. 3.8(a), the current which flows through the damping
branch is forming the voltage across it and causes that the voltage across the grid inductor is
also affected by the damping branch. On the other hand, the converter current shows its effect
on the grid-side inductor voltage. Fig. 3.8(b) shows the grid current and filter inductor voltage
in one switching cycle at peak current. The aim is to present maximum current ripple for this
inductor as shown with ǻig,max as a function of damping resistor.
The minimum required grid filter inductance value, then, is derived as a function of the
damping resistor and the converter current ripple as follows:
'imax
Lf,min§ Rd 1  ma (3.23)
18 f sw 'ig*

where ǻig* is the maximum allowable current ripple at grid side with respect to the grid
regulations. Using (3.22) and (3.23), the values for Lf and Rd can be calculated. The complete
method of deriving the inductance value for the grid filter has been conducted in Appendix
B1 and Appendix B5.

3.3.4.2. LCL filter design with LISN

Designing filter parameters often ends up with oversizing, since the design is for a stiff grid
or literally for no grid impedance. Therefore, the overall loss in filter increases in despite of
this fact that the grid impedance is constantly changing. Providing well-defined grid
impedance which is defined by the standards for choosing filter parameters can be beneficial
for having an optimum filter and providing repeatable measurements. By introducing the
WBG switches, the capability of having high frequency converter has increased which means
the major converter current harmonics drops at high frequency where Line impedance
stabilizing network (LISN) can provide well-defined impedance.
As it was mentioned in Section 3.3.1, the major PFC current harmonics happens at side-band

25
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

Fig. 3.9: Single phase equivalent circuit of the filter at hth harmonic.

of switching frequency. Besides, using SiC switches has increased the switching frequency
and then the side-band harmonics will certainly drop in the region that LISN can actively
provide constant impedance. The equivalent circuit of the filter with LISN is shown in Fig.
3.9.

The converter-side inductor and the filter capacitor are derived in the previous sections using
(3.8), (3.18), and (3.22), respectively. To optimally design the grid side filter inductance, the
equivalent circuit is used and the required inductance value to fulfill the grid regulation is
achieved as follows:

§ §V ·
2 ·
Lf ¨ ¨ an* ¸  RLISN D
2
 LcZh ¸¸ DZh
¨ ¨ Ig ¸
¨ © ¹ ¸ (3.24)
© ¹
D C f LcZh  1
2

Deriving of (3.24) is explained in details in Appendix B4.

The value of the grid-side inductor using the first method of damping is three times bigger
than the second damping method. In next section where the loss distribution will be studied,
the loss different between these two methods will be also discussed.
3.3.5. Filter comparison

Two different LCL filter has been designed and results are listed in TABLE 3-3 for a 5 kW
SiC based three-phase PFC with 45 kHz switching frequency [see Fig. 3.7(a)&(c)] (the
reason on selecting 45 kHz as switching frequency is explained in Section 3.7). The
converter-side inductance is independent from the filter configurations, hence using (3.8) for
30% current ripple gives the minimum converter-side inductance for the higher dc link
voltage (i.e. 700 V, see TABLE 3-1). Eq. (3.23) and (3.24) are used for determining the grid-
side filter inductance for both filter configurations, respectively. Using damping branch in
parallel with filter capacitor reduces size of the grid-side filter inductance to 1/3. According
to (3.15) and (3.18), the margin regardless of the filter configuration for minimum and
maximum filter capacitor is determined which is 2.5 ȝF and 5 ȝF, respectively. Based on the
lower margin defined in (3.22), the damping resistor for LCL with Rd is calculated. The
damping resistor for LCL with RdCd is also determined using root-locus analysis-scenario 2-
shown in Fig. 3.7(d). TABLE 3-3 is the summary of designed filter for both configurations.

26
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

TABLE 3-3: Comparison of designed filter between two presented methods in this work.

Ploss,damping(W) @
Method Lc (ȝH) Lf (ȝH) Cf (ȝF) Cd (ȝF) Rd (Ÿ)
Full power
Presented in Appendix B5 320 0 5 11 4
580
Presented in Appendix B4 100 2.5 2.5 10 0.815

According to the parameters, the second design will lead to higher efficiency and therefore it
will be used for the final converter design.

3.4. Layout design

Different layouts have been designed in this project and finally the optimum layout has been
taken which lead to higher conversion efficiency. The driver voltage for turn on and off has
been kept +15 V for turning on and -5 V for turning off [81]. In the beginning of the project,
the driver from Cree was used [82]. However, to place the driver as close as possible to the
switches for reducing the gate inductance, the driver layout changed.
The drive layout is also modified to provide proper shielding to the gate driver circuit to
avoid any noise injection at the gate of SiC MOSFETs. The parasitic inductance in the whole
converter is reduced as much as possible to avoid any voltage spikes for the SiC MOSFETs.
Although, SiC MOSFET switches have relatively low charges compared to alternative Si
MOSFET, the fast transient current during each switching instant can cause ringing in the
circuit. In order to reduce the parasitic inductance, ground and power planes or traces as well
as the decoupling capacitors are placed as close as possible to switches. In half bridge
configuration, the connection between the top and bottom switches (i.e., high side and low
side switches) is maintained very short by keeping them back to back on the PCB. Modular
design has been constructed in this layout to make sure the conditions for all phases are
identical.
The positive and negative dc rails are placed on top of each other to confine the filed in a very
small area. In addition, since the plates are wide and short the ac resistance of the plate is
reduced. The loop is also small and the parasitic inductance of each plate is also reduced.
The efficiency has increased by introducing the new layout. The efficiency curve which has
been shown in Appendix B3, results in the peak efficiency of 98.6%. In the new design, the
layout and inductors have been modified to achieve the peak efficiency of 98.95% which will
be explained in Chapter 4.

3.5. DC link capacitor

DC link capacitance value has been calculated according to the presented method in [85]. The
dc link capacitor is facing high frequency voltage ripple coming from switching pattern and
its value can be affected by the modulation scheme [85]-[86]. Furthermore, the capacitance

27
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

Fig. 3.10: Schematic of the dc link capacitor.

has to be sufficient to keep the dc link voltage constant during the transient. Because, the
delay introduced in signal measurements can cause noticeable transient for the dc link
voltage.
The minimum filter capacitance for 5% voltage ripple and voltage measurement delay time of
1 msec is 100 ȝF. To reduce the ESR of the dc link capacitor, Film capacitor has been used
and 6 of them are paralleled. To provide middle point connection for the dc link two
electrolytic capacitors are added in parallel with two film capacitors. The final dc link
capacitance value is 144 ȝF. The dc link capacitor configuration is shown in Fig. 3.10.

3.6. Loss distribution

In this section, loss distribution in two-level three-phase PFC will be explained. Core loss and
copper loss in filter inductors and damping power loss in damping branch will be calculated.
The conduction loss after determining the converter-side inductor is also explained and
finally the switching loss is achieved.
3.6.1. Inductor loss
According to the literature review and TABLE 2-2, although MPP core has lower saturation
flux density compared to other powder cores, it offers lower core loss. In addition, the effect
of dc magnetization on core loss is very small in this type of core. Therefore, MPP core has
been utilized for design of high frequency inductor in this work (i.e. Lc). During the process
of design, a great attention has been dedicated to the saturation flux density, size and number
of winding turns to avoid saturation and increasing the ac copper resistance. The
specifications of the inductor are shown Fig. 3.11(a).

Due to the effect of dc magnetization (i.e. change in permeability), the inductance value
changes by the fundamental grid frequency current as it is shown in Fig. 3.11(b) for different
load conditions. As it can be seen, no-load inductance value is 870 ȝH and when the current
is lower than 2 A the inductance value will be the same. As soon as the instantaneous current
increases more than 2 A, the inductance value starts to decrease. The full load inductance is

28
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

(a) (b)
Fig. 3.11: (a) wiring of the core, and (b) the inductance change through fundamental frequency of main current
for different loads.

about 580 ȝH. This variable inductance value causes the profile of the current ripple to
change.
As it is proved in Appendix B2, the ac copper loss is not critical for the high frequency
inductor Lc. Therefore the winding is selected to be solid wire. However, a great
consideration is taken to keep the windings layers not more than two as shown in Fig. 3.11(a)
to make sure that the ac resistance does not increase more than three times of the dc copper
resistance. The conclusion of the calculated ac resistance can be summarized as follows:
x The number of layer in toroidal core needs to be kept as low as possible not more
than two layers.
x Although the ac resistance is high at switching frequency and its multiple, since the
current harmonic at these frequency is small compared to the fundamental current, the
corresponding ac copper losses are negligible compared to the fundamental current
harmonic. On the other hand, for designing of the inductor for three-phase PFC, solid
round wire is perfectly suitable. This finding is also confirmed by [84].

To calculate the core loss, loss map method has been used [39],[87] and [88]. This method
has been explained in Appendix B2 and Appendix B8.
3.6.2. Switching loss
Device capacitance (i.e. CGS, CGD, and CDS) plays an important role in determining the energy
loss during each switching transition. The required charge at turn-on and turn-off state
determines the capacitance losses in switches. Due to the non-linearity of the gate-drain
capacitor, the output capacitor (COSS = CDS + CGD) is also nonlinear.
To calculate the capacitive switching loss, the output charge must be calculated. In device
datasheet, normally the output charge has given for a specific test condition and drain-source
voltage which might be different from the test condition of the converter. Therefore, this
value needs to be calculated for the operating voltage of the converter as in (3.25).

29
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

TABLE 3-4: Comparison between SiC and Si MOSFETs (1200 V, 30 A).

SiC MOSFET [89] Si MOSFET [90]

RDS(ON) 80mŸ 350 mŸ
Ciss (pF) 525 22500
Coss (pF) 134 950
Qg(nC) 49.2* 310**
*
Vds = 800 V, ID = 20 A, Vdrive = 0/20 V.
**
Vds = 800 V, ID = 12.5 A, Vdrive = 0/10 V.
V
Qoss ³C
0
oss v dv (3.25)

where, V is the drain-source voltage (i.e. for this converter is dc link voltage) and Coss(v) is
the variant output capacitance of the device with instantaneous drain-source voltage. By
modifying the output charge of the switch, capacitive loss can be calculated as follows:
1
Pcap. Qoss @VDS VDS f sw (3.26)
2
In addition to capacitive loss, turn-on and turn-off loss during the transition also composes
part of the loss in the whole converter. However, due to the fast switching transient of current
and voltage of SiC devices, the loss due to the capacitive loss is larger than this transition.
ª º
1
Psw VDS I D « tri  t fv  trv  t fi » f sw (3.27)
2 « »
¬ ON OFF ¼
Another loss which contributes to the switching loss is drive loss. SiC devices have very low
gate drive losses due to the small input capacitance (Ciss). The comparison between two
switches one SiC and other Si MOSFET shows the difference between the characteristics in
TABLE 3-4. Drive loss in the device is given as follows:

Pdrive Vdrive f swQG (3.28)

where, Vd is the gate drive reference voltage, fsw is the switching frequency and QG is the total
gate charge.
The other loss in switch is the conduction loss which is calculated as follows:
Pcond . RDS I D 2 (3.29)
Therefore, the power dissipation due to the switching is Psw+Pcap.+Pdrive+Pcond., all these
parameters except conduction loss are a function of switching frequency. Therefore, the
critical switching frequency can be achieved when the independent loss from switching is
equal to the rest of the switching loss.

30
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

3.7. Selection of switching frequency

Although having high frequency converter leads to smaller magnets, switching loss can be the
bottle neck of loss distribution in the converter. The losses in the converter components are
all dependent on the switching frequency. In order to find a tradeoff between size and
efficiency, a comparison has been conducted for three different switching frequencies:
1) 25 kHz,
2) 50 kHz, and
3) 75 kHz.
For any of these frequencies, the converter-side inductor is designed to keep the current ripple
at 30% and therefore, the rest of the filter is not changed. The specifications of the designed
inductor for each switching frequency are listed in TABLE 3-5. The material is MPP for all
the inductors. The core loss is increased by reducing the frequency because of higher
magneto motive force (mmf) which comes from higher number of turns (i.e. when fsw = 25
kHz).
Since the current ripple is kept constant in all cases, the conduction loss in all three cases will
be identical. However, the capacitive switching loss will be increased by frequency as
explained in Section 3.6.2. To have an idea on how parameters are affecting each other and
how the converter size and efficiency could be optimized Fig. 3.12 is depicted for three
frequencies. Note that all the calculations are done at full power. As it can be seen, the lower
frequency leads to have higher copper and core loss plus occupying more volume (more than
50% of all loss in the green area). On the contrary, higher switching frequency deviates the
red area from core and copper loss toward switching loss.
Therefore, 50 kHz switching is an optimum tradeoff between the size, switching loss, core
loss, and copper losses (see blue area in Fig. 3.12). In this work, the switching frequency is
selected to be 45 kHz to keep the third multiple of switching current harmonics lower than the
frequency where EMI standard is applying (i.e. 150 kHz). In next chapter, the measured
efficiency will be shown and the results will be discussed in details.

3.8. Conversion efficiency

Loss distribution for the designed converter with the specifications stated in TABLE 3-6 is
calculated and shown in Fig. 3.13 for different loads. As it can be seen, at full load the largest
losses are allocated to loss in the switches (about 60%) and then inductor copper loss (about
25%). As soon as the power goes down the importance of idle losses such as capacitive loss,
drive loss gets higher. For instance at 25% load, the idle loss contributes to more than 75% of
total losses as it can be seen in Fig. 3.13.

31
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

TABLE 3-5: Designed inductor for 25 kHz, 50 kHz, and 75 kHz.

Frequency Lc (mH) Core material Number of turns Core loss (W)* Copper loss (W)*
25 kHz 1.16 MPP-C055617 115 1.32 6.86
50 kHz 0.580 MPP- C055439 82 0.85 3.65
75 kHz 0.386 MPP- C055439 60 0.77 2.7
*The core and copper loss at full load are written.

Fig. 3.12: The loss distribution in the converter at full load for three difference frequencies.

The best balance between the losses in the converter has happened at full load. The
conduction loss, switching loss, and copper loss of the main inductor are dominant and equal
to each other; while at half load the dominant power loss belongs to the switching capacitive
loss. The SiC Schottky diodes can be used antiparallel with the SiC MOSFETs. These diodes
have better performance with respect to the reverse recovery losses compared to the body
diode of the SiC MOSFETs. However, the drop voltage across these diodes is higher in
higher current than the drop voltage of the SiC MOSFET body diode. More importantly,
adding these diodes causes an increase in the output capacitor of the switch which contributes
in switching loss. In next chapter, a comparison of the measured efficiency will be presented
by using SiC Schottky diode and not using them. The specifications of these diodes are listed
in TABLE 3-6 as well.

32
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

TABLE 3-6: Specifications of the components used in the converter.

Component Number Specifications

SiC
C2M0080120D [89]
Power MOSFET 6
Rds@60oC = 92 mŸ
Qoss@570V = 93.72 nC
SiC
Anti-Parallel Schottky 6 C4D15120A [91]
diode Qc @ 570 V = 68 nC
VF @ 15 A and 50oC = 1.6 V
Core MPP- C055439A2 [92]
Lc : 580 ȝH
Converter-side inductor 3 Number of turns: 82
Number of layers: 1 outer layer and 1.5 inner layer
Wire diameter: 1.42 mm
Metallized Polypropylene Film Capacitors-B32794
Filter capacitor 3
Cf : 2.5 ȝF : Cd
Damping capacitor 3
ESR : 14 mŸ @ 10 kHz
Core MPP- C055439A2
Lf : 100 ȝH,
Grid-side inductor 3 Number of turns: 32
Number of layers: 1
Wire diameter: 1.5
Damping resistor 3 Rd : 10 Ÿ

100
Conduction loss
Loss distribution (%)

80
Capacitive switching loss
60 Damping loss
Copper loss
40
Core loss
20

0
25% 50% 75% 100%
Load

Fig. 3.13: The loss distribution in 5 kW SiC based three-phase PFC based on different load.

3.9. Summary

In this chapter, the converter current and voltage of the three-phase PFC have been analyzed.
The following is a list of some of the conclusions and summary that can be drawn from the
analyses presented in this chapter:
x The maximum current ripple for converter-side inductor depending on dc link voltage
level can happen either at zero crossing or peak current.

33
CHAPTER III- TWO-LEVEL THREE-PHASE PFC

x If modulation index is higher than 0.845, then the maximum current ripple happens at
zero crossing.

x The derived equation for current ripple-(3.8)- can be used for sinusoidal pulse width
modulation (SPWM) and third harmonic PWM.

x The minimum filter capacitor is determined by current ripple introduced by the

converter-side inductor.

x It is shown that even at low switching frequency (e.g. 10 kHz) the filter capacitor by
this method is achieved about half of the maximum filter capacitor. Therefore, a
valuable margin is presented for the filter capacitor.

x The optimum damping resistor for LCL filter with RC damping branch increases when
the filter capacitor increases (i.e. damping capacitor reduces).

x Using line stabilization network (LISN) for designing the grid-side filter inductance
leads to an optimum filter in terms of size and loss.

x Using LISN for high frequency converters provides repeatable measurements for
designing and testing the designed LCL filter.

x MPP core materials among other materials such as Ferrite, Amorphous, Kool-Mȝ,
High Flux offers smaller core loss and presents lower dependency on dc pre-
magnetization for the power range of 5 kW. Special consideration must be taken to
avoid saturation in MPP cores.

x For a 5 kW three-phase PFC, the ac copper loss is negligible compared to the dc

copper loss. Therefore, the solid round wire is the best option for winding the
converter-side inductor.

x The distribution of the losses between switches and the filter is optimum around 50
kHz switching for a 5 kW SiC based three-phase PFC.

34
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

4. Control of Three-phase Power Factor Correction Rectifier

This section focuses on the controller of the power factor correction rectifier and the
influence of the controller choice on the conversion efficiency. Two types of current
controllers will be studied 1) PI current controller in the rotational dq reference frame and 2)
proportional resonant (PR) controller in the stationary DE reference frame. The reason why
two controllers have been studied in this work will be explained shortly.
Due to the nonlinearities of the converter such as the blanking time effect, the power quality
decreases, especially at low power level. Using the dq control without any harmonic
compensation has been found to require an increase in the value of the converter-side
inductance. In the previous chapter, the converter-side inductor was designed to have
maximum current ripple of 30%. However, this causes a serious reduction in power quality.
Therefore, the maximum allowed current ripple has been reduced to 15% to achieve an
acceptable harmonic performance at low frequencies (5th, 7th, 11th, 13th). This clearly changes
the power loss distribution in the converter.
On the contrary, the simplicity of employing a harmonic compensator (HC) in a PR controller
allows the maximum primary current ripple to be increased again to 30% while achieving the
same harmonic performance.
Here the impact of the current controller on the efficiency can be seen. In addition, having
better harmonic performance helps increasing the efficiency at low power which will also be
discussed in this chapter.

4.1. System description

The general schematic of the setup is shown in Fig. 4.1. The current controller is either the PI
or PR controller in the appropriate reference frame. The system consists of a three-phase SiC
based PFC connected via an LCL filter to the grid with passive damping. The LCL filter
contains a converter-side inductor (Lc), a grid-side inductor (Lg), a filter capacitor (Cf), and a
damping branch comprising a capacitor Cd in series with a damping resistor Rd. These filter
parameters have been designed in Chapter 3.

The purpose of employing the controller is to keep the dc link voltage constant, program the
current and power factor. The dc link voltage is controlled with an outer voltage loop and the
output is the reference current for the inner current loop. The control system consists of a dc
link voltage control loop with controller transfer function, Gc,dc(s), and a current control loop
with controller transfer function Gc(s). The design of the current control loop for the dq and
Įȕ control will be studied along with stability analyses. The dc link voltage control loop will
be the same for both current controllers and will be studied subsequently

4.2. Current controller

The current control loop is responsible for power quality and current protection. The block
diagram of the closed-loop system with Gc(s) as current controller is shown in Fig. 4.2(a). For

35
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Fig. 4.1: General schematic of the converter with controller.

improving the performance of the controller, the voltage at the point of common coupling
(vPCC) is usually used [66]. In this case, vPCC is added with a gain denoted as gcc.

The open loop transfer function of the system is then:

GOL ( s ) Gc s Gd s Yeq s (4.1)
where Yeq(s) is the admittance of the LCL filter along with the grid impedance seen from the
converter side [see Fig. 3.2]. Gd(s) is the transfer function of the pure time delay, O
introduced by the PWM, ADC conversions, and the computation. Thus
Gd s e  OTs s (4.2)
For realization of the feedforward, the block diagram in Fig. 4.2(a) has changed to Fig.
4.2(b). This change is done for simplifying the further analysis. PCC voltage is added to the
output of the current controller with a gain of gcc which can be set from 0 to 1. The open loop
transfer function of the system with feedforward compensation is as follows:

Gc s Yeq ( s )Gd s GOL s

GOLFF s (4.3)
1  g cc G s Gd s 1  g cc G s Gd s

where G(s) is:

G s g cc Z s Yeq ( s )
vPCC s ZC (4.4)
Z s Z Lgrid
i s ZC  Z Lf  Z Lgrid

According to the conclusion made in Appendix B6, feeding the PCC voltage as a feedforward
to the current control loop helps reducing the sensitivity of the controller to the grid
impedance. This improves the transient response of the current controller.

36
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

(a)

(b)
Fig. 4.2: (a) The block diagram of the PFC current control and (b) realization of feedforward effect as a block
diagram for further analysis.

4.2.1. PI current control in the dq reference frame

To eliminate any steady state error in the current control with a constant current reference, the
synchronous rotational reference or dq reference frame has been used. To control the power
factor, the q-axis current component must be controlled. Due to the presence of the filter
capacitor as it was mentioned in Section 3.3.2, the equivalent circuit from grid point of view
is capacitive.
To compensate for the reactive power absorbed by the filter capacitor, the q-axis reference
current cannot be set to zero. For designing this controller, the presented methods in
[45],[46],[53], and [66]-[68] are used. It should be noted that the purpose of this section is not
to introducing a new dq frame based control technique but to determine the conversion
efficiency using an already established controller.
The current in d-axis is controlled by the dc link voltage control loop. The schematic of the
controller has been shown in Fig. 4.3(a). The implementation of the PI current control loop is
also shown in Fig. 4.3(b).

Since the filter capacitor only deals with the switching frequency ripple, the influence of it is
neglected on the current controller [12], [45]. The LCL filter model and L filter model are
practically the same for frequency larger than half of the filter resonant frequency. Therefore,

37
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

(a)

(b)
Fig. 4.3: (a) the block diagram of the controller in the dq reference frame and (b) the block diagram of the PI
current controller.

the equivalent circuit shown in Fig. 3.2 can be simplified to Fig. 4.4. Accordingly, the grid
current can be written as follows:
dig
RT ig  LT vPCC t  van t (4.5)
dt
where RT = Rg+Rf+Rc, and LT = Lg+Lf+Lc. Analyzing the system in the synchronous rotating
reference frame, (4.5) will be written in d and q axis equations [46] as follows:

­ dig ,d
'VPCC ,d
 
° RT ig ,d  LT vPCC ,d  Z LT iq  van ,d
° dt
® 'VPCC ,q (4.6)
° dig ,q  
° RT ig ,q  LT vPCC ,q  Z LT id  van ,q
¯ dt
Therefore, the transfer function of the system can be written as follows:
I g ,dq s 1 RT
,W LT RT (4.7)
Van ,dq s 1W s

The converter current controller has transfer function, Gc(s), which is a PI controller in the dq
reference frame along with the delay, O contributed by the computation and the PWM
represented by transfer function (4.2). This delay is significant as it is normally of the order of
1.5 times the sampling time (Ts). The controller transfer function is:

38
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Fig. 4.4: Simplified equivalent circuit of filter and grid impedance.

(a) (b)
Fig. 4.5: The converter and grid current with PI controller in dq reference frame.

Gc s K p §¨ 1  1 ·¸ (4.8)
© sti ¹

where Kp, and ti are the controller parameters. According to (4.7) and (4.8), IJi = Ts and Kp is
calculated as follows:
LT
Kp , D t2 (4.9)
1.5D Ts
To study the stability of the converter, the impedance based analysis is performed together
with the impact of the PCC feedforward compensation [73] and the influence of filter
capacitor is also included in the analysis. The analysis of the stability has been thoroughly
investigated in Appendix B6. The impact of the PCC feedforward compensation has been
also examined in this paper.
The experimental results shown in Fig. 4.5 are the grid current and converter current for
different load conditions. Fig. 4.5(a) is the converter and grid current for 25% load and Fig.
4.5(b) shows the current for 100% load. As it can be seen, at low load, the converter current
ripple throughout the profile of main current is dominant. More specifically, the impact of
switching dead-time is clearer in the low load condition rather than the full load as it is
specified with three rectangular dashed lines for both cases.
4.2.1. PR control in the Įȕ reference frame
The schematic of the control system is shown in Fig. 4.6(a). To cancel the steady state error,
the stationary or the Įȕ reference frame is used. The control has a voltage outer loop which

39
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

provides the references for the inner current controller in the Įȕ reference frame. The
converter current controller transfer function, Gc(s), is now a proportional-resonant (PR)
controller along with the delay, Gd(s), from the computation and PWM defined by (4.2) [69].
The controller transfer function of the fundamental harmonic is as follows:

(a)

(b)

(c)
Fig. 4.6: (a) Implementation of the controller, (b) the current control loop, and (c) the implementation of
harmonic compensator in z-domain.

40
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

s
Gc s K p  Ki (4.10)
s  Zg 2
2

4.2.1.1. Implementation
To compensate for the nonlinearities of the converter due to the blanking time effect, low
frequency unwanted harmonics such as 5th, 7th, 11th, and 13th which are the largest in
magnitude are compensated with resonator controller. The general transfer function is written
as follows:
nth
s
Gc s K p  ¦ Ki,h (4.11)
h 1 s  Zh 2
2

The current control loop with harmonic compensators up to 13th harmonic is shown in Fig.
4.6(b). In this figure, the feedforward PCC voltage is also added to the current control loop
with the gain of gcc which can be adjusted between 0 and 1. If gcc is set to zero, the
feedforward compensation is removed. The frequency response of the open loop current
controller with and without feedforward is shown in Fig. 4.7. The control design is explained
in details in Appendix B7.
The implementation of the controller has been done in the z-domain in view of the digital
implementation. To minimize the phase shift introduced by the discretization, the integrator
in forward path is transformed to the z- domain using the forward Euler transform and the
integrator in the backward path is transformed to the z-domain using the Backward Euler
transform [71]. Fig. 4.6(c) shows the implementation of the controller in the z-domain.

To synchronize the system for the unbalance grid, the dual second order generalized
integrator (DSOGI) is used. This method is based on the second-order generalized integrator
(SOGI). The transfer function of SOGI is expressed as follows:
Zr s
C ( s) (4.12)
s  Zr 2
2

where Ȧr is the resonance angular frequency. The implementation of DSOGI has been
explained in [12] and [13].

Fig. 4.8 shows the controller response with different proportional gains. Fig. 4.8(a) shows a
more oscillatory system when the proportional gain is set to 15. Once the gain is reduced to
6.3 oscillatory behavior in the converter becomes more damped as can be seen in Fig. 4.8(b).
The comparison between the output of the PR controller for 50% of the load in Fig. 4.8(b)
and the full load response of the PI controller in Fig. 4.5(b), shows better current quality with
the PR controller.

41
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

(a)
100
Magnitude (dB)

50
Zg = 2.5%Zb

0
Zg = 10%Zb
-50

180
Phase (deg)

90
0

-90

100 1000
frequency (Hz)
(b)
Fig. 4.7: The frequency response of the open loop system for PR controller (a) without and (b) with feed forward
(gcc = 0.8).

(a) (b)
Fig. 4.8: (a) Oscillatory response, (b) more damped response of the grid current for different proportional gains.

42
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

4.2.1.1.Compensation
To compensate for the delay caused by PWM, AD conversion and computational delay,
compensation has been introduced to the controller for each harmonic compensator.
As mentioned, the feedforward compensation effect has been added with the gain of gcc in the
system. Therefore, the phase delay in the voltage measurement contributes to the output of
the current control. The phase delay impact on the PCC voltage can be written as follows:
 j TV TV ,delay
v ff gcc VPCC ‘ TV  TV ,delay gcc VPCC e (4.13)

where vff is the feedforward voltage as it is shown in Fig. 4.6(b). ɽv,delay is the phase delay
which is introduced by the voltage measurement and șV could be set to zero.
The output of the HC depends on the measured current as well as the reference current.
Therefore, two delays contribute in the path of the HCs; the delay from the measurement plus
the delay due to PWM. Then, the output of the HCs as called vRes (shown in Fig. 4.6(b)) is
calculated as follows:
 j T I T I ,delay
vRes VRes ‘ T I  T I ,delay 1  gcc VR e (4.14)

In this equation, ɽI,delay is the phase delay in the current path due to the measurement and the
PWM. Since the PCC voltage has contributed to the reference output voltage by the factor of
gcc, the contribution of the HCs will be (1-gcc). The target is to have unity power factor for the
converter and therefore șI can also be set to zero in (4.14). According to Fig. 4.6(b), the
reference output voltage is expressed as follows:
v* v ff  vRes (4.15)
Ideally, the normalized feedforward voltage (normalized with respect to VPCC) has the
magnitude of 1 and phase of zero. The difference between the feedforward voltage and the
ideal would be the compensation that vRes must provide.
vRes,Comp 1‘0$  v ff (4.16)
Corresponding to (4.16), the compensated resonator has an angle denoted as ɽVRes,Comp. Using
this angle and the real angle of the resonator without compensation, gives an angle that needs
to be added to the current controller for compensation as follows:
T comp. T v Res,Comp
 T vRes (4.17)
According to (4.16), the compensation can be easily added to the block diagram shown in
Fig. 4.6(c). Fig. 4.9(a) shows the implementation of the compensation to the HC. For the
implementation, the compensation gains are defined as follows:

43
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

sin hT comp.
K sin,h 2
hZ g (4.18)
K cos, h cos hT comp .

where Ksin,h is the compensation gain for hth harmonic on the path of the ȕ-axis and Kcos,h is
the compensation on the path of the Į-axis for the hth harmonic.

(a)

(b)

(c)
Fig. 4.9: (a) the implemented compensation for harmonic compensator, (b) frequency response of the open loop
system without phase compensation and (c) frequency response comparison for 13th harmonic.

44
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Fig. 4.10: The block diagram of the dc link voltage control loop including the current controller.

If in (4.18) the compensation angle is set to zero then the block diagram of the current
compensator will be the same as Fig. 4.6(c). Moreover, in (4.18), as the harmonic number
increases the compensation gain for the ȕ-axis increases while the compensation gain for the
Į-axis decreases. The impact of this compensation is more visible for higher harmonics as can
be seen in Fig. 4.9(b). For the designed controller, the angle at the 13th harmonic has reduced
from 134 degrees to 127 degrees using the compensation method. The importance of this
compensation becomes apparent when the number of HCs increases and their resonance
frequencies becomes closer to the cross over frequency of the controller.

4.3. DC voltage control loop

The block diagram of the dc voltage control loop is shown in Fig. 4.10. The bandwidth of the
voltage controller must be kept smaller than the current controller. The dc link voltage control
loop employs a PI controller with anti-windup implementation (not shown) to allow
saturation of the current reference during transients.
3Vm 1
Gdc s (4.19)
2 I load Cdc Rload s  1
§ ·
K p , dc ¨ 1  1
sti , dc ¸¹
Gc , dc s (4.20)
©
According to [68], the controller parameters are as follows:

2Vdc ref Cdc

K p ,dc
3D dcTinVm (4.21)
ti ,dc D dc Tin
2

Tin has been set to 5Ȝ (Ȝ is the time delay).

The step response of the system has been plotted for various grid impedances. It should be
noted that the target is to minimize differences between the step responses obtained for low-

45
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

TABLE 4-1: The parameters of the dc link controller for 2 case studies.

Parameters Lc = 580ȝH Lc = 1 mH
Įdc 5.5 4.2
Kp,dc 0.11 0.14
ti,dc 9msec 4.9msec
Overshoot range (%) 1-10
Settling time range (msec) 9.5-10.5

and high converter-side inductance values. TABLE 4-1 lists the parameters of the dc link
voltage controller in order to achieve this similar transient behavior. With reference to Fig.
4.11(a), increasing the grid impedance increases both the overshoot and the settling time.

(a)

(b)

(c)

Fig. 4.11: The performance of dc link control loop (a) general step response for different grid impedances, the
transient response of the dc link for (b) 564 V, and (c) 650 V.

46
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Modulation index

Fig. 4.12: : Reference converter voltage (vabc*-see Fig. 4.6(a)) and zero sequence offset.

However, it is desirable to keep the overshoot no higher than 10% for the largest grid
impedance. To study the stability of the converter with the dc link voltage control loop, two
different experimental tests have been conducted. Fig. 4.11(b) and (c) show the transient
response of the dc link voltage when the controller turns on for linear modulation and
overmodulation, respectively.

4.4. Experimental results

4.4.1. PFC rectifier connected to Drive

This section is dedicated to the experimental results that have been carried out in the Danfoss
Drive A/S laboratory. The experiments have been done by connecting the PFC to a fully SiC
based 7.5 kW drive from Danfoss (Danfoss FC302 7.5kW modified drive). For the drive, the
switches are all SiC implemented and the maximum switching frequency is 32 kHz. The
switching frequency of the PFC is 45 kHz. The PFC is connected via an auto-transformer to
the grid. The voltages at grid side are not balanced.
The linearity of the modulation index is extended by adding a zero sequence offset. The
calculated zero sequence offset is stored in dSPACE system. The results of this test have been
published and explained in Appendix B7.
It can be seen in Fig. 4.12 that to the complete zero sequence offset which is equal to the
maximum modulation index 2/¥3 there is a small difference and that is due to that the grid
voltage is not balance. To compensate for the unbalance grid, the dc link voltage is slightly
higher than normal condition as shown in Fig. 4.13(a). The Drive is connected to a motor test
bench which is able to drive the motor generative or regenerative. It should be noted that the
results are saved in dSPACE system and plotted in MATLAB.
Two tests have been carried out:
1) The torque is set to zero, and then it increases to 3 N.m and after about 4 seconds the
direction of torque changes to -3 N.m. This test shows the bidirectional power flow.
The results are shown in Fig. 4.13. As it can be seen, the dc link voltage in all the
transitions changes very smoothly. The overshoot in dc link voltage is not noticeable
and it reaches to steady state very fast. From Fig. 4.13(b), the direction of the d-axis

47
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

reference current is changing when the torque changes from positive to negative. In
the current also there is not a big overshoot as it is expected. Besides, this test also
shows the bidirectional power flow. It should be also noted that applying torque equal
to ±3 N.m is equivalent to 50% of PFC nominal power.
2) The torque is set to -6 N.m (regenerative), after 5 seconds the torque becomes zero
and after 10 seconds it changes to 6 N.m (generative). Fig. 4.14 shows the results.
Again it can be seen that the dc link does not have overshoot and in all the transitions
reaches to steady state very fast. In the last transition when the torque changes to 6
N.m, the current overshoot becomes larger than the current limit. Other words, the
limit for the current reference has been set to 10 A and it can be seen that id is
saturated when it reaches to this value. It can also be seen when the torque changes
from zero to 6 N.m, for fraction of a second, the measured dc link voltage does not
follow the reference voltage. That is because suddenly the demand increases on the
load side and until the grid current reaches to the demand the dc link voltage drops
from its reference value.

(a) (b)
Fig. 4.13: The experimental results of connecting PFC to Drive, torque from 3 N.m to -3 N.m (I: no torque, II:
positive torque, III: negative torque).
DC link voltage (V)

(a) (b)
Fig. 4.14: The experimental results of connecting PFC to Drive, changing torque 6 N.m to -6 N.m (I: negative
torque, II: zero torque, III: positive torque).

48
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

(a) (b)
Fig. 4.15: Nonlinearities of the converter at low load and high voltage for the 4-wire PFC (a) simulation results
and (b) experimental results.

4.4.2. Comparison of the controllers

4.4.2.1. Harmonic evaluation
Due to the nonlinearities of the converter, at low load and high voltage (nominal dc link
voltage), the current ripple dominates the main sinusoidal current component based on (3.8).
Therefore, the interval over which the current ripple causes rapidly repeated zero crossings
increases. In this case, the effect of the blanking time will be more obvious and the current
quality after the filtering is unsatisfactory. Fig. 4.15 shows an example of this condition both
in simulation and experiments. The test condition is that the dc link voltage is set to 565 V,
the grid current is 2 A peak. As it can be seen, the time interval over which the current ripple
causes rapidly repeated zero crossings is noticeable. There are two methods to improve the
quality of the current at low loads: either increase the converter-side inductance to yield lower
current ripple or improve the controller to mitigate the low frequency current harmonics (5th,
7th, 11th, …). Both methods have been investigated in this work and the results are shown in
Fig. 4.16.
In the first scenario, the converter side is increased to 1 mH to yield a 15% current ripple and
both the PI and the PR controller have been tested for this case. In the second scenario, the
inductance has been kept to yield a 30% current ripple (i.e. 580ȝH) and again the two
controllers are compared. The experimental results are shown for 25% load and 100% load
and the grid current waveform are shown in Fig. 4.16. With reference to Fig. 4.16(b), the grid
current with 580 ȝH inductance and PI controller presents the worst current waveform. A
comparison on THD performance is also presented in Fig. 4.17 for both scenarios. The THD
of the phase ‘a’ current has been compared.
According to Fig. 4.17, the best harmonic performance is obtained with the PR controller
when overmodulation occurs. The reason is that in overmodulation the dc link voltage is
better utilized and therefore according to (3.11) the current ripple will be reduced. Unlike
overmodulation, the linear modulation applies a larger voltage difference across the
converter-side inductance and causes a larger current ripple, thereby causing a more visible
effect in the harmonic performance.

49
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

(a) (b)

(c) (d)

(e) (f)

(g) (h)
Fig. 4.16: The experimental results of the grid current for different controllers and converter-side inductors (a)-
(d) 25% of nominal load and (e)-(h) for full load.

With a higher inductance value, the grid regulations for the low frequency harmonics are all
fulfilled. However, for a low inductance value, the grid regulations cannot be fulfilled within
the low load range using PI controller. In line with the objective of the project, the lowest
possible inductance value will eventually be chosen that yields an acceptable harmonic
performance at low frequencies. Using PI controller in this case shows weak harmonic
performance in comparison with PR controller for 580 ȝH. And that is the break point for the
efficiency and the impact of controller on the efficiency at low loads.

50
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Lc = 1 mH
6

THD % 4
PI LinMod.
3
PI OverMod.
2 PR LinMod.
1 PR OverMod.

0
25% 50% 75% 100%
Load
(a)
Lc = 580 ȝH
12
10
THD (%)

8
PI LinMod
6
PI OverMod
4
PR LinMod
2
PR OverMod
0
25% 50% 75% 100%
Load (%)

(b)
Fig. 4.17: The harmonic evaluation of the controllers with two different inductance value (a) Lc = 1 mH, (b) Lc =
580 ȝH.

4.4.2.2. Efficiency evaluation

The efficiency of the converter has been measured for both of the controllers to evaluate the
effect of these controllers on the conversion efficiency. The measurement was carried out
using a YOKOGAWA-WT3000 precision power analyzer for both the ac and dc sides. The
linear average mode of the measurement is active and taking averaging over 128 cycles. The
accuracy of the measurement for a 2 A current or lower (less than 20% load) is about 0.05%
and for higher than 2 A is about 0.00055%. Similarly, the voltage accuracy for the ac-side
voltage (peak of 325 V) is 0.00325% and for dc-side is 0.007%. After operating the system
for 45 minutes, the full load efficiency was measured. After 3-5 minutes, the measurement for
each load step was performed to make sure that the converter reached the steady state. Fig.
4.18 shows the experimental setup for the efficiency measurements. It should be noted that
for monitoring the accuracy of the measurements at the dc side, two precision multi-meter
(Agilent 34410A) have been used. For the dc current measurements, a high precision current
sensing resistor (precision 1 ppm/oC) was used for monitoring purpose. These two multi-
meters are synchronized with the power analyzer. The results using only the power analyzer
or using both the power analyzer for the ac measurement and the multi-meter for the dc
measurements are identical.

51
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Fig. 4.18: The experimental setup for measuring the efficiency.

99.1

99
Efficiency (%)

98.9

98.8
PR without diode
98.7 PR with diode
98.6

98.5
20 25 30 35 40
Load (%)

Fig. 4.19: The measured efficiency with and without diode at low load (25% < Load < 40%) for the PR control
(without including drive loss).

Fig. 4.20 shows the measured efficiency of the converter obtained with the PI and the PR
controllers (black and gray lines, respectively). The efficiency measurement has been
conducted in 4 different scenarios. Firstly, both controllers have been compared regarding
their impact on efficiency and secondly the SiC Schottky diodes have been removed and the
efficiency measurement repeated for both controllers. Due to the presence of the SiC
Schottky diodes, the total output charge of the diodes is added to the output charge of
MOSFETs and certainly the capacitive switching loss increases. Adding the SiC Schottky
diodes adds about 68 nC to the capacitive charge of the MOSFETs and it increases the
capacitive loss from 2.6 W for one switch to 4.56 W. This increase causes a reduction of
about 0.2% as idle loss. This reduction can easily be seen in Fig. 4.19 at low load. The impact
of diode for the whole range of loads for two different controllers is also shown in Fig. 4.20.

The presence of the Schottky diode at higher loads is not so evident. The forward drop
voltage of the body diode is smaller than the Schottky diode and the current at higher loads
will flow mostly through the body diode rather than the Schottky diode.

52
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

99

98.8
Efficiency (%)

98.6
PI contorller with diode
PR controller with diode
98.4

98.2

98
20 30 40 50 60 70 80 90 100
Load (%)
(a)
99.2

99

98.8
Efficiency (%)

98.6
PI controller without diode
PR controller without diode
98.4

98.2

98
20 30 40 50 60 70 80 90 100
Load (%)
(b)
Fig. 4.20: The efficiency curve for PI and PR controller (a) with SiC Schottky diode and (b) without SiC
Schottky diode.

The maximum efficiency occurs at 55% of the load for both of controller. For the PR
controller the maximum achievable efficiency is 99.1% and for the PI controller it is 99.08%.
As expected, because of better harmonic performance of the PR controller at lower load a
higher efficiency is achieved. Also, when the load is increased, the efficiencies obtained with
the two controllers become closer.

53
CHAPTER IV- CONTROL OF THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

The other observation for the efficiency curve is that with and without the anti-parallel diode
the efficiency is substantially flat for a wide range of loads. The efficiency at full load for
both cases is around 99%.

4.5. Summary

The following is a list of the main conclusion and summary that can be drawn from the
analyses presented in this chapter:
x Adding the PCC voltage to the control input is equally beneficial when using the PI or
PR current controllers;

x At low loads and high dc link voltages, the power quality is the lowest. Because, the
current ripple in the converter-side inductor is relatively large compared to the main
fundamental current and the effect of switching dead-time becomes more visible.

x The PR controller with harmonic compensation allows the value, and hence the size of
the converter-side inductor, to be reduced by a factor of 2/3.

x The measured conversion efficiency of the 5 kW SiC based three-phase PFC at half of
nominal load is about 99.1% and at full load it is 98.95%.

x Using SiC Schottky diodes anti-parallel with the MOSFETs increases the switching
loss by a factor of 70% for each switch. The contribution of the diode at high load is
very small because the forward voltage drop is higher than the SiC MOSFET body
diode.

x The impact of using different controllers on the efficiency is more obvious at low
loads. The PR controller shows better harmonic performance at low load than the PI
controller. Therefore, the efficiency at low load is also higher for the PR controller.

x Bidirectional power flow is provided for this converter and the performance is tested
by connecting the PFC converter to drive.

x The efficiency achieved is greater than the efficiencies most recently reported in the
literature representing the state of the art (see Chapter 2).

54
CHAPTER V- CONCLUSION AND FUTURE WORK

5. Conclusion and Future work

5.1. Conclusion

This PhD research work has presented a comprehensive design of a two-level three-phase
power factor correction (PFC) using silicon-carbide (SiC) devices to further increase
efficiency. To achieve the compliance with the grid standards (e.g. IEEE-519) an LCL filter
has been used for the PFC. A complete model of the filter is achieved by analyzing the
current and voltage waveform of each filter parameter. The converter current ripple has been
analyzed to choose the converter-side inductance. The analysis results are as follows:
x The converter current ripple waveform is generalized by categorizing its behavior into
two intervals with respect to the grid period. Interval 1 is 0 < Ȧt < ʌ/3 and interval 2 is
ʌ/3 < Ȧt < ʌ/2.

x Each time interval has its own maximum current ripple. For the first interval, the
maximum current ripple occurs at zero crossing. For the second interval, peak current
contains the maximum current ripple. For modulation index higher than 0.845, the
maximum current ripple occurs at zero crossing; otherwise, it occurs at peak current.

x A general equation has been derived for the maximum converter current ripple. This
expression is generalized for both the sinusoidal PWM and the third harmonic injected
PWM (THPWM).

Since the converter-side inductor is exposed to high frequency current ripple, the inductor
design is critical. MPP Powder core material is used, due to the low power loss and also
lower dependency on the dc pre-magnetization. For a 5 kW three-phase PFC, solid wire for
winding of this inductor is the best compromise between the simplicity and the loss. The ac
copper loss for switching side-band harmonics and its multiples is negligible in comparison
with the ac copper loss at the fundamental frequency.
Using the analysis for the converter current ripple, a minimum and a maximum margin for the
filter capacitance have achieved. The upper margin is defined by the absorbed reactive power
and the lower margin is achieved as a function of the maximum converter current ripple. It is
shown that even at low switching frequency (e.g. 10 kHz) the lower margin of the filter
capacitance is about half of the upper margin.
Line impedance stabilization network (LISN) provides a fixed impedance for the current
harmonics (at switching side-band harmonics and multiples). To optimize the grid-side filter
inductor, LISN is connected between the grid and the converter. The filter inductance is
derived as a function of the LISN impedance. The only way to find the minimum size of the
grid-side filter is using LISN, despite changing of the grid impedance. Using LISN also
assures that the measurements are repeatable.

55
CHAPTER V- CONCLUSION AND FUTURE WORK

To achieve the maximum efficiency, the loss distribution in the converter is analyzed for
different switching frequencies. Therefore, the switching frequency is selected to be in the
range of 45-50 kHz. Respecting electromagnetic interference (EMI), 45 kHz has finally been
selected as the switching frequency. According to the selected switching frequency, an LCL
filter is designed and the layout is optimized for a 5 kW three-phase PFC using SiC
MOSFETs.
Two types of current controllers are used: 1) PI controller in the rotational reference frame
and 2) Proportional-resonant (PR) controller in the stationary reference frame. The effect of
adding the point of common coupling (PCC) voltage to the current controller is studied (i.e.
feedforward compensation). The observations of studying the controllers are as follows:
x PI controller without harmonic compensation (HC) needs larger filter to obtain the
same harmonic performance as PR controller.

x With the same filter, the efficiency of the converter with PR controller is higher at low
loads.
The efficiency of the converter is measured for different scenarios. The efficiency is
measured with the PI controller and the PR controller. The efficiency is also measured with
and without SiC Schottky diode in parallel with the SiC MOSFETs. The following results are
achieved:
x The efficiency of the converter is higher without using the SiC Schottky diodes.

x For PR controller, a maximum efficiency of 99.1% is achieved at 50% of nominal

load. The measured efficiency at full load is 98.95%.

x The conversion efficiency is substantially flat for a wide range of loads for both
controllers.
The major contributions of this work can be summarized as follows:
x A complete analytical model for an LCL filter of two-level PFCs has been proposed.
This model can be extended for the multilevel converters. By using this model:

o Comparison between two-level and multilevel converters is analytically

possible.
o Comparison between the size of the filter for different modulation schemes is
possible.

x A high efficiency two-level PFC using SiC switches with the maximum efficiency of
99.1% has been achieved.

56
CHAPTER V- CONCLUSION AND FUTURE WORK

5.2. Future work

The following future work is suggested:

x Investigating active damping for the presented converters;

x Studying the impact of different modulation schemes on the efficiency and size of the
filter;

x Measure the efficiency of the converter in the bidirectional operation;

x Analytical common mode filter design for PFCs;

x In this PhD work, a three-level PFC using Gallium-Nitride (GaN) switches has also
been designed. The design process and specifications of the designed converter have
been described in Appendix A. Comparing the two-level SiC based converter from
different aspects with three-level GaN based converter can be very interesting. Filter
size, EMI performance, and efficiency are the main interests of this comparison.

57
REFERENCES

References
[1] B. Singh, B.N. Singh, A. Chandra; K. Al-Haddad, A. Pandey, D.P. Kothari, "A review of three-phase
improved power quality AC-DC converters," in IEEE Transactions on Industrial Electronics, vol. 51,
no. 3, pp. 641-660, June 2004.
[2] J. W. Kolar and T. Friedli, "The Essence of Three-Phase PFC Rectifier Systems—Part I," in IEEE
Transactions on Power Electronics, vol. 28, no. 1, pp. 176-198, Jan. 2013.
[3] T. Friedli, M. Hartmann and J. W. Kolar, "The Essence of Three-Phase PFC Rectifier Systems—Part
II," in IEEE Transactions on Power Electronics, vol. 29, no. 2, pp. 543-560, Feb. 2014.
[4] M.H, Rashid, "Power Electronics handbook," Academic Press, 2001, pp. 181-193.
[5] J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas, J. Rebollo, "A survey of wide bandgap power
semiconductor devices," in IEEE Transactions on Power Electronics, vol. 29, pp. 2155 – 2163, May
2014.
[6] N. Kaminski, O. Hilt, "SiC and GaN Devices - Wide Bandgap is not all the same," in IET Circuits,
Devices & Syst., Vol. 8, Iss. 3, pp.227-236, 2014.
[7] Heena Jain; Rajawat, S.; Puja Agrawal, "Comparision of wide band gap semiconductors for power
electronics applications," Recent Advances in Microwave Theory and Applications, 2008.
MICROWAVE 2008. International Conference on, vol., no., pp.878-881, Nov. 2008.
[8] A. Marzoughi, R. Burgos, D. Boroyevich, "Characterization and comparison of latest generation 900-V
and 1.2-kV SiC MOSFETs," in Energy Conversion Congress and Exposition (ECCE), 2016 IEEE, vol.,
no., pp., 18-22 Sept. 2016.
[9] IEEE Recommended Practice and Requirements for Harmonic Control in Electric Power Systems,"
in IEEE Std 519-2014 (Revision of IEEE Std 519-1992) , vol., no., pp.1-29, June 11 2014.
[10] D.G. Holmes, T.A. Lipo, Pulse width modulations for power converters: principles and practice, Wiley
publication, 2003.
[11] H. Mao; F.C. Lee, D. Boroyevich, S. Hiti, "Review of high-performance three-phase power-factor
correction circuits, " in IEEE Transactions on Industrial Electronics, vol. 44, no. 4, pp.437-446, Aug
1997.
[12] Remus Teodorescu, Marco Liserre, Pedro Rodriguez, "Grid Converters for Photovoltaic and Wind
Power Systems," Wiley-IEEE Press, 2011.
[13] Gonzalo Abad, "Power Electronics and Electrical Drives for Traction Applications," Wiley-IEEE Press,
2017, pp.200-230.
[14] Francesco Lattarulo, "Electromagnetic Compatibility in Power Systems," Design of line front-end
converter systems under real line conditions-Chapter 8, 1st edition, Elsevier Ltd. 2007.
[15] Power conversion and line filter applications, Application note, pp. 58-60, 2002.
[16] S. Piasecki and J. Rąbkowski, "The 10 kVA SiC-based grid connected AC/DC converter with extended
functionalities — Experimental investigation," 2016 10th International Conference on Compatibility,
Power Electronics and Power Engineering (CPE-POWERENG), Bydgoszcz, 2016, pp. 214-218.
[17] S. Pisecki and J. Rąbkowski, "Experimental investigations on the grid-connected AC/DC converter
based on three-phase SiC MOSFET module," Power Electronics and Applications (EPE'15 ECCE-
Europe), 2015 17th European Conference on, Geneva, 2015, pp. 1-10.
[18] B. Burger and D. Kranzer, "Extreme high efficiency PV-power converters," Power Electronics and
Applications, 2009. EPE '09. 13th European Conference on, Barcelona, 2009, pp. 1-13.
[19] S. Piasecki, R. Szmurla, J. Rabkawski, M. Jasinski, "Dedicated system for design, analysis and
optimization of the AC-DC converters", Bulletin of the Polish Academy of Science, 2016.
[20] Yimin Jiang, Hengchun Mao, F. C. Lee and D. Borojevic, "Simple high performance three-phase boost
rectifiers," Power Electronics Specialists Conference, PESC '94 Record., 25th Annual IEEE, Taipei,
1994, pp. 1158-1163, vol.2.
[21] A. Stupar T. Friedli J. Miniböck J. W. Kolar, "Towards a 99% Efficient Three-Phase Buck-Type PFC
Rectifier for 400-V DC Distribution Systems," in IEEE Transactions on Power Electronics, vol. 27, no.
4, pp. 1732-1744, April 2012.
[22] F. Xu, B. Guo, L. M. Tolbert, F. Wang and B. J. Blalock, "An All-SiC Three-Phase Buck Rectifier for
High-Efficiency Data Center Power Supplies," in IEEE Transactions on Industry Applications, vol. 49,
no. 6, pp. 2662-2673, Nov.-Dec. 2013.
[23] M. Schweizer and J. W. Kolar, "Design and Implementation of a Highly Efficient Three-Level T-Type
Converter for Low-Voltage Applications," in IEEE Transactions on Power Electronics, vol. 28, no. 2,
pp. 899-907, Feb. 2013.

58
REFERENCES

[24] N. McNeill, X. Yuan and P. Anthony, "High-Efficiency NPC Multilevel Converter Using Super-
Junction MOSFETs," in IEEE Transactions on Industrial Electronics, vol. 63, no. 1, pp. 25-37, Jan.
2016
[25] J.W. Kolar, H. Ertl, F.C. Zach, “Design and Experimental Investigation of a Three-Phase High Power
Density High Efficiency Unity Power Factor PWM (Vienna) Rectifier Employing a Novel Integrated
Power Semiconductor Module, ” Proceedings of the 11th IEEE Applied Power Electronics Conference,
San Jose (CA), USA, March 3-7, Vol.2, pp.514-523 (1998).
[26] T. B. Soeiro, J. W. Kolar, "Analysis of High-Efficiency Three-Phase Two- and Three-Level
Unidirectional Hybrid Rectifiers," in IEEE Transactions on Industrial Electronics, vol. 60, no. 9, pp.
3589-3601, September 2013.
[27] F. Xu et al., "Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated
Inverter," in IEEE Transactions on Power Electronics, vol. 28, no. 3, pp. 1464-1478, March 2013.
[28] H. M. Suryawanshi, M. R. Ramteke, K. L. Thakre and V. B. Borghate, "Unity-Power-Factor Operation
of Three-Phase AC–DC Soft Switched Converter Based On Boost Active Clamp Topology in Modular
Approach," in IEEE Transactions on Power Electronics, vol. 23, no. 1, pp. 229-236, Jan. 2008.
[29] L. Ma, T. Kerekes, P. Rodriguez, X. Jin, R. Teodorescu and M. Liserre, "A New PWM Strategy for
Grid-Connected Half-Bridge Active NPC Converters With Losses Distribution Balancing Mechanism,"
in IEEE Transactions on Power Electronics, vol. 30, no. 9, pp. 5331-5340, Sept. 2015.
[30] S. Basu, T. Undeland, "Inductor design considerations for optimizing performance & cost of
continuous mode boost PFC converters," Applied Power Electronics Conference and Exposition
(APEC), vol.2, pp.1133-1138, 6-10 March 2005.
[31] R. Burkart, H. Uemura, J. Kolar, “Optimal inductor design for 3-phase voltage-source PWM converters
considering different magnetic materials and a wide switching frequency range,” Power Electronics
Conference (IPEC-Hiroshima), pp. 891-898, May 2014.
[32] C.W.T. McLyman, "Transformer and inductor design handbook," 4th edition, Taylor & Francis Group,
2011, pp. 2-4, 2-53.
[33] R. Beres, X. Wang, F. Blaabjerg, C. L. Bak, H. Matsumori and T. Shimizu, "Evaluation of core loss in
magnetic materials employed in utility grid AC filters," 2016 IEEE Applied Power Electronics
Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 3051-3057.
[34] Magnetics Technical documents, “Powder Cores”, 2015.
[35] Ferroxcube, 3C94 Material specification, Sep 2008.
[36] TDK, Large Size Ferrite Cores for High Power, Nov. 2010.
[37] Hitachi Metals, Powerlite C-Cores, 2605SA1.
[38] Micrometals Iron Powder Cores, Power conversion and line filter applications, issue L, Feb 2007.
[39] T. Shimizu, S. Iyasu, "A Practical Iron Loss Calculation for AC Filter Inductors Used in PWM
Inverters," in IEEE Transactions on Industrial Electronics, vol. 56, no. 7, pp. 2600-2609, July 2009.
[40] M. Biglarbegian, N. Shah, I. Mazhari, J. Enslin and B. Parkhideh, "Design and evaluation of high
current PCB embedded inductor for high frequency inverters," 2016 IEEE Applied Power Electronics
Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 2998-3003.
[41] M. Biglarbegian, N. Shah, I. Mazhari and B. Parkhideh, "Design considerations for high power
density/efficient PCB embedded inductor," 2015 IEEE 3rd Workshop on Wide Bandgap Power Devices
and Applications (WiPDA), Blacksburg, VA, 2015, pp. 247-252.
[42] Jinjun Liu; T.G. Wilson, R.C. Wong, R. Wunderlich, F.C. Lee, "A method for inductor core loss
estimation in power factor correction applications," Applied Power Electronics Conference and
Exposition, APEC, vol. 1, pp. 439-445, 2002.
[43] IEEE Recommended Practice and Requirements for Harmonic Control in Electric Power Systems -
Redline," in IEEE Std 519-2014 (Revision of IEEE Std 519-1992) - Redline , vol., no., pp.1-213, June
11 2014.
[44] L. Wei and R. A. Lukaszewski, "Optimization of the Main Inductor in a LCL Filter for Three Phase
Active Rectifier," Industry Applications Conference, 2007. 42nd IAS Annual Meeting. Conference
Record of the 2007 IEEE, New Orleans, LA, 2007, pp. 1816-1822.
[45] M. Liserre, F. Blaabjerg, S. Hansen, "Design and control of an LCL-filter-based three-phase active
rectifier," in IEEE Transactions on Industry Applications, vol. 41, no. 5, pp. 1281-1291, Oct. 2005.
[46] K. Jalili, S. Bernet, "Design of LCL Filters of Active-Front-End Two-Level Voltage-Source
Converters," in IEEE Transactions on Industrial Electronics, vol.56, no.5, pp.1674-1689, May 2009.
[47] Weimin Wu, Yuanbin He, Tianhao Tang, F. Blaabjerg, "A New Design Method for the Passive
Damped LCL and LLCL Filter-Based Single-Phase Grid-Tied Inverter," in IEEE Transactions on
Industrial Electronics, vol.60, no.10, pp.4339-4350, Oct. 2013.

59
REFERENCES

[48] P. Channegowda and V. John, "Filter Optimization for Grid Interactive Voltage Source Inverters,"
in IEEE Transactions on Industrial Electronics, vol. 57, no. 12, pp. 4106-4114, Dec. 2010.
[49] J. Muhlethaler, M. Schweizer, R. Blattmann, J.W. Kolar, A. Ecklebe, "Optimal Design of LCL
Harmonic Filters for Three-Phase PFC Rectifiers," in IEEE Transactions on Power Electronics, vol.
28, no. 7, pp. 3114-3125, July 2013.
[50] R. N. Beres, X. Wang, F. Blaabjerg, M. Liserre and C. L. Bak, "Optimal Design of High-Order
Passive-Damped Filters for Grid-Connected Applications," in IEEE Transactions on Power
Electronics, vol. 31, no. 3, pp. 2083-2098, March 2016.
[51] L. Shen, G. Asher, P. Wheeler and S. Bozhko, "Optimal LCL filter design for 3-phase Space Vector
PWM rectifiers on variable frequency aircraft power system," Power Electronics and Applications
(EPE), 2013 15th European Conference on, Lille, 2013, pp. 1-8.
[52] J. Verveckken, J. F. Silva and J. Driesen, "Optimal analytic LCL filter design for grid-connected
voltage-source converter," EUROCON, 2013 IEEE, Zagreb, 2013, pp. 823-830.
[53] M. Liserre, F. Blaabjerg, A. Dell Aquila, "Step-by-step design procedure for a grid-connected three-
phase PWM voltage source converter," International Journal of Electronics, vol. 91, no. 8, pp. 445-
460, Aug 2004.
[54] M. Liserre, A. Dell'Aquila and F. Blaabjerg, "Genetic algorithm-based design of the active damping for
an LCL-filter three-phase active rectifier," in IEEE Transactions on Power Electronics, vol. 19, no. 1,
pp. 76-86, Jan. 2004.
[55] A. Rockhill, M. Liserre, R. Teodorescu and P. Rodriguez, "Grid-filter design for a multimegawatt
medium-voltage voltage-source inverter," in IEEE Transaction on Industrial Electronics, vol. 58, pp.
1205-1217, 2011.
[56] D. Jovcic, Lu Zhang, M. Hajian, "LCL VSC Converter for High-Power Applications," in IEEE
Transaction on Power Delivery, vol.28, no.1, pp.137-144, Jan. 2013.
[57] R. Pena-Alzola, M. Liserre, F. Blaabjerg, R. Sebastián, J. Dannehl, F. W. Fuchs, "Analysis of the
passive damping losses in LCL-filter based grid converters," in IEEE Transaction on Power
Electronics, vol. 28, no. 6, pp. 2642-2646, 2013.
[58] Y. Jiao and F. C. Lee, "LCL Filter Design and Inductor Current Ripple Analysis for a Three-Level NPC
Grid Interface Converter," in IEEE Transactions on Power Electronics, vol. 30, no. 9, pp. 4659-4668,
Sept. 2015.
[59] R. N. Beres, X. Wang, M. Liserre, F. Blaabjerg and C. L. Bak, "A Review of Passive Power Filters for
Three-Phase Grid-Connected Voltage-Source Converters," in IEEE Journal of Emerging and Selected
Topics in Power Electronics, vol. 4, no. 1, pp. 54-69, March 2016.
[60] W. Wu et al., "A Robust Passive Damping Method for LLCL-Filter-Based Grid-Tied Inverters to
Minimize the Effect of Grid Harmonic Voltages," in IEEE Transactions on Power Electronics, vol. 29,
no. 7, pp. 3279-3289, July 2014.
[61] M. Huang, X. Wang, P. C. Loh and F. Blaabjerg, "LLCL-Filtered Grid Converter With Improved
Stability and Robustness," in IEEE Transactions on Power Electronics, vol. 31, no. 5, pp. 3958-3967,
May 2016.
[62] J. Rabkowski, S. Piasecki and M. P. Kazmierkowski, "Design of a three-phase AC/DC converter with
paralleled SiC MOSFETs," Power Electronics and Motion Control Conference and Exposition
(PEMC), 2014 16th International, Antalya, 2014, pp. 533-539.
[63] S. Piasecki, "High order line filters for Grid Connected AC-DC Converter — Parameters selection and
optimization," 2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE), Istanbul,
2014, pp. 2691-2696.
[64] S. Piasecki, A. M. Cantarellas, J. Rabkowski and P. Rodriguez, "Design of AC-DC power converters
with LCL + tuned trap line filter using Si IGBT and SiC MOSFET modules," Industrial Electronics
Society, IECON 2013 - 39th Annual Conference of the IEEE, Vienna, 2013, pp. 5957-5962.
[65] Y. Patel, D. Pixler, A. Nasiri, "Analysis and design of TRAP and LCL filters for active switching
converters," Industrial Electronics (ISIE), IEEE International Symposium on, pp.638-643, July 2010.
[66] F. Blaabjerg, R. Teodorescu, M. Liserre and A. V. Timbus, "Overview of Control and Grid
Synchronization for Distributed Power Generation Systems," in IEEE Transactions on Industrial
Electronics, vol. 53, no. 5, pp. 1398-1409, Oct. 2006.
[67] A. Timbus, M. Liserre, R. Teodorescu, P. Rodriguez and F. Blaabjerg, "Evaluation of Current
Controllers for Distributed Power Generation Systems," in IEEE Transactions on Power Electronics,
vol. 24, no. 3, pp. 654-664, March 2009.
[68] M. Liserre, A. Dell'Aquila, F. Blaabjerg, "Stability improvements of an LCL-filter based three-phase
active rectifier," Power Electronics Specialists Conference, vol.3, pp.1195-1201, 2002.

60
REFERENCES

[69] R. Teodorescu, F. Blaabjerg, M. Liserre and P. C. Loh, "Proportional-resonant controllers and filters
for grid-connected voltage-source converters," in IEE Proceedings - Electric Power Applications, vol.
153, no. 5, pp. 750-762, September 2006.
[70] D. G. Holmes, T. A. Lipo, B. P. McGrath and W. Y. Kong, "Optimized Design of Stationary Frame
Three Phase AC Current Regulators," in IEEE Transactions on Power Electronics, vol. 24, no. 11, pp.
2417-2426, Nov. 2009.
[71] S. A. Richter and R. W. De Doncker, "Digital proportional-resonant (PR) control with anti-windup
applied to a voltage-source inverter," Power Electronics and Applications (EPE 2011), Proceedings of
the 2011-14th European Conference on, Birmingham, 2011, pp. 1-10.
[72] M. Liserre, R. Teodorescu, F. Blaabjerg, "Stability of photovoltaic and wind turbine grid-connected
inverters for a large set of grid impedance values," in IEEE Transactions on Power Electronics, vol.21,
no.1, pp.263-272, Jan. 2006.
[73] X. Wang, F. Blaabjerg and P. C. Loh, "Proportional derivative based stabilizing control of paralleled
grid converters with cables in renewable power plants," 2014 IEEE Energy Conversion Congress and
Exposition (ECCE), Pittsburgh, PA, 2014, pp. 4917-4924.
[74] L. Harnefors, L. Zhang, and M. Bongiorno, "Frequency-domain passivity-based current controller
design," IET Power Electron., vol. 1, no. 4, pp. 455–465, Dec. 2008.
[75] Y. Tang, W. Yao, P. C. Loh and F. Blaabjerg, "Design of LCL Filters With LCL Resonance
Frequencies Beyond the Nyquist Frequency for Grid-Connected Converters," in IEEE Journal of
Emerging and Selected Topics in Power Electronics, vol. 4, no. 1, pp. 3-14, March 2016.
[76] R. Peña-Alzola, M. Liserre, F. Blaabjerg, M. Ordonez and Y. Yang, "LCL-Filter Design for Robust
Active Damping in Grid-Connected Converters," in IEEE Transactions on Industrial Informatics, vol.
10, no. 4, pp. 2192-2203, Nov. 2014.
[77] S. G. Parker, B. P. McGrath and D. G. Holmes, "Regions of Active Damping Control for LCL Filters,"
in IEEE Transactions on Industry Applications, vol. 50, no. 1, pp. 424-432, Jan.-Feb. 2014.
[78] A. M. Hava, R. J. Kerkman and T. A. Lipo, "Carrier-based PWM-VSI overmodulation strategies:
analysis, comparison, and design," in IEEE Transactions on Power Electronics, vol. 13, no. 4, pp. 674-
689, Jul 1998.
[79] A. M. Trzynadlowski and S. Legowski, "Minimum-loss vector PWM strategy for three-phase
inverters," in IEEE Transactions on Power Electronics, vol. 9, no. 1, pp. 26-34, Jan 1994.
[80] A. M. Hava, R. J. Kerkman and T. A. Lipo, "Simple analytical and graphical methods for carrier-based
PWM-VSI drives," in IEEE Transactions on Power Electronics, vol. 14, no. 1, pp. 49-61, Jan 1999.
[81] How to fine tune your SiC MOSFET gate driver to minimize losses, App. Note AN4671, pp. 1-17.
[82] Cree, "SiC MOSFET isolated gate driver," February 2011, pp. 1-6.
[83] S. Prabhakaran and C. R. Sullivan, "Impedance-analyzer measurements of high-frequency power
passives: techniques for high power and low impedance," Industry Applications Conference, 2002. 37th
IAS Annual Meeting. Conference Record of the, Pittsburgh, PA, USA, 2002, pp. 1360-1367 vol.2.
[84] B. Carsten, "Calculating the high frequency resistance of single and double layer toroidal windings,"
Home applications, MicroMetals, 2002.
[85] L. Malesani, L. Rossetto, P. Tenti and P. Tomasin, "AC/DC/AC PWM converter with reduced energy
storage in the DC link," in IEEE Transactions on Industry Applications, vol. 31, no. 2, pp. 287-292,
Mar/Apr 1995.
[86] G. Gohil, L. Bede, R. Teodorescu, T. Kerekes and F. Blaabjerg, "Analytical method to calculate the DC
link current stress in voltage source converters," Power Electronics, Drives and Energy Systems
(PEDES), 2014 IEEE International Conference on, Mumbai, 2014, pp. 1-6.
[87] J. Muhlethaler, J. Biela, J.W. Kolar, A. Ecklebe, "Core losses under the DC bias condition based on
Steinmetz parameters," in IEEE Transactions on Power Electronics, vol. 27, no. 2, pp. 953-963, February
2012.
[88] J. Muhlethaler, J. Biela, J.W. Kolar, A. Ecklebe, "Improved Core-Loss Calculation for Magnetic
Components Employed in Power Electronic Systems," Power Electronics, IEEE Transactions on, vol. 27,
no. 2, pp. 964,973, Feb. 2012.
[89] Cree, "C2M0080120D Silicon Carbide Power MOSFET- C2M MOSFET," Rev. C, October 2015.
[90] IXYS corporation, "IXFB30N120P Polar HiPerFET Power MOSFET," DS99825B, 2010.
[91] Cree, "C4D15120A Silicon Carbide Schottky Diode- Z-Rectifier," Rev. B, 2014.
[92] Magnetics, "C055439A2," October 2013.
[93] Rodriguez, L.G. Franquelo, S. Kouro, J. Leon, R. Portillo, M. Prats, M. Perez, “Multilevel converters:
an enabling technology for high power applications,” Proceeding of the IEEE, vol. 97, no. 11, pp. 1786-
1817, Nov. 2009.

61
REFERENCES

[94] T.B. Soeiro, J.W. Kolar, “The new high efficiency hybrid neutral point clamped converter,” IEEE
Trans. Industrial Elec., vol. 60, no. 5, pp. 1919-1935, May 2013.
[95] F.Z. Peng, “A generalized multilevel inverter topology with self-voltage balancing,” in IEEE
Transactions on Industry Applications, vol. 37, no. 2, pp. 611-618, 2001.
[96] T. Bruckner, “The active NPC converter for medium voltage drives,” PhD dissertation, Technical
University of Dresden, 2006.
[97] T. Bruckner, S. Bernet, H. Guldner, “The active NPC converter and its loss balancing control,” IEEE
Trans. Industrial Elec., vol. 52, no. 3, pp. 855-868, June 2005.
[98] P. Barbosa, P. Steimer, J. Steinke, M. Winkelnkemper and N. Celanovic, "Active-neutral-point-
clamped (ANPC) multilevel converter technology," Power Electronics and Applications, 2005 European
Conference on, Dresden, 2005.
[99] V. Dargahi, Khoshkbar, M. Abarzade, S. Eskandari, K.A. Corzine,"A New Family of Modular
Multilevel Converter Based on Modified Flying-Capacitor Multicell Converters," IEEE Tans. Power
Electroncis, vol. 30, no. 1, Jan 2015.
[100] A. Marzoughi, R. Burgos, D. Boroyevich and Y. Xue, "Steady-state analysis of voltages and
currents in modular multilevel converter based on average model," 2015 IEEE Energy Conversion
Congress and Exposition (ECCE), Montreal, QC, 2015, pp. 3522-3528.
[101] A. Marzoughi, R. Burgos, D. Boroyevich and Y. Xue, "Design and comparison of cascaded H-
bridge, modular multilevel converter and 5-L active neutral point clamped topologies for drive
application," 2015 IEEE Energy Conversion Congress and Exposition (ECCE), Montreal, QC, 2015, pp.
4033-4039.
[102] A. Marzoughi, R. Burgos, D. Boroyevich and Y. Xue, "Investigation and design of modular
multilevel converter in AFE mode with minimized passive elements," 2015 IEEE Energy Conversion
Congress and Exposition (ECCE), Montreal, QC, 2015, pp. 6770-6776.

62
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

A. Three-Level Three-Phase Power Factor Correction Rectifier

This chapter presents a hybrid three-level converter which utilizes generalized multilevel
concept to achieve low power losses and equally distributed losses among the active switches.
In generalized three-level converter and active neutral point clamped converter (ANPC), six
active switches are employed. Using this switching strategy, only two of six switches are
switched with high frequency and the rest are switched with low frequency (i.e. grid
frequency). Therefore, two different frequencies bring an opportunity to use two different
technologies for switches. For two high frequency switches, low switching loss-high
frequency gallium-nitride (GaN) FET is used which helps more to reduce the switching loss.
For low frequency switches, the conventional silicon MOSFET is employed.

A. 1. Introduction

Multilevel converters have become interesting solution for high voltage, high power
applications [93]-[102]. Lower common mode voltage, lower stress on power
semiconductors, and higher quality of current and voltage have changed them into serious
rivals of two-level converters [93],[94]. Although neutral point clamped converter (NPC) was
firstly proposed for medium voltage industry applications, this topology is now used for low
voltage drive applications as well. However, this topology among all its advantages offers
one substantially weakness which is an unequal distribution of the switching loss between the
power semiconductor devices. To overcome this problem, active NPC (ANPC) is introduced
to share the losses between active switches equally, even though number of active switches is
increased from 4 to 6 in three-level ANPC [95], [96]. In 2001, Peng presented a general
topology of multilevel converter in which NPC, flying capacitor and ANPC converter can be
driven from that topology and is called generalized multilevel converter [95]. This topology
has interesting features that can be used to improve the overall efficiency of multilevel
converters. In [98], a new topology of 5 level converter has been proposed which uses the
idea of NPC and flying capacitor to generate five level converter. In 5 level ANPC (5L-
ANPC), there are two different switching frequencies, the higher voltage switches are
switching with grid frequency and the lower voltage switches are switching with higher
frequency. Therefore, the switching loss in high voltage switches is almost negligible and
only their conduction loss contributes to the overall loss of the converter.
GaN FETs are not commercially available for high voltage which makes them suitable for
multilevel applications. Combining the idea behind generalized multilevel concept or 5L-
ANPC, and different semiconductor technology can be beneficial from conversion efficiency
as well as power density of the converter. This work uses this combination and is built a
hybrid ANPC (HANPC) in which GaN FETs are used for high frequency switches and
normal Si are used for low frequency ones.

63
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

Fig. A.1: The schematic of three-level three-phase active NPC.

A. 2. Three-level ANPC

The schematic of a three-level active NPC is shown in Fig. A.1. Switches S1-S4 are the low
frequency switches and Q1 and Q2 are the high frequency switches. When the voltage
reference is positive, switches S1 and S3 are in turn-on state. When Q1 is turn-on, the ac link is
connected to the positive rail and when it is turn-off, the path of the current is
correspondingly provided via S3 and Q2 and the connection to the dc link midpoint is
achieved. Similar scenario can be explained for negative reference voltage, when the
complementary of S1 and S3 are now in turn-on state (i.e. S2 and S4). In this case, when Q1 is
turn-on, the zero state is provided and when Q2 is turn-on the negative rail is connected to the
ac link. Although there are 6 active switches in each leg, sever switching losses occur only for
two high frequency switches and the other 4 switches are not facing high switching frequency
loss. The switching states have been listed in TABLE A-1 [98].

A. 3. Hybrid three-level ANPC

In ANPC, existing two switching frequencies leads to use two different types of switches.
Therefore, for Q1 and Q2, GaN FET is interesting choice. For low frequency switches, Si
MOSFET can be employed in the circuit. Therefore, this converter is called hybrid active
NPC (HANPC). To demonstrate the performance and superiority of HANPC, a 10 kW three-
TABLE A-1: Switching state of the generalized three-level converter.

State S1 & S3 S2 & S4 Q1 Q2

State “+” 1 0 1 0
0 (positive half cycle) 1 0 0 1
0 (negative half cycle) 0 1 1 0
State “—“ 0 1 0 1

64
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

TABLE A-2: The converter specifications

Parameter Description Value

Pnom Nominal power 10 kW
Vac Ac voltage 230 V
Vdc DC link voltage 650 V
fg Grid frequency 50 Hz
fsw Switching frequency 100 kHz
Lc Inductance 133 ȝH
Cdc DC link capacitor 144 ȝF

phase hybrid generalized three-level converter has been built. The specifications of the
converter are listed in TABLE A-2. This converter consists of two GaN FETs- 650 V, 60 A-
and four Si MOSFETs- 650 V, 130 A. The schematic of one leg of the converter (i.e. 3.3 kW
single phase schematic) along with the built prototype are shown in Fig. A.2(b). The
advantage of using high voltage GaN is that there is no need for antiparallel diode. Because,
firstly GaN FETs are capable of reverse conduction even though they do not have parasitic
body diode construction. Secondly, by adding another diode in parallel with switch, the
output capacitive charge of the switch increases and it increases the switching loss. In
addition, the reverse conduction of GaN FETs does not have recovery losses which means
during the dead time between Q1 and Q2 the transition is lossless.

A. 4. Loss distribution

A. 4.1. Inductor design and loss calculation

The converter works in the linear region of the modulation index. The process of calculating
the current ripple is very similar to the one which is presented for two-level PFC in Section
3.3.1.
Si
+ S1 D1
GaN
Vdc/2 Cdc1 Cc-Si
S2 Q1
D2

ia
N
Lc
S3 D3
Q2
5c

cm
m

Vdc/2 Cdc2 Cc-Si

5

S4 D4
-
(a) (b)
Fig. A.2: (a) the schematic of one phase of three-level HANPC, (b) the build prototype of one leg three-level
HANPC.

65
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

TABLE A-3: The ac resistance of the copper winding for 136 ȝH inductor

Frequency 50 Hz 100 kHz 200 kHz 300 kHz

Total
AC resistance (mŸ) 23 460 678 858
Copper loss (W)@full load 5.17 0.16 0.052 §0 5.4
Copper loss (W)@half load 1.13 0.13 0.04 §0 1.3

Using these time intervals, the current ripple can be obtained as [ac peak voltage (Vm), and
inductance value (L), fsw is the switching frequency].
Vdc
'i 2  ma 3ma  2 (A.1)
12 f sw L
By determining the desired maximum current ripple, the minimum inductance value can be
achieved. According to, the maximum current ripple depends on the modulation index square
and also the dc link voltage level. In PWM converters, the intention is to work at high
modulation index to utilize the most of the dc link voltage.
To have 20% of the nominal current as current ripple in the converter with the specification
that is mentioned, the required inductance value must be 133 ȝH. For designing the inductor,
iron power Kool-Mu EE core- K5528E060- is chosen with solid winding. The number of
winding is 33 turns which gives 136 ȝH at full load and 235 uH at no-load. The designed
inductor is shown in (c). The ac resistance has been measured at switching frequency and its
multiple (where the current harmonics happen) and are listed in TABLE A-3. The
measurement has been done using precision impedance analyzer Agilent 4294A. For the
accuracy in measurement, the ac resistance of the winding is measured with the air core.
From TABLE A-3 although the ac resistance at high frequency is way bigger than the
fundamental frequency, the loss is almost negligible compared to fundamental.
The expected core loss in this core at full load condition is calculated to be 1.35 W for each
phase inductor. The core loss has been calculated for each switching cycle and for each B-H
curve in one switching cycle as suggested in Chapter 3.

A. 4.3. Loss in the switches

For calculating the switching capacitive loss and conduction loss of the switches, the
presented method in Section 3.6 is used. Since the MOSFETs are switching with grid
frequency the switching capacitive loss is negligible and therefore is not reported in this
Section. The switching parameters are listed in TABLE A-4. According to the parameters and
the full load condition, the switching capacitive and conduction losses are calculated for each
leg as listed in TABLE A-5. Even though the total gate charge of Si MOSFET is about 30
times larger than the one of GaN FET, the drive loss for both of them is negligible.
A. 4.2. Total loss
To calculate the total loss in the converter, the presented method in Section 3.6 is used. The
total loss is summation of switch losses and inductor loss. The total loss at full load condition

66
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

TABLE A-4: The switching parameters of Si MOSFET and GaN FET.

Parameters GaN Si
Ron@50oC (mŸ) 40 17.5
QOSS (nC) 106 4100
QG (nC) 12 363

TABLE A-5: Loss in the switches.

Parameter Loss (W)

PswQ1=PswQ2 1.85
Pcond. Q1&Q2 9
Pdrive. Q1&Q2 0.0084
Pcond.S1-S4 4
Pdrive. S1-S4 0.0003
Ptotal 16.7 Fig. A.3: Loss distribution in the converter at full load.

is 0.7% and the distribution of losses in the system is shown in Fig. A.3. As it can be seen, the
major loss in high power is the conduction loss and switching loss.

A. 5. Conclusion

This chapter has investigated a 10 kW GaN based hybrid three-level active NPC (HANPC).
x Using the presented method in Chapter 3, the filter parameters, especially the
converter-side inductor can easily be calculated.
Leg A LegB LegC

Si MOSFET, 650 V

GaN 650 V, 60 A
Measurement circuits

Fig. A.4: Built prototype of a 10 kW GaN based three-level HANPC.

67
APPENDIX A- THREE-LEVEL THREE-PHASE POWER FACTOR CORRECTION RECTIFIER

x The inductor for this converter is designed and the core loss and copper loss is
calculated.

x 6 active switches are utilized in this converter. Due to the superior advantages of GaN
switches the switching frequency of GaN FETs are set to 100 kHz.

x Even with this switching frequency, the switching capacitive loss only occupies 16%
of the overall loss in the converter.

x Expected efficiency of the converter at full load is 99.3%. GaN FETs are switched
with 100 kHz and Si MOSFETs with 50 Hz switching.

x The majority of the power loss is dedicated to the conduction loss in both GaN and Si
switches.

68
APPENDIX B-PUBLICATION

B. Appendix B
Appendix B includes the selected published papers as a part of the PhD work listed as
follows:
[B1] A. Kouchaki, M. Nymand, "Analytical Design of Passive LCL Filter for Three-phase
Two-level Power Factor Correction Rectifiers," in IEEE Transactions on Power Electronics,
submitted, under review.
[B2] A. Kouchaki, N. F. Javidi, F. Haase and M. Nymand, "An analytical inductor design
procedure for three-phase PWM converters in power factor correction applications," 2015
IEEE 11th International Conference on Power Electronics and Drive Systems, Sydney, NSW,
2015, pp. 1013-1018.
[B3] A. Kouchaki and M. Nymand, "Inductor design comparison of three-wire and four-wire
three-phase voltage source converters in power factor correction applications," Power
Electronics and Applications (EPE'15 ECCE-Europe), 2015 17th European Conference on,
Geneva, 2015, pp. 1-10.
[B4] A. Kouchaki and M. Nymand, "LCL filter design for three-phase two-level power factor
correction using line impedance stabilization network," 2016 IEEE Applied Power
Electronics Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 2382-2388.
[B5] A. Kouchaki, M. Nymand, R. Lazar, "Non-iterative, Analytic-based Passive LCL Filter
Design Approach for Three-phase Two-level Power Factor Correction Converters", Power
Electronics and Applications (EPE'16 ECCE-Europe), 2016 18th European Conference on,
Karlsruhe, 2016, pp. 1-10.
[B6] A. Kouchaki, R. Lazar, J.L. Pedersen, M. Nymand, "High Frequency Three-Phase
PWM Grid Connected Drive Using Silicon-Carbide Switches," IEEE Southern Power
Electronics Conference (SPEC’16), 5-8 December 2016
[B7] A. Kouchaki, R. Lazar, J.L. Pedersen, M. Nymand, "5 kW Bidirectional Grid-
Connected Drive using Silicon-Carbide Switches: Control," 2017 IEEE Applied Power
Electronics Conference and Exposition (APEC), Tampa, Florida, 2017.
[B8] F. Javidi, A. Kouchaki and M. Nymand, "A simple core loss modeling for three-phase
PWM voltage source converters," Industrial Electronics Society, IECON 2015 - 41st Annual
Conference of the IEEE, Yokohama, 2015, pp. 003063-003068.

69