VLSI Design
(BEC-701)
Unit-05
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Unit-5 Topics Unit-3 Syllabus
• Introduction to Testing: Faults in digital circuits
• Modeling of faults, Functional Modeling at the Logic
Level
• Functional Modeling at the Register, Structural Model
and Level of Modeling.
• Design for Testability
• Ad Hoc Design for Testability Techniques,
• Controllability and Observability,
• Introduction to Built-in-self-test (BIST) Concept.
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Introduction to Testing
• The increased complexity of integrated circuits (ICs) may cause the degradation
of performance due to defects and faults.
• In order to have smooth functionality and defect-free circuit and devices, the
testing and observability of ICs need to be grown for deep submicron
technology.
• Technology enhancement and higher complexity of IC become the bottleneck
for the circuit to work correctly and difficult to test due to the faster clock
speed.
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Introduction to Testing
• The demand of delay testing and timing analysis are tremendously increased
due to the higher operating frequency and miniaturization of technology.
• There are three ways by which circuits and devices can be tested:
– Verification testing: To test the correctness of circuits and devices.
– Manufacturing testing: To test for any logic faults, parametric faults, and physical faults which
can occur during the manufacturing of an IC.
– Acceptance testing: The quality of products supplied by the VLSI industry need to be verified
and accepted by the user only after completing the acceptance test.
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Fault Modelling
• A Fault Model is an engineering representation of something that could go wrong in
the production, development, or operation of a circuit or device.
• Using such models, the designer or user can then efficiently and effortlessly predict
the consequences of any particular fault.
• Instead of listing the types of faults, the essence of fault modelling is to describe the
impact of faults on the normal operation of VLSI circuits.
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Fault Modelling
• The number and nature of faults in VLSI circuits is strongly dependent on the level
of abstraction (or modelling).
• At the system level, the number of faults are relatively less and fault modelling
becomes easier.
• As we move towards the physical level, number of faults increase significantly and
fault modelling becomes very tedious.
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Fault Modelling
• At the highest (system) and lowest (physical) level of abstraction, fault modelling
also reaches an extreme.
• At the functional level, defect (which causes the fault) identification is challenging.
• An optimized fault modelling approach is designed either at the at the Logic level
(Structural/Gate level) or the Device level (Switch/Transistor level).
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Fault Modelling at the Logic level
• The most common fault models at this level are (i) Stuck-at fault model and (ii)
Bridging fault model.
• Stuck-At Fault Model: The most common model used for logical faults is the
single stuck-at fault. Here we assume that some of the circuit lines are permanently
fixed at logic-0 or logic-1 due to some failures.
• Bridging Fault Model: A bridging fault is said to have occurred when two or more
signal lines in a circuit are accidentally connected together. It is quite possible due to
imperfection during layout fabrication.
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Switch Level Fault Modelling
• The circuit is defined at the transistor level.
• MOS transistors are considered as switches such that:
– An nMOS transistor is ON when gate is HIGH.
– A pMOS transistor is ON when gate is LOW.
• Types of switch level fault models:
– Stuck-open fault: A transistor never turns ON.
– Stuck-short fault: A transistor is always ON.
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Stuck-Open Fault Modelling
• A transistor becomes non-conducting due to some fault.
• The gate output may depend on its previous state.
– A combinational circuit may exhibit sequential behavior.
• The 2-pattern test which includes two test vectors that are applied in sequence is a
common stuck-open fault model.
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Stuck-Short Fault Modelling
• A transistor is permanently conducting in the presence of fault.
• Both pull-up and pull-down networks may become conducting resulting in large
current flowing from VDD to ground.
• To detect this fault, we monitor the current flowing.
– Known as the IDDQ testing.
– Test vector causes a conducting path from VDD to ground in the presence of fault.
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Design for Testability
• The task of determining whether fabricated chips are fully functional is highly
complex and can be very time-consuming.
• When faulty chips pass an improperly designed test, they can cause system failures
and enormous difficulty in system debugging.
• Thus, it is of great importance to detect faults as early as possible.
• Generating tests for large circuits is very time consuming and ensuring correct
functionality becomes increasingly more difficult.
• If designs can be modified to make test generation easier: “Design for Testability”.
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Design for Testability
• Design for testability (DFT) is a design technique that makes testing a chip possible
and cost-effective by adding additional circuitry to the chip.
• DFT techniques improve the controllability and observability of internal nodes, so
that embedded functions can be tested.
• Most DFT techniques are targeted towards sequential circuits where test generation
is generally a tedious task.
• DFT techniques can be divided into: Ad-hoc techniques, Built-in Self Test, Scan cell
based approach.
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Controllability & Observability
• The controllability of an internal circuit node within a chip is a measure of the
ease of setting the node to a 1 or 0 state.
• Controllability measures the degree of difficulty of testing a particular signal
within a circuit.
• A node with little controllability, such as the most significant bit of a counter, might
require multiple cycles to get it to the right state.
• An easily controllable node would be directly settable via an input pad. For e.g.
making all flip-flops resettable via a global reset signal achieves good
controllability.
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Controllability & Observability
• The observability of a particular circuit node is the degree to which you
can observe the node at the outputs of an integrated circuit (i.e., the
pins).
• Observability measures the degree of difficulty of measuring the output
of a gate within a larger circuit to check that it operates correctly.
• The output of an easily observable node will be accessible either directly or
with moderate indirection (i.e., you may have to wait a few cycles).
• The effectiveness of DFT techniques is measured in terms of their impact on
controllability and observability of internal nodes.
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Ad-hoc DFT Techniques
• Ad hoc test techniques, as their name suggests, are collections of ideas aimed at
reducing the testing combinations.
• The common techniques for ad hoc testing include:
– Partitioning large sequential circuits
– Adding test points
– Adding multiplexers
– Providing for easy state reset
• In general, ad hoc testing techniques have been developed based on experience of
designers. While these techniques are still quite valid, increasing chip complexities
require a structural approach to testing.
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Ad-hoc DFT Techniques
• Partition and MUX Technique: Complex circuits can be partitioned and
multiplexers can be inserted such that some of the primary inputs can be fed to
partitioned parts through multiplexers with accessible control signals. This increases
the number of accessible nodes and reduces the number of test patterns. E.g.
Dividing a 32-bit counter into two 16-bit constituents would reduce the testing
time in principle by a factor of 215.
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Ad-hoc DFT Techniques
• Disable Internal Oscillators and Clocks: To avoid synchronization issues during
testing, internal oscillators and clocks should be disabled. For example, rather than
connecting the circuit directly to the on-chip oscillator, the clock signal can be ORed
with a disabling signal followed by an insertion of a testing signal.
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Ad-hoc DFT Techniques
• Avoid Asynchronous and Redundant Logic: The speed of an asynchronous logic
circuit can be faster than that of the synchronous logic circuit but design and testing
is relatively difficult. Additionally, prediction of state transition times is a challenge.
• The operation of an asynchronous logic circuit is sensitive to input test patterns,
which can often cause RACE condition and result in temporary errors in output
values.
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Ad-hoc DFT Techniques
• Avoid Asynchronous and Redundant Logic: To avoid static hazards, deliberate
redundancy is introduced. However, redundant nodes are difficult to observe since
the dependency of output on redundant node can’t be established. If a fault is
undetectable, the associated line or gate can be removed without changing the logic
function.
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Ad-hoc DFT Techniques
• Avoid Delay Dependent Logic: Chains of inverters can be used to design delay
times and use AND operation of their outputs along with inputs to generate pulses.
Most ATPG programs do not include logic delays to minimize the complexity of the
program. As a result, such delay-dependent logic is viewed as redundant
combinational logic, and the output of the re-convergent gate is always set to logic-
0, which is not correct. Thus, the use of delay-dependent logic should be avoided.
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Scan-based DFT Techniques
• It is already known that the controllability and observability can be enhanced by
providing more accessible logic nodes via additional I/O lines and multiplexers.
• However, the use of additional I/O pins can be costly not only for chip fabrication
but also for packaging.
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Scan-based DFT Techniques
• A popular alternative is to use scan registers with both shift and parallel load
capabilities. The scan design technique is a structured approach to design sequential
circuits for testability.
• The storage cells in registers are used as observation points, control points, or both.
• By using the scan design techniques, the testing of a sequential circuit is reduced to
the problem of testing a combinational circuit, since a sequential circuit consists of a
combinational circuit and some storage elements
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Scan-based DFT Techniques
• In the scan-based design, the storage elements are connected to form a long serial
shift register, the so-called scan path, by using multiplexers and a control (test/
normal) signal.
• Test mode:---- scan-in signal is clocked into the scan path, and the output of the
last stage latch is scanned out.
• Normal mode:---- scan-in path is disabled and the circuit functions as a sequential
circuit.
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Scan-based DFT Techniques
• The general structure of scan-based approach is as follows:
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Scan-based DFT Techniques
• The testing sequence is as follows:
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Scan-based DFT Techniques
• Example: Scan-based design of an edge-triggered D-type flip-flop.
• Practically, two clocks can be used: one for normal operation and one for shift
operation.
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Level Sensitive Scan Design
• The LSSD incorporates both the level sensitivity and the scan path approach using
shift registers. The level sensitivity is to ensure that the sequential circuit response is
independent of the transient characteristics of the circuit, such as the component and
wire delays.
• Thus, LSSD removes hazards and races. Its ATPG is also simplified since tests have
to be generated only for the combinational part of the circuit.
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Built-in Self Test (BIST) Techniques
• Built-in self-test, or BIST, is a DFT methodology involving the insertion of
additional hardware and software features into integrated circuits to allow them
to perform self-testing.
• BIST avoids the use of costly ATE (Automated Test Equipment).
• Only two external pins (CONTROL and OUTPUT) are sufficient.
• BIST requires lower system effort and provides better fault diagnosis.
• System maintenance and repair costs are reduced.
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Built-in Self Test (BIST) Techniques
• The BIST concept is also applicable to circuits that have no direct connections to
external pins, such as embedded memories.
• The essential circuit modules required for BIST include:
– Pseudo random pattern generator (PRPG)
– Output response analyzer (ORA)
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Built-in Self Test (BIST) Techniques
• The two most common categories of BIST are the Logic BIST (LBIST) and the
Memory BIST (MBIST).
• LBIST, which is designed for testing random logic, typically employs a
pseudorandom pattern generator to generate input patterns that are applied to the
device's internal scan chain, and a multiple input signature register (MISR) for
obtaining the response of the device to these input test patterns.
• MBIST is used specifically for testing memories. It has a circuit that apply, read,
and compare test patterns.
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Built-in Self Test (BIST) Techniques
• The basic architecture of BIST is as follows:
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Built-in Self Test (BIST) Techniques
• PRPG using LFSR: Pseudo Random Number Generators (PRNG) are widely used
in VLSI Design as Test Pattern Generators for testing of digital circuits in a BIST
system. These can be designed using the LFSR.
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Built-in Self Test (BIST) Techniques
• ORA using LFSR: The signature generator consists of a single-input LFSR in
which all the latches are edge-triggered. The signature is the content of this register
after the last input bit has been sampled. The input sequence (G) can be represented
as: 𝐺 = 𝑄. 𝑃 + 𝑅, where Q represents the output sequence, P is the characteristic
polynomial of LFSR and R is the remainder which is the signature to be compared.
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Built-in Self Test (BIST) Techniques
Advantages of BIST Disadvantages of BIST
Reduced costs of testing Additional Silicon area and pins required
Independent of technology Power overhead increases
Enhanced fault coverage On-chip testing hardware can fail
Reduced Testing Times
Concurrent testing is possible
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References
1. Sung-Mo Kang & Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis
& Design”,Mcgraw Hill, 4th Edition.
2. Neil H.E.Weste, David Money Harris, “CMOS VLSI Design – A circuits and
Systems Perspective” Pearson, 4th Edition.
3. D. A. Pucknell and K. Eshraghian, “Basic VLSI Design: Systems and Circuits”,
PHI, 3rd Ed.,1994.
4. R. J. Baker, H. W. Li, and D. E. Boyce , " CMOS circuit design, layout, and
simulation", Wiley IEEE Press,2007.
5. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and
Testable Design" , Jaico Publishing House.
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