RTL & HDL Interview Questions with
Simple Answers
1. What is the difference between blocking and non-blocking assignments?
o Blocking (=) executes in order. Non-blocking (<=) executes in parallel.
2. What are synthesisable and non-synthesisable constructs?
o Synthesisable = can become hardware. Non-synthesisable = for simulation
only.
3. What is the difference between posedge clk and posedge clk or posedge reset?
o First triggers only on clock, second triggers on clock or reset.
4. What is the difference between wire and reg?
o wire is for connection, reg stores value.
5. What is FSM? Types of FSMs?
o FSM: Finite State Machine. Types: Moore (output from state), Mealy (output
from state + input).
6. What are the different types of delays in Verilog?
o #delay (simulation), inertial (glitch filtering), transport (passes all).
7. How do you infer a latch in Verilog?
o Happens when if/else is incomplete in always @(*) block.
8. What is the difference between case, casex, and casez?
o case = exact match, casez = z/? is don't care, casex = x/z is don't care.
9. What is a race condition?
o When two things try to change the same signal at the same time.
10. How do you write a parameterized module in Verilog?
o Use parameter keyword to make module flexible.
11. What are synthesizable loops in RTL?
o Loops with fixed bounds that tools can unroll.
12. How do you avoid combinational loops in RTL design?
o Give full conditions, avoid feedback without flip-flop.
13. How do you implement a priority encoder in Verilog?
o Use a case block checking inputs in order.
14. What is the difference between always_comb, always_ff, and always_latch?
o For combo logic, sequential, and latches respectively.
15. What is a setup and hold violation?
o Data comes too early/late around clock edge.
16. What is the difference between combinational and sequential logic?
o Combo = output depends only on input, Sequential = input + past state.
17. What is metastability?
o Flip-flop gets input during setup/hold violation, output uncertain.
18. What is clock gating?
o Turn off clock to unused blocks to save power.
19. What is the difference between initial and always blocks?
o initial runs once, always runs repeatedly.
20. What is a sensitivity list and why use (*)?
o Tells which signals trigger always block. (*) adds all automatically.
21. How is a counter implemented in Verilog?
o A register that increases on every clock.
22. What is the difference between assign and always blocks?
o assign = continuous assign to wire, always = procedural logic.
23. What is pipelining in RTL design?
o Break long logic into stages using registers.
24. How do you avoid race conditions in testbenches?
o Use proper = and <=, sync with clock.
25. What is the purpose of the generate block in Verilog?
o Repeat code using for loop in hardware.
26. What is one-hot encoding and when is it used?
o Only one bit is high for any state.
27. What are implicit and explicit FSM coding styles?
o Implicit = one block, Explicit = split blocks.
28. What is the difference between Moore and Mealy FSMs?
o Moore = output changes on clock, Mealy = changes anytime.
29. What is the default signal value in simulation?
o x (unknown). Initialize them.
30. What is the difference between assign and force in simulation?
o assign is RTL, force is testbench override.
31. How do you detect a glitch in a signal?
o Use waveform or assertions.
32. What are design constraints in synthesis?
o Timing, area, power limits using SDC.
33. What is register packing and duplication?
o Save area or improve speed by combining or copying.
34. What is the difference between functional and code coverage?
o Code = lines executed, Functional = scenarios tested.
35. What is inferred and instantiated hardware?
o Inferred = let tool decide. Instantiated = write exact block.
36. What is a glitch and how to avoid it?
o Short unwanted pulse. Fix with clean design.
37. What is the difference between RTL simulation and synthesis?
o Sim = behavior. Synthesis = convert to gates.
38. What is a test vector?
o Set of inputs to test circuit.
39. What is the difference between disable and deassign?
o disable = stop block, deassign = remove assignment.
40. What is the difference between synthesis warning and error?
o Warning = compiles, Error = stops.
41. What are asynchronous and synchronous resets?
o Async = works anytime, Sync = works on clock edge.
41. What are asynchronous and synchronous resets?
Async = works anytime, Sync = works on clock edge.
42. What is the difference between edge-sensitive and level-sensitive devices?
Edge = triggered on clock edge, Level = depends on enable signal level.
43. What is meant by fan-out?
Number of gates a signal drives. High fan-out = more delay.
44. What is a latch? How is it different from a flip-flop?
Latch = level-sensitive, Flip-flop = edge-sensitive.
45. What is false path and multicycle path?
False = never occurs, Multicycle = needs more than 1 clock.
46. What are the three blocks in FSM design?
State Register, Next-State Logic, Output Logic.
47. What is zero-delay modeling?
Simulation where all logic has zero delay.
48. What is event-driven simulation?
Simulator triggers evaluation only when signals change.
49. Difference between posedge clk and @clk?
posedge clk = edge-triggered, @clk = any change (unsafe).
50. What are don’t care conditions in synthesis?
Inputs where output doesn't matter. Used for optimization.
51. What is the issue with latch inference in RTL?
Can create unwanted memory and glitches.
52. What is a deadlock in FSM?
FSM gets stuck in one state.
53. What is meant by over-constraining and under-constraining?
Over = too strict, Under = too loose constraints.
54. What is combinational feedback? Why is it bad?
Feedback without clock causes instability.
55. What is reset deassertion glitch?
Reset released without sync, causes metastability.
56. Why is always_comb preferred over always @(*)?
Better checks, catches missing assignments.
57. What is the purpose of unique case in SystemVerilog?
Tells tool only one case is true, helps optimization.
58. What is metastability? How do you handle it?
Unstable output due to timing issue. Fix with flip-flop synchronizers.
59. What is meant by pulse synchronization?
Method to pass short pulses between clock domains safely.
60. What are stuck-at faults?
Signal stuck at 0 or 1 permanently. Used in test models.
61. How are testbenches structured in RTL simulation?
Stimulus, DUT, Monitor, Scoreboard.
62. How do you design a CDC-safe data transfer?
Use 2 flip-flops for control, FIFO for data.
63. How to prevent race conditions in non-blocking assignments?
Use <= inside clocked blocks, don't mix with =.
64. What is a retiming technique in synthesis?
Move flip-flops to balance delays.
65. What is the significance of setup and hold margins in CDC paths?
Prevents data capture errors across clocks.
66. What is the purpose of multicycle path constraints?
Allows data more than 1 cycle to settle.
67. How can false paths affect timing closure?
Waste optimization effort. Must be declared.
68. What is clock-domain pessimism in STA?
Extra margin added due to uncertain clocks.
69. How does clock gating impact simulation and synthesis?
Saves power in synthesis. Needs override in sim.
70. How do you check clock skew at RTL?
Not in RTL. Done in STA post-layout.
71. What is glitch-free muxing in clock-domain switching?
Use handshake FSM or special cells to avoid glitches.
72. What are scan FFs and how do they impact design?
Flip-flops for testing. Adds area but improves coverage.
73. How is an FSM deadlock diagnosed during RTL simulation?
Use waveform or assertions to catch stuck state.
74. What is RTL code coverage?
Measures which lines, bits, and states are tested.
75. How do you optimize for area in RTL design?
Remove unused logic, share operations, use binary FSM.
76. How do you use generate blocks in Verilog/SystemVerilog?
Create repeated logic using generate and for.
77. What is RTL clock gating and how is it implemented?
Turn off clock using enable signal or special cells.
78. What is RTL power estimation?
Estimate power based on switching activity.
79. What is glitch power and how do you reduce it?
Power from unnecessary transitions. Balance delays to fix.
80. Explain toggle rate and its relevance in power estimation.
More toggles = more power. Used in power analysis.
81. What is a coverage hole? How to detect and fix it?
Untested logic. Fix with better testbench.
82. What is a sticky bit in control logic?
Bit stays set until cleared manually.
83. Explain design partitioning and its importance.
Divide big design into blocks. Helps reuse and debugging.
84. Why are assertions better than testbench if checks?
Automatic, reusable, easier to debug.
85. What’s the difference between immediate, concurrent, and cover assertions?
Immediate = now, Concurrent = over time, Cover = check condition happens.
86. How is functional reset coverage measured?
Check if all logic resets properly.
87. What are CDC reconvergence paths and why are they critical?
Two unsynced signals meet. Can cause errors.
88. Why should we avoid inferred latches in synthesis?
Can glitch. Harder to time and test.
89. How to handle asynchronous FIFO full and empty logic?
Use gray-code pointers with proper sync.
90. Why use ready/valid protocol in SoC buses?
Ensures safe data transfer. Prevents loss.
91. How to minimize logic duplication in RTL?
Use functions, shared modules, remove redundancy.
92. What causes FSM livelock and how to fix it?
Looping forever. Fix transition logic or add timeout.
93. How to write a reconfigurable FSM in Verilog?
Use parameters or config table.
94. What is FSM state encoding corruption and how is it debugged?
Bad reset or no default. Debug with assertions.
95. What is datapath control decoupling and why is it useful?
Split FSM and datapath. Makes reuse/debug easier.
96. What are power-aware verification techniques at RTL?
Use UPF/CPF and simulate power control logic.
97. How to detect and fix redundant logic in RTL?
Use lint tools and remove dead code.
98. How to design glitch-free combinational logic?
Balance delays, avoid multiple drivers.
99. What’s the role of input/output buffering in RTL design?
Helps manage drive strength and signal timing.
100. What is an uninitialized register and why is it risky?
Default X value causes unknowns in sim. Must reset.
