TPA3122D2

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15-W STEREO CLASS-D AUDIO POWER AMPLIFIER

1FEATURES APPLICATIONS
• 10-W/ch into an 4-Ω Load From a 17-V Supply • Televisions
• 15-W/ch into an 8-Ω Load From a 28-V Supply
• Operates from 10 V to 30 V
DESCRIPTION
• Efficient Class-D Operation The TPA3122D2 is a 15-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
• Four Selectable, Fixed Gain Settings single ended speakers or mono bridge tied load. The
• Internal Oscillator (No External Components TPA3122D2 can drive stereo speakers as low as 4Ω.
Required) The efficiency of the TPA3122D2 eliminates the need
• Single Ended Analog Inputs for an external heat sink when playing music.
• Thermal and Short-Circuit Protection with The gain of the amplifier is controlled by two gain
Auto Recovery Feature select pins. The gain selections are 20, 26, 32, and
36 dB.
• 20-pin DIP Package
SIMPLIFIED APPLICATION CIRCUIT
TPA3122D2
1 mF
0.22 mF
Left Channel LIN BSR 22 mH 470 mF
Right Channel RIN ROUT
1 mF 0.68 mF
PGNDR

PGNDL 0.68 mF
1 mF
BYPASS LOUT
22 mH 470 mF
AGND BSL
0.22 mF

PVCCL 10 V to 30 V
10 V to 30 V AVCC
PVCCR

VCLAMP
Shutdown
Control SD 1 mF

Mute Control MUTE

GAIN0

GAIN1
} 4-Step Gain
Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas Copyright © 2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

N (DIP) PACKAGE
(TOP VIEW)

PVCCL 1 20 PGNDL
SD 2 19 LOUT
MUTE 3 18 BSL
LIN 4 17 AVCC
RIN 5 16 AVCC
BYPASS 6 15 GAIN0
AGND 7 14 GAIN1
AGND 8 13 BSR
VCLAMP 9 12 ROUT
PVCCR 10 11 PGNDR

TERMINAL FUNCTIONS
TERMINAL
20-PIN I/O DESCRIPTION
NAME
(DIP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC.
RIN 5 I Audio input for right channel.
LIN 4 I Audio input for left channel.
GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
MUTE 3 I
outputs enabled). TTL logic levels with compliance to AVCC.
BSL 18 I/O Bootstrap I/O for left channel.
PVCCL 1 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
LOUT 19 O Class-D -H-bridge positive output for left channel.
PGNDL 20 Power ground for left channel H-bridge.
VCLAMP 9 Internally generated voltage supply for bootstrap capacitors.
BSR 13 I/O Bootstrap I/O for right channel.
ROUT 12 O Class-D -H-bridge negative output for right channel.
PGNDR 11 Power ground for right channel H-bridge.
PVCCR 10 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
AGND 8 Analog ground for digital/analog cells in core.
AGND 7 Analog Ground for analog cells in core.
Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 6 O
external capacitor sizing.
AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
VCC Supply voltage, AVCC, PVCC –0.3 to 36 V
VI Logic input voltage SD, MUTE, GAIN0, GAIN1 –0.3 to VCC +0.3 –0.3 to VCC +0.3 V
VIN Analog input voltage RIN, LIN –0.3 to 7 V
Continuous total power dissipation See Dissipation Rating Table
TA Operating free-air temperature range –40 to 85 °C
TJ Operating junction temperature range –40 to 150 °C
Tstg Storage temperature range -65 to 150 °C
RL Load resistance (Minimum value) 3.2 kV
Human body model (all pins) ±2 kV
ESD Electrostatic Discharge
Charged-device model (all pins) ±500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS
PACKAGE (1) TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
20-pin DIP 1.87 W 15 mW/°C 1.20 W 0.97 W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at [Link].

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 10 30 V
VIH High-level input voltage SD, MUTE, GAIN0, GAIN1 2 V
VIL Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V
SD, VI = VCC, VCC = 30 V 125
IIH High-level input current MUTE, VI = VCC, VCC = 30 V 125 µA
GAIN0, GAIN1, VI = VCC, VCC = 24 V 125
SD, VI = 0, VCC = 30 V 1
IIL Low-level input current MUTE, VI = 0 V, VCC = 30 V 1 µA
GAIN0, GAIN1, VI = 0 V, VCC = 24 V 1
TA Operating free-air temperature –40 85 °C

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DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage
| VOS | VI = 0 V, AV = 36 dB 7.5 50 mV
(measured differentially)
V(BYPASS) Bypass output voltage No load AVCC/8 V
ICC(q) Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mA
ICC(q) Quiescent supply current in mute mode MUTE = 2 V, No load 23 mA
ICC(q) Quiescent supply current in shutdown 1
SD = 0.8 V , No load 0.39 mA
mode
rDS(on) Drain-source on-state resistance 200 mΩ
Gain0 = 0.8 V 18 20 22
Gain1 = 0.8 V
Gain0 = 2 V 24 26 28
G Gain dB
Gain0 = 0.8 V 30 32 34
Gain1 = 2 V
Gain0 = 2 V 34 36 38
Mute Attenuation VI = 1Vrms –82

AC CHARACTERISTICS
TA = 25°C, VCC = 24V, RL = 4Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 12 V, Vripple = 200 mVPP 100 Hz –30 dB
KSVR Supply ripple rejection Gain = 20 dB
1 kHz -48 dB
VCC = 12 V, RL = 4 Ω, f = 1 kHz 4
Output Power at 1% THD+N
VCC = 24 V, RL = 8 Ω, f = 1 kHz 8
PO W
Output Power at 10% VCC = 12 V, RL = 4 Ω, f = 1 kHz 5
THD+N VCC = 24 V, RL = 8 Ω, f = 1 kHz 10
Total harmonic distortion + RL = 4 Ω, f = 1 kHz, PO = 1 W 0.1%
THD+N
noise RL = 8 Ω, f = 1 kHz, PO = 1 W 0.06%
85 µV
Vn Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dB
Crosstalk PO = 1 W, f = 1kHz; Gain = 20 dB –60 dB
SNR Signal-to-noise ratio Max Output at THD+N < 1%, f = 1 kHz, Gain = 20 dB 99 dB
Thermal trip point 150 °C
Thermal hysteresis 30 °C
fOSC Oscillator frequency 10 V ≤ VCC 230 250 270 kHz
mute delay time from mute input switches high until outputs muted 120 msec
Δt
unmute delay time from mute input switches low until outputs unmuted 120 msec

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FUNCTIONAL BLOCK DIAGRAM

BSL
AVCC AVDD PVCCL

REGULATOR
HS
+ LOUT
- VCLAMP

LS
AVDD AVDD PGNDL
LIN

SC
AVDD/2 DETECT

AGND

CONTROL
SD
BIAS
VCLAMP
THERMAL
MUTE
MUTE CONTROL

OSC/RAMP
BYPASS BYPASS

GAIN1 AV
CONTROL
GAIN0

SC
DETECT

BSR
PVCCR

HS
ROUT
-
VCLAMP
+
LS

PGNDR
AVDD
AVDD
RIN

AVDD/2

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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY (SE) FREQUENCY (SE)
10 10
Gain = 20 dB Gain = 20 dB
RL = 4 Ω (SE) RL = 4 Ω (SE)
VCC = 12 V VCC = 18 V
PO = 2 W PO = 5 W
1 1
THD+N − %

THD+N − %
0.1 0.1

PO = 1 W PO = 0.5 W PO = 1 W
PO = 2.5 W

0.01 0.01
20 100 1k 10k 20k 20 100 1k 10k 20k

f − Frequency − Hz f − Frequency − Hz G002

G001
Figure 1. Figure 2.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY (SE) FREQUENCY (SE)
10 10
Gain = 20 dB Gain = 20 dB
RL = 4 Ω (SE) RL = 8 Ω (SE)
VCC = 24 V VCC = 24 V PO = 5 W
PO = 5 W
1 1
THD+N − %

THD+N − %

PO = 2.5 W

0.1 0.1

PO = 2.5 W PO = 1 W PO = 1 W

0.01 0.01
20 100 1k 10k 20k 20 100 1k 10k 20k

f − Frequency − Hz G003
f − Frequency − Hz G004

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
OUTPUT POWER (SE) OUTPUT POWER (SE)
10 10
Gain = 20 dB Gain = 20 dB
RL = 4 Ω (SE) RL = 8 Ω (SE)

1 1
THD+N − %

THD+N − %

VCC = 12 V VCC = 12 V

VCC = 18 V
0.1 0.1

VCC = 24 V VCC = 24 V
VCC = 18 V
0.01 0.01
0.01 0.1 1 10 40 0.01 0.1 1 10 40

PO − Output Power − W G005

PO − Output Power − W G006

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

CROSSTALK CROSSTALK
vs vs
FREQUENCY (SE) FREQUENCY (SE)
0 0
Gain = 20 dB Gain = 20 dB
PO = 0.25 W PO = 0.125 W
−20 RL = 4 Ω (SE) −20 RL = 8 Ω (SE)
VCC = 18 V VCC = 18 V
Crosstalk − dB

Crosstalk − dB
−40 −40
Left to Right
Left to Right
−60 −60

−80 −80

Right to Left Right to Left

−100 −100
20 100 1k 10k 20k 20 100 1k 10k 20k

f − Frequency − Hz G007
f − Frequency − Hz G008
Figure 7. Figure 8.

GAIN/PHASE GAIN/PHASE
vs vs
FREQUENCY (SE) FREQUENCY (SE)
400 30 200
Gain
20 25 100
Gain
200 20
Gain − dBr A

Gain − dBr A

0 0
Phase − °

Phase − °
Phase Phase
15
−100
−20
0 10
Gain = 20 dB L filt = 22 mH Gain = 20 dB L filt = 47 mH
PO = 0.125 W Cfilt = 0.68 mF PO = 0.125 W Cfilt = 0.22 mF −200
5
−40 RL = 4 Ω (SE) Cdc = 470 mF RL = 8 Ω (SE) Cdc = 470 mF
VCC = 24 V VCC = 18 V
−200 0 −300
100 1k 10k 100k 20 100 1k 10k 200k

f − Frequency − Hz G009
f − Frequency − Hz G010
Figure 9. Figure 10.

OUTPUT POWER OUTPUT POWER

vs vs
SUPPLY VOLTAGE (SE) SUPPLY VOLTAGE (SE)
15 18
Gain = 20 dB Gain = 20 dB
16
R L = 4 W (SE) RL = 8 Ω (SE)
PO − Output Power − W

14
PO − Output Power − W

10 12
THD+N = 10%
10
THD+N = 10%
8
5 6 THD+N = 1%
THD+N = 1%
4
2
0 0
10 12 14 16 18 20 10 12 14 16 18 20 22 24 26 28 30
PVCC − Supply Voltage − V G011 PVCC − Supply Voltage − V G012
Figure 12.
NOTE: Dashed line = Thermally limited
Figure 11.

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TYPICAL CHARACTERISTICS (continued)

EFFICIENCY EFFICIENCY
vs vs
OUTPUT POWER (SE) OUTPUT POWER (SE)
100 100

80 80
Efficiency − %

Efficiency − %
60 60 VCC = 24 V
VCC = 12 V

40 40
VCC = 18 V
20 Gain = 20 dB 20
RL = 4 Ω (SE) Gain = 20 dB
VCC = 12 V RL = 8 Ω (SE)
0 0
0 1 2 3 4 5 6 7 0 2 4 6 8 10 12 14

PO − Output Power − W PO − Output Power − W

G013 G014
Figure 13. Figure 14.

SUPPLY CURRENT SUPPLY CURRENT

vs vs
TOTAL OUTPUT POWER (SE) TOTAL OUTPUT POWER (SE)
1.4 0.7
Gain = 20 dB Gain = 20 dB
1.2 RL = 4 Ω (SE) 0.6 RL = 8 Ω (SE)
VCC = 12 V
ICC − Supply Current − A

ICC − Supply Current − A

1.0 0.5

0.8 0.4
VCC = 24 V
0.6 0.3

0.4 0.2 VCC = 18 V

0.2 0.1
VCC = 12 V
0.0 0.0
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14

PO − Total Output Power − W G015

PO − Total Output Power − W G016
Figure 15. Figure 16.

POWER SUPPLY REJECTION RATIO TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY (SE) FREQUENCY (BTL)
0 10
Gain = 20 dB
−20 RL = 8 Ω (BTL)
VCC = 24 V
1 PO = 20 W
−40
THD+N − %
PSRR − dB

PO = 1 W
−60 0.1

−80
Gain = 20 dB 0.01 PO = 5 W
RL = 4 Ω (SE)
−100
VCC = 12 V
Vripple = 200 mVp-p
−120 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k

f − Frequency − Hz G017
f − Frequency − Hz G018

Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION + NOISE GAIN/PHASE

vs vs
OUTPUT POWER (BTL) FREQUENCY (BTL)
10 30
Gain = 20 dB Phase
RL = 8 Ω (BTL) 20
−200

1 VCC = 12 V Gain
−300
10

Gain − dBr A
THD+N − %

Phase − °
−400
0.1 0

−500
−10
0.01 Gain = 20 dB L filt = 33 mH
VCC = 18 V PO = 0.125 W Cfilt = 1 mF −600
VCC = 24 V −20
RL = 8 Ω (BTL)
VCC = 24 V
0.001 −30 −700
0.01 0.1 1 10 50 20 100 1k 10k 200k

PO − Output Power − W f − Frequency − Hz G020

G019

Figure 19. Figure 20.

OUTPUT POWER EFFICIENCY

vs vs
SUPPLY VOLTAGE (BTL) OUTPUT POWER (BTL)
70 100
Gain = 20 dB
60 RL = 8 Ω (BTL)
80
PO − Output Power − W

50
Efficiency − %

60 VCC = 24 V
40 THD+N = 10% VCC = 12 V

30 VCC = 18 V
40
THD+N = 1%
20
20
10 Gain = 20 dB
RL = 8 Ω (BTL)
0 0
10 12 14 16 18 20 22 24 26 28 30 0 4 8 12 16 20 24 28

PVCC − Supply Voltage − V G021

PO − Output Power − W G022
Figure 21. Figure 22.

SUPPLY CURRENT POWER SUPPLY REJECTION RATIO

vs vs
TOTAL OUTPUT POWER (BTL) FREQUENCY (BTL)
2.0 0
Gain = 20 dB Gain = 20 dB
1.8
RL = 8 Ω (BTL) −20 RL = 8 Ω (BTL)
1.6 VCC = 18 V
ICC − Supply Current − A

VCC = 24 V
1.4 Vripple = 200 mVp-p
−40
PSRR − dB

1.2 VCC = 12 V
1.0 −60
0.8
−80
0.6
VCC = 24 V
0.4
−100
0.2
0.0 −120
0 4 8 12 16 20 24 28 20 100 1k 10k 20k

PO − Total Output Power − W f − Frequency − Hz G024

G023
Figure 23. Figure 24.

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APPLICATION INFORMATION

CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3122D2.

Traditional Class-D Modulation Scheme

The TPA3122D2 operates in AD mode. There are two main configurations that may be used. For stereo
operation, the TPA3122D2 should be configured in a single-ended (SE) half bridge amplifier. For mono
applications, TPA3122D2 may be used as a bridge tied load (BTL) amplifier. The traditional class-D modulation
scheme, which is used in the TPA3122D2 BTL configuration, has a differential output where each output is 180
degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential pre-filtered
output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 25.

+12 V
OUTP
0V

-12 V
OUTN
0V

+12 V
Differential Voltage
0V
Across Load
-12 V

Current

Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input

Supply Pumping
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping
is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D
amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at
the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due
to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,
which temporarily shuts down the audio output.
Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out
of phase 180° and reverse the speaker connections. Because most audio is highly correlated, this causes the
supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on
the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby,
sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at low
frequencies and high output levels.

Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3122D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.

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For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3122D2. At the higher gain
settings, the input impedance could increase as high as 72 kΩ

Table 1. Gain Setting

AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ)
GAIN1 GAIN0
TYPICAL TYPICAL
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 kΩ ±20%, to
the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.

Zf

Ci
Zi
Input IN
Signal

The -3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1.
1
f =
2p Zi Ci (1)

INPUT CAPACITOR, CI
In the typical application, an input capacitor I) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 2.

–3 dB

1
fc =
2p Zi Ci

fc (2)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc (3)
In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network I) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially

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in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.

Single Ended Output Capacitor, Co

In single ended (SE) applications, the DC blocking capacitor forms a high pass filter with speaker impedance.
The frequency response rolls of with decreasing frequency at a rate of 20dB/decade. The cutoff frequency is
determined by
fc = 1/2×πCoZL
Table 2 shows some common component values and the associated cutoff frequencies:

Table 2. Common Filter Responses

CSE – DC Blocking Capacitor (µF)
Speaker Impedance (Ω)
fc = 60 Hz fc = 40 Hz fc = 20 Hz
4 680 1000 2200
8 330 470 1000

Output Filter and Frequency Response

For the best frequency response, a flat passband output filter (second order Butterworth) may be used. The
output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.
There are several possible configurations depending on the speaker impedance and whether the output
configuration is Single Ended (SE) or Bridge Tied Load (BTL). Table 3 list several possible arrangements.

Table 3. Recommended Filter Output Components

Output Configuration Speaker Impedance (Ω) Filter Inductor (µH) Filter Capacitor (nF)
4 22 680
Single Ended (SE)
8 47 390
4 10 1500
Bridge Tied Load
8 22 680

Lfilter LOUT / ROUT Lfilter

LOUT

Cfilter Cfilter

ROUT Lfilter

Cfilter

Figure 26. BTL Filter Configuration Figure 27. SE Filter Configuration

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Power Supply Decoupling, CS

The TPA3122D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF to 1 µF placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near
the audio power amplifier is recommended. The 220-µF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-µF
capacitor on the AVCC terminal is adequate.

BSN and BSP Capacitors

The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

VCLAMP Capacitor
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one
internal regulator clamps the gate voltage. One 1-µF capacitor must be connected from VCLAMP (pin 11 for
PWP and pin 9 for DIP package) to ground and must be rated for at least 16 V. The voltages at the VCLAMP
terminal may vary with VCC and may not be used for powering any other circuitry.

VBYP Capacitor Selection

The scaled supply reference (VBYP) nominally provides an AVcc/8 internal bias for the preamplifier stages. The
external capacitor for this reference CBYP) is a critical component and serves several important functions. During
start-up or recovery from shutdown mode, CBSP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling with the output drive signal. This
noise could result in degraded PSRR and THD + N.
The circuit is designed for a CBSP value of 1 µF for best pop performance. The inputs caps should be the same
value. A ceramic or tantalum low-ESR capacitor is recommended.

SHUTDOWN OPERATION
The TPA3122D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of non-use for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the
power supply voltage.

MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3122D2. A logic high on this terminal causes
the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be
used as a quick disable/enable of outputs when changing channels on a television or switching between different
audio sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.

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TPA3122D2 [Link]
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.

SHORT-CIRCUIT PROTECTION
The TPA3122D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts and output-to-GND shorts. When a short circuit is detected on the outputs, the part
immediately disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is
removed.

THERMAL PROTECTION
Thermal protection on the TPA3122D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3122D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—The high-frequency 0.1µF decoupling capacitors should be placed as close to the
PVCC (pins 1 and 10) and AVCC (pins 16 and 17) terminals as possible. The VBYP (pin 6) capacitor and
VCLAMP (pin 9) capacitor should also be placed as close to the device as possible. Large (220 µF or
greater) bulk power supply decoupling capacitors should be placed near the TPA3122D2 on the PVCCL and
PVCCR terminals.
• Grounding—The AVCC (pins 16 and 17) decoupling capacitor and VBYP (pin 6) capacitor should each be
grounded to analog ground (AGND, pins 7 and 8). The PVCCx decoupling capacitors and VCLAMP
capacitors should each be grounded to power ground (PGND, pins 11 and 20). Analog ground and power
ground should be connected at the thermal pad, which should be used as a central ground connection or star
ground for the TPA3122D2.
• Output filter—The EMI filter (L1, L2, C9, and C16) should be placed as close to the output terminals as
possible for the best EMI performance. The capacitors should be grounded to power ground.
For an example layout, see the TPA3122D2 Evaluation Module (TPA3122D2EVM) User Manual, (SLOU214).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
[Link]
VCC

22uH
Shutdown Control
0.1uF
Mute Control
470uF
1 PVCCL PGNDL 20
1.0uF 2 19 LEFT_OUT 4.7K 0.68uF
Left Input SD LOUT
3 MUTE BSL 18
4 17 0.22uF
LIN AVCC1
5 RIN AVCC2 16
Right Input 6 15
BYPASS GAIN0
7 AGND1 GAIN1 14
1.0uF 8 13 0.22uF
1.0uF AGND2 BSR RIGHT_OUT
9 VCLAMP ROUT 12
10 PVCCR PGNDR 11

TPA3122_PDIP
4.7K 0.68uF

0.1uF 22uH

470uF

1.0uF 470uF 470uF

0.1uF 10uF

Figure 28. SE 4-Ω Application Schematic

14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s) :TPA3122D2

 [Link]
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

VCC

22uH
Shutdown Control
0.1uF
Mute Control

1 PVCCL PGNDL 20
1.0uF 2 19 LEFT_OUT 4.7K 0.68uF
Plus Input SD LOUT
3 MUTE BSL 18
4 17 0.22uF
LIN AVCC1
5 RIN AVCC2 16
Minus Input 6 15
BYPASS GAIN0
7 AGND1 GAIN1 14
1.0uF 8 13 0.22uF
1.0uF AGND2 BSR RIGHT_OUT
9 VCLAMP ROUT 12
10 PVCCR PGNDR 11

TPA3122_PDIP
4.7K 0.68uF

0.1uF 22uH

1.0uF 470uF 470uF

0.1uF 10uF

Figure 29. BTL 8-Ω Application Schematic

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 30 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer-input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 30(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 30(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 15

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TPA3122D2 [Link]
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

Power Supply

Signal APA RL Analyzer

Generator 20 Hz - 20 kHz

(a) Basic Class-AB

Power Supply

Lfilt

Signal Class-D APA Cfilt Analyzer

Generator RL 20 Hz - 20 kHz

(b) Traditional Class-D

Figure 30. Audio Measurement Systems

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 [Link]
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

SE Input and SE Output (TPA3122D2 Stereo Configuration)

The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE
measurement circuit is shown in Figure 31. SE inputs normally have one input pin per channel. In some cases,
two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through
an output ac coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are
considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for
best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that
will effect the measurement accuracy. The analyzer should have balanced inputs to cancel out any
common-mode noise in the measurement.

Evaluation Module
Audio Power
Generator Analyzer
Amplifier
CIN

Lfilt
RGEN RIN CL
VGEN
RANA CANA
Cfilt RL

RANA CANA

Twisted-Pair Wire Twisted-Pair Wire

Figure 31. SE Input—SE Output Measurement Circuit

The following general rules should be followed when connecting to APAs with SE inputs and outputs:
• Use an unbalanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 4)

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TPA3122D2 [Link]
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3122D2 Mono Configuration)

Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 32. The differential input is a balanced input,
meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the SE output
equates to a balanced output.

Evaluation Module
Audio Power
Generator Analyzer
Amplifier
CIN Lfilt

RGEN RIN Cfilt RANA CANA

VGEN RL
CIN Lfilt

RGEN RIN Cfilt RANA CANA

Twisted-Pair Wire Twisted-Pair Wire

Figure 32. Differential Input, BTL Output Measurement Circuit

The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 4).
Table 4 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.

Table 4. Recommended Minimum Wire Size for Power Cables

DC POWER LOSS AC POWER LOSS
POUT (W) RL(Ω) AWG Size
(MW) (MW)
10 4 18 22 16 40 18 42
2 4 18 22 3.2 8 3.7 8.5
1 8 22 28 2 8 2.1 8.1
< 0.75 8 22 28 1.5 6.1 1.6 6.2

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 PACKAGE OPTION ADDENDUM

[Link] 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPA3122D2N Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TPA3122D2
TPA3122D2N.A Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TPA3122D2
TPA3122D2N.B Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TPA3122D2

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
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and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 23-May-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPA3122D2N N PDIP 20 20 506 13.97 11230 4.32
TPA3122D2N.A N PDIP 20 20 506 13.97 11230 4.32
TPA3122D2N.B N PDIP 20 20 506 13.97 11230 4.32

Pack Materials-Page 1
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