100 MUST-KNOW SYSTEMVERILOG ASSERTIONS
(SVA) COMMANDS FOR DV INTERVIEWS
SVA COMMAND / CONSTRUCT PURPOSE
1 assert property ( ... ); Basic assertion syntax
property p_name; ...
2 Declare a named property
endproperty
sequence s_name; ...
3 Declare a named sequence
endsequence
4 always @(posedge clk) Define sampling edge
5 disable iff (reset) Assertion disabling condition
6 ##[1:3] Repetition within a delay range
7 ##0 Zero-delay concatenation
Sequential implication with 1-
8 s_event1 ##1 s_event2
cycle delay
9 ` ->`
10 ##1 Fixed one-cycle delay
Matches only the first
11 first_match
occurrence
Hold a condition true over a
12 throughout
sequence
Ensure sequence occurs entirely
13 within
within another
SVA COMMAND / CONSTRUCT PURPOSE
Logical intersection of
14 intersect
sequences
15 `overlapped implication ( =>)`
16 `non-overlapped implication ( ->)`
17 not ... Negate a sequence or condition
Combine multiple sequences
18 or ...
(logical OR)
Combine multiple sequences
19 and ...
(logical AND)
Match any number of cycles
20 ##[*]
(including 0)
21 $rose(signal) Rising edge detector
22 $fell(signal) Falling edge detector
23 $stable(signal) No change on signal
24 $changed(signal) Signal changed
25 [*N] Repeat the sequence N times
26 [->N] At least N cycles
27 [->N:N] Exact N cycles
28 [+] One or more repetitions
29 [=N] Repeats exactly N times
30 [=N:M] Repeats N to M times
31 iff inside sequence Conditional filtering
SVA COMMAND / CONSTRUCT PURPOSE
Define a simple two-cycle
32 sequence s = a ##1 b;
sequence
property p = @(posedge clk)
33 Sampling with disable condition
disable iff (rst) ... ;
34 assert property (p); Use named property in assertion
35 `s_event => s_result`
36 `a ##1 b ##1 c -> d;`
37 assert final (x == y); Assert at end of simulation
Alternative to assert for
38 expect property (...);
monitoring
39 cover property (...); Functional coverage of assertion
40 cover sequence (...); Sequence coverage
Check assertion result using
41 pass/fail handling
simulators
42 bind module instance Bind assertion module to DUT
Encapsulate assertion in
43 checker ... endchecker
reusable unit
checker_name check_instance
44 Instantiate checker
(...);
clocking cb @(posedge clk); ...
45 Clocking block for sync
endclocking
Evaluate true when sequence
46 triggered
triggers
SVA COMMAND / CONSTRUCT PURPOSE
47 disable iff inside property Disables assertion on condition
48 sequence a = b ##1 c; Define sequence with delay
49 `property p = s -> d;`
50 assert property (@(posedge clk) ... Clocked assertion
51 assert #0 property (...); Assert at time 0
52 local variable inside sequence Use temporary values
53 `property p = $rose(x) => y;`
54 property p = x throughout y; x must stay true during y
55 `property p = (a or b) => c;`
a and b must start and end at
56 a intersect b
same time
Assert that a followed by b
57 property p = !(a ##1 b);
should not occur
Ensure a, b, c occur in given
58 wait_order(a, b, c)
order
59 sequence s = (a ##1 b)[*3]; Sequence repeated 3 times
Sequence must occur 1 to 3
60 property p = (s)[*1:3];
times
61 boolean_expr ##[1:5] b; Delay range in sequences
62 a ##1 (!b)[*3] Ensure !b repeats 3 times after a
Ensures mutually exclusive
63 unique case (expr)
sequence branches
SVA COMMAND / CONSTRUCT PURPOSE
64 `property p = (a and b) => c;`
65 disable iff (!ready) Disable assertion until ready
66 let expr = a ##1 b; Define reusable sequence using let
67 if (condition) assert property (...); Conditional assertion
68 assume property (...); Use in formal tools
69 restrict property (...); Restrict stimulus (formal)
70 global clocking cb; Define global clocking block
71 property p = ##[0:$] (a); a must eventually occur
72 property p = not (a ##1 b); a followed by b should not occur
73 property p = (a ##1 b) within (x ##1 y); Sequence occurs within a boundary
74 `property p = disable iff (reset) (a -> b);`
75 `property p = (s1 ##1 s2) -> s3;`
76 sequence timed = ##[0:10] x; x occurs within 10 cycles
77 covergroup ... with function sample(); Sample for assertion coverage
78 `cover property (a => b);`
79 checker my_check(signal); Parametrized checker
80 `property p = a => ##[1:3] b;`
sequence s = (x ##1 y) intersect (z
81 Intersection of 2 sequences
##1 w);
82 `property p = ##1 disable iff(rst) (a -> b);`
SVA COMMAND / CONSTRUCT PURPOSE
83 sequence nested=(a ##1 (b ##1 c)); Nested sequences
84 property p = (a throughout(##1 b)); a remains true throughout b
85 `assert property (##1 a[*2] => b);`
86 property p = @(negedge clk) Negative edge sampling
87 a ##1 b[*2] ##1 c b repeats twice between a and c
88 `s1 => (s2
89 `assert property (!reset => data == 0);`
90 a ##1 (b intersect c) a followed by simultaneous b & c
91 a ##1 disable iff(rst) b; Reset-safe implication
92 `property p = (x => ##[0:$] y);`
93 `property p = s -> s2
94 sequence s = @(posedge clk) a ##1 Clocked sequence declaration
95 `property p = $fell(signal) => out == 0;`
96 assert final ($past(data) == 1); Final time check using $past
97 `assert property (##[1:$] a => b);`
98 sequence s = a[*0:$]; a may occur zero or more times
cover property ((a ##1 b) intersect Cover when (a followed by b)
99
c); happens at same time as c
100 `assert property ($rose(clk) => req == 1);`
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