Ques

The advantage of RISC processor over CISC processor is that

Which of the following is true about interrupts?
To devices connected to a microprocessor can use the data bus
For which shared (virtual) memory systems is the snooping protocol suited?
Computer system of a parallel computer is capable of
Writing parallel programs is referred to as
Simplifies application’s of three-tier architecture is ____________.
Dynamic networks of networks, is a dynamic connection that grows is called
In which application system Distributed systems can run well?
In which systems desire HPC and HTC.
No special machines manage the network of architecture in which resources are known as
Significant characteristics of Distributed systems have of
Built of Peer machines are over
Type HTC applications are
Virtualization that creates one single address space architecture that of, is called
We have an internet cloud of resources In cloud computing to form
Data access and storage are elements of Job throughput, of __________.
Billions of job requests is over massive data sets, ability to support known as
Broader concept offers Cloud computing .to select which of the following.
Resources and clients transparency that allows movement within a system is called
Distributed program in a distributed computer running a is known as
Uniprocessor computing devices is called__________.
Utility computing focuses on a______________ model.
What is a CPS merges technologies
Aberavationn of HPC
Peer-to-Peer leads to the development of technologies like
Type of HPC applications of.
The development generations of Computer technology has gone through
Utilization rate of resources in an execution model is known to be its
CPU does not perform the operation _____________
A complete microcomputer system consist of _____________
PC Program Counter is also called ________________
In a single byte how many bits will be there?
The access time of memory is ___________ the time required for performing any single CPU operation.
A collection of lines that connects several devices is called ____________.
Memory address refers to the successive memory words and the machine is called as _________
A microprogram written as string of 0's and 1's is a ______________.
A pipeline is like ____________.
Data hazards occur when ________________.
Processors of all computers, whether micro, mini or mainframe must have
What is the control unit's function in the CPU?
What is meant by a dedicated computer?
The most common addressing techiniques employed by a CPU is
Pipeline implement ______________.
Which of the following code is used in present day computing was developed by IBM corporation.
When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the
Interrupts which are initiated by an instruction are
Memory access in RISC architecture is limited to instructions
From where interrupts are generated?
The output of a gate is low when at least one of its input is low . It is true for
Which one of the following is most suitable to make a parity checker
What is the minimum number of flip-flops required in a counter to count 100 pulses?
For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is
Which of the following is true about interrupts?
To devices connected to a microprocessor can use the data bus:
Intel 8080 microprocessor has an instruction set of 91 instruction.
The opcode to implement this instruction set should be at least
Dynamic RAMs are best suited to
Intel Pentium CPU is a
A modem is used to link up two computers via
The maximum integer which can be stored on a 8 bit accumulator is
In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices it could contain
Which of the following memories in a computer is volatile?
A peripheral is
How many bits do you think will be adequate to encode individual character in Devnagari script
Minimum number of spanning tree in a connected graph is
The minimum number of edges required to create a cyclid graph of n vertices is
What will be the running-time of Dijkstra's single source shortest path algorithm,
if the graph G(V,E) is stored in form of adjacency list and binary heap is used
Maximum degree of any vertex in a simple graph of vertices n is
If the data collection is in sorted form and equally distributed then the run time complexity of interpolation search is
A directed graph is ___________ if there is a path from each vertex to every other vertex in the digraph.
Which of the following bus is used to transfer data from main memory to peripheral device?
To provide increased memory capacity for operating system, the
CD -RAW is
Which of the following require large computer memory?
Which major development led to the production of microcomputers?
In immediate addressing the operand is placed
Micro instructions are stored in
Pipeline processing implement
The 16- bit registers in 8085 is
Instruction pipelining has minimum stages
Systems that do not have parallel processing capabilities are
The word size of the microprocessor refers to
How many address lines are needed to address each memory location in a 2048X 4 memory chip?
Who is regarded as the founder of Computer Architecture?
What is characteristic for the organization of a computer architecture?
What is usually regarded as the von Neumann Bottleneck?
How does the number of transistors per chip increase according to Moore ´s law?
Who is regarded as the founder of Computer Science?
Which is the fastest storage unit in a usual memory hierarchy?
Which cache miss does not occur in case of a fully associative cache ?
Which miss even occurs in infinite caches?
What is stored in a Translation Lookaside Buffer?
Which value has the speedup of a parallel program that achieves an efficiency of 75% on 32 processors ?
Pipelining strategy is called implement
The concept of pipelining is most effective in improving performance if the tasks being performed in different stages:
Which Algorithm is better choice for pipelining?
The expression 'delayed load' is used in context of
Parallel processing may occur
The cost of a parallel processing is primarily determined by :
An instruction to provide small delay in program
Characteristic of RISC (Reduced Instruction Set Computer) instruction set is
In daisy-chaining priority method, all the devices that can request an interrupt are connected in
Which one of the following is a characteristic of CISC (Complex Instruction Set Computer)
During the execution of the instructions, a copy of the instructions is placed in the ________.
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps.
For the execution of the same instruction which processor is faster ?
A processor performing fetch or decoding of different instruction during the execution of another instruction is called ___ .
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster executio
The clock rate of the processor can be improved by
An optimizing Compiler does
The ultimate goal of a compiler is to,
SPEC stands for,
As of 2000, the reference system to find the performance of a system is _____ .
When Performing a looping operation, the instruction gets stored in the ______.
The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
If a processor clock is rated as 1250 million cycles per second, then its clock period is ________ .
If the instruction, Add R1,R2,R3 is executed in a system which is pipe-lined,
then the value of S is (Where S is term of the Basic performance equation)
CISC stands for,
As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
The computer architecture aimed at reducing the time of execution of instructions is ________.
The Sun micro systems processors usually follow _____ architecture.
The RISC processor has a more complicated design than CISC.
The iconic feature of the RISC machine among the following are
Both the CISC and RISC architectures have been developed to reduce the______.
Out of the following which is not a CISC machine.
Pipe-lining is a unique feature of _______.
In CISC architecture most of the complex instructions are stored in _____.
Which of the architecture is power efficient?
To which class of systems does the von Neumann computer belong?
Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors
if 5% of a program is sequential and the remaining part is ideally parallel?
Itanium processor: Which hazard can be circumvented by register rotation?
Which MIMD systems are best scalable with respect to the number of processors?
Cache coherence: For which shared (virtual) memory systems is the snooping protocol suited?
Opt1
The hardware architecture is simpler
They are generated when memory cycles are stolen
all the time
Crossbar connected systems
Decentralized computing
Parallel computation
Maintenance
Multithreading
HPC
Adaptivity
Peer-to-Peer
5 types
Many Server machines
Business
Loosely coupled
Centralized computing
Flexibility
Efficiency
Parallel computing
Mobility transparency
Distributed process
Grid computing
Data
5C
High-peak computing
Norming grids
Management
6
Adaptation
Data transfer
microprocessor
instruction pointer
8
Longer than
Bus
word addressable
Symbolic microinstruction
an automobile assembly line
Greater performance loss
ALU
To transfer data to primary storage
which is used by one person only
immediate
fetch instruction
ASCII
stack pointer
internal
CALL and RET
Central processing unit
AND gate
AND gate
Five
Memory state
They are generated when memory cycles are stolen
all the time

bit long
slow system
RISC based
telephone line
112
16
RAM
any drives installed in the computer
12
n
n

Ο(|V|2)
2n - 1
Ο(n)
Weakly connected
DMA bus
virtual memory is created
Input device only
Imaging
Magnetic disks
in the CPU register
computer memory
fetch instruction
general purpose register
4
SISD
the amount of a information that can be stored in a byte
10
Alan Turing
Size
Processor/memory interface
Quadratically
Alan Turing
Cache
Conflict miss
Coherence miss
System dumps
18
instruction execution
require different amount of time
Small Algorithm
processor-printer communication
in the instruction stream
Time Complexity
LDA
three instructions per cycle
parallel
Fixed format instructions
Register
 A
Super-scaling
ISA
Improving the IC technology of the logic circuits
Better compilation of the given piece of code.
Reduce the clock cycles for a programming task.
Standard Performance Evaluation Code.
Ultra SPARC 10
Registers
ISA
1.9 * 10 ^ -10 sec

3
Complete Instruction Sequential Compilation
Intel Atom SParc 300Mhz
CISC
CISC
1
Reduced number of addressing modes
Cost
IBM 370/168
RISC
Register
CISC
SIMD (Single Instruction Multiple Data)
Infinite speedup
Control hazards
Distributed memory computers
Crossbar connected systems
Opt2
An instruction can be executed in one cycle
They are used in place of data channels
at regular interval of time
Systems with hypercube network
Parallel computing
Parallel processes
Initiation
Cyber cycle
HTC
Transparency
Space based
2 types
1 Server machine
Engineering
Peer-to-Peer
Decentralized computing
Adaptation
Dependability
Centralized computing
Concurrency transparency
Distributed program
Centralized computing
Cloud
2C
High-peripheral computing
Data grids
Media mass
3
Efficiency
Logic operation
memory
memory pointer
18
Shorter than
Peripheral connection wires
byte addressable
binary microinstruction
house pipeline
Pipeline changes the order of read/write access to operands
Primary Storage
to store program instruction
which is assigned to one and only one task
direct
decode instruction
Hollerith Code
accumulator
external
PUSH and POP
Memory chips
OR gate
OR gate
seven
Set state
They are used in place of data channels
at regular interval of time

5 bit long
large system
CISC based
dedicated line
200
64
ROM
tapedrive connected to a computer
16
n(n - 1)
n+1

Ο(|V| log |V|)

n
Ο(1)
Strongly Connected
Output bus
cache memory is increased
output device only
Graphics
floppy disks
after opcode in the instruction
primary storage
decode instruction and fetch operand
accumulator
2
SIMD
the amount of a information that can be stored in a cycle
11
Konrad Zuse
Dynamic behaviour
Control unit
Linearly
Konrad Zuse
Main memory
Capacity miss
Capacity miss
Physical addresses
24
instruction prefetch
require about the same amount of time
Hash Algorithm
memory-monitor communication
in the data stream
Switching Complexity
NOP
two instructions per cycle
serial
Variable format instructions
RAM
B
Pipe-lining
ANSA
Reducing the amount of processing done in one step
Takes advantage of the type of processor and reduces its process time.
Reduce the size of the object code.
System Processing Enhancing Code.
SUN SPARC
Cache
Pipe-lining
1.6 * 10 ^ -9 sec
~2
Computer Integrated Sequential Compiler
Ultra SPARC -IIi 300MHZ
RISC
ISA
0
Increased memory size
Time delay
VAX 11/780
CISC
Diodes
RISC
MIMD (Multiple Instruction Multiple Data)

5
Data hazards
ccNUMA systems
Systems with hypercube network
Opt3
Less number of registers accommodate in chip
They can be generated by arithmetic operation
only when it’s sending or receiving data
Systems with butterfly network
Centralized computing
Parallel development
Implementation
Internet of things
HRC
Dependency
Tightly coupled
3 types
1 Client machine
Science
Space-based
Parallel computing
Efficiency
Adaptation
Utility computing
Performance transparency
Distributed application
Parallel computing
Scalable
3C
High-performance computing
Computational grids
Business
4
Dependability
All of the above
peripheral equipment
data counter
4
Negligible than
Both a and b
bit addressable
symbolic microinstruction
both a and b
Some functional unit is not fully pipelined
Control unit
to perform logic operations
which does one kind of software
indirect
calculate operand
Baudot code
program counter
hardware
STA and LDA
Registers
NAND gate
Exclusive- OR gate
ten
Reset state
They can be generated by arithmetic operation
only when it’s sending or receiving data

7 bit long
one bit system
Both of the above
Both of the above
255
256
EPROM
any physical device connected to the computer
64
1
n-1

Ο(|E|+|V| log |V|)

n+1
Ο(log n)
Tightly Connected
Data bus
memory for OS is reserved
Both of the above
Voice
Logic gates
in the memory
secondary storage
calculate operand and execute instruction
stack pointer and program counter
3
MIMD
The number of machine operations performed in a second
8
John von Neumann
Static behaviour
Arithmetic logical unit
Cubicly
J. Presper Eckert
Hard disk
Compulsory miss
Conflict miss
program data
16
instruction decoding
require different amount of time with time difference between any two tasks being same
Merge-Sort Algorithm
pipelining
both[A] and [B]
Circuit Complexity
BEA
one instruction per cycle
random
Instructions are executed by hardware
System heap
Both take the same time
Parallel Computation
Super-scalar
By using overclocking method
Does better memory managament.
Be versatile.
System Performance Evaluation Corporation.
SUN II
System Heap
Super-scaling
1.25 * 10 ^ -10 sec
~1
Complex Instruction Set Computer
Amd Neutrino series
ISA
ULTRA SPARC
May be False
Having a branch delay slot
Semantic gap
Intel 80486
ISA
CMOS
ISA
MISD (Multiple Instruction Single Data)

20
Structural hazards
nccNUMA systems
Systems with butterfly network
Opt4 CrtOpt
Parallel execution capabilities quesOptID3
They can indicate completion of an I/O operation quesOptID4
when the microprocessor is reset quesOptID3
Bus based systems quesOptID4
None of the above quesOptID1
Parallel programming quesOptID4
Deployment quesOptID4
Cyber-physical system quesOptID3
Both A and B quesOptID4
Secretive quesOptID2
Loosely coupled quesOptID1
4 types quesOptID3
Many Client machines quesOptID4
Media mass quesOptID1
Tightly coupled quesOptID3
All of these quesOptID4
Dependability quesOptID3
Flexibility quesOptID3
Decentralized computing quesOptID3
Replication transparency quesOptID1
Distributed computing quesOptID2
Distributed computing quesOptID2
Business quesOptID4
4C quesOptID3
Highly-parallel computing quesOptID3
Both A and B quesOptID4
Science quesOptID4
5 quesOptID4
Flexibility quesOptID2
Arithmetic operation quesOptID1
all of the above quesOptID4
file pointer quesOptID1
32 quesOptID1
Same as quesOptID1
Internal wires quesOptID1
Terra byte addressable quesOptID1
binary micro-program quesOptID4
a gas line quesOptID1
Machine size is limited quesOptID2
All of above quesOptID4
to decode program instruction quesOptID3
which is meant for application software only quesOptID2
all of the above quesOptID4
all of the above quesOptID4
EBCDIC code quesOptID4
Stack quesOptID4
software quesOptID2
MOV and JMP quesOptID3
I/O devices quesOptID4
NOR gate quesOptID1
None of the above quesOptID3
hundred quesOptID2
Unused state quesOptID4
They can indicate completion of an I/O operation quesOptID1
when the microprocessor is reset quesOptID3

9 bit long quesOptID3

none of the above quesOptID1
none of the above quesOptID1
none of the above quesOptID3
224 quesOptID3
65536 quesOptID3
ALL quesOptID1
None of above quesOptID3
10 quesOptID4
0 quesOptID2
2n quesOptID1

None of these quesOptID3

n-1 quesOptID4
Ο(log (log n)) quesOptID4
Linearly Connected quesOptID3
All of the above quesOptID3
Additional memory is installed quesOptID1
None of the above quesOptID2
All of the above quesOptID4
Integrated Circuits quesOptID4
in the stack quesOptID2
control memory quesOptID4
all of the above quesOptID4
all of the above quesOptID3
6 quesOptID2
All of the above quesOptID1
the maximum length of an English word that can be input to a computer quesOptID2
12 quesOptID2
John William Mauchly quesOptID3
Speed quesOptID2
Instruction set quesOptID1
Exponentially quesOptID4
John William Mauchly quesOptID1
Register quesOptID4
Cold start miss quesOptID1
Cold start miss quesOptID4
Operating system log files quesOptID2
20 quesOptID2
instruction manipulation quesOptID2
require different amount with time difference between any two tasks being different quesOptID2
Quick-Sort Algorithm quesOptID3
none of the above quesOptID3
none of the above quesOptID3
None of the above quesOptID3
None of the above quesOptID2
None of the above quesOptID3
None of the above quesOptID2
None of the above quesOptID2
Cache quesOptID4
Insuffient information quesOptID1
None of these quesOptID2
All of the above quesOptID3
All of the above quesOptID4
Both a and c quesOptID2
Be able to detect even the smallest of errors. quesOptID1
Standard Processing Enhancement Corporation. quesOptID3
None of these quesOptID1
System stack quesOptID2
Sequential quesOptID3
8 * 10 ^ -10 sec quesOptID4
6
quesOptID3
Complex Instruction Sequential Compilation quesOptID3
ASUS A series 450 Mhz quesOptID2
ANNA quesOptID2
RISC quesOptID4
may be true quesOptID2
All of the above quesOptID3
All of the above quesOptID3
Motorola A567 quesOptID4
IANA quesOptID1
Transistors quesOptID4
IANA quesOptID2
SISD (Single Instruction Single Data) quesOptID4

50 quesOptID3
None of the answers quesOptID2
Symmetric multiprocessors quesOptID1
Bus based systems quesOptID4