02/09/17

Lecture 21: VERILOG TEST BENCH

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Verilog Test Bench

• What is test bench?
– A Verilog procedural block that executes only once.
– Used for simulaFon.
– Test bench generates clock, reset, and the required test vectors for a given
design-under-test (DUT).
– The test bench can monitor the DUT outputs and present them in a way as
specified by the creator.
• Print the values of the signal lines.
• Dump the values in a file from where waveforms can be viewed.

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• Basic requirements:
– The inputs of the DUT need to be connected to the test bench.
– The outputs of the DUT needs also to be connected to the test bench.
• Points to note:
– Test benches use the “ini,al” procedural block that executes only once.
– Can also use “always” for generaFng some test inputs, like a clock signal.

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TEST BENCH

Design Under
SFmulus Test Monitor
(DUT)

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A Simple Example module testbench;

reg A,B,C,D,E,F; wire Y;
example DUT(A,B,C,D,E,F,Y);
module example (A,B,C,D,E,F,Y);
input A,B,C,D,E,F; initial
output Y; begin
wire t1, t2, t3, Y; $monitor ($time,” A=%b, B=%b, C=%b,
nand #1 G1 (t1,A,B); D=%b, E=%b, F=%b, Y=%b”,
and #2 G2 (t2,C,~B,D); A,B,C,D,E,F,Y);
nor #1 G3 (t3,E,F); #5 A=1; B=0; C=0; D=1; E=0; F=0;
nand #1 G4 (Y,t1,t2,t3); #5 A=0; B=0; C=1; D=1; E=0; F=0;
endmodule #5 A=1; C=0;
#5 F=1;
#5 $finish;
end
endmodule

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How to write test benches?

• Create a dummy template
– Declare inputs to the design-under-test (DUT) as “reg”, and the outputs as
“wire”.
• Because we have to iniFalize the DUT inputs inside procedural block(s),
typically “ini,al”, where only “reg” type variables can be assigned.
– InstanFate the DUT.
• IniFalizaFon and Monitoring
– Assign some known values to the DUT inputs.
– Monitor the DUT outputs for funcFonal verificaFon.

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• For synchronous sequenFal circuits:

– We need some clock generaFon logic.
– Various ways to specify clock signal.
• Test bench can include various simulator direcFves:
– $display, $monitor, $dumpfile, $dumpvars, $finish, etc.
• Important point:
– We do not need test bench when we are synthesizing a design.
– Required only during simulaFon.

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The Simulator DirecAves

• $display (“<format>”, expr1, expr2, …);
– Used to print the immediate values of text or variables to stdout.
– Syntax is very similar to “prina” in C.
– AddiFonal format specifiers are supported, like “b” (binary), “h” (hexadecimal), etc.
• $monitor (“<format>”, var1, var2, …);
– Similar in syntax to $display, but does not print immediately.
– It will print the value(s) whenever the value of some variable(s) in the given list
changes.
– Has the funcFonality of event-driven print.

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• $finish;
– Terminates the simulaFon process.
• $dumpfile (<filename>);
– Specifies the file that will be used for storing the values of the selected variables so
that they can be graphically visualized later.
– The file typically has an extension .vcd (Value Change Dump), and contains
informaFon about any value changes on the selected variables.
• $dumpoff;
– This direcFve stops the dumping of variables. All variables are dumped with “x”
values and the next change of variables will not be dumped.
• $dumpon;
– This direcFve starts previously stopped dumping of variables.

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• $dumpvars (level, list_of_variables_or_modules);

– Specifies which variables should be dumped to the .vcd file.
– Both the parameters are opFonal; if both are omided, all variables are dumped.
– If level=0, then all variables within the modules from the list will be dumped. If any
module from the list contains module instances, then all variables from these
modules will also be dumped.
– If level=1, then only listed variables and variables of listed modules will be dumped.
• $dumpall;
– The current values of all variables will be wriden to the file, irrespecFve of whether
there has been any change in their values or not.
• $dumplimit (filesize);
– Used to set the maximum size of the .vcd file.

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A Complete Example :: 2-bit equality checker

`timescale 1ns / 100ps
module comparator (x, y, z);
input [1:0] x, y; output z;
assign z = (x[0]&y[0]&x[1]&y[1]) |
(~x[0]&~y[0]&x[1]&y[1]) |
(~x[0]&~y[0]&~x[1]&~y[1]) |
(x[0]&y[0]&~x[1]&~y[1]);
endmodule

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`timescale 1ns / 100ps

module testbench;
reg [1:0] x, y; wire z;
comparator C2 (.x(x), .y(y), .z(z));
initial
begin
$dumpfile (“comp.vcd”);
$dumpvars (0, testbench);
x = 2’b01; y = 2’b00;
#10 x = 2’b10; y = 2’b10;
#10 x = 2’b01; y = 2’b11;
end
initial
begin
$monitor (“t=%d x=%2b y=%2b z=%d”, $time, x, y, z);
end
endmodule

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END OF LECTURE 21

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Lecture 22: WRITING VERILOG TEST BENCHES

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

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WriAng Test Benches

• We shall be illustraFng the process of wriFng test benches through a number
of examples.
• We shall be looking at how to:
– Write test benches for combinaFonal designs.
– Write test benches for sequenFal designs.
– Generate clock and synchronize the applied inputs.
– AutomaFcally verifying the outputs generated by the design under test.
– GeneraFng random test vectors.

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Example 1: Full Adder

module full_adder (s, co, a, b, c);

input a, b, c;
output s, co;
assign s = a ^ b ^ c;
assign co = (a & b) | (b & c) | (c & a);
endmodule

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module testbench;
reg a, b, c; wire sum, cout;
full_adder FA (sum, cout, a, b, c);

initial
begin
$monitor ($time,” a=%b, b=%b, c=%b, sum=%b, cout=%b”,
a, b, c, sum, cout);
#5 a=0; b=0; c=1;
#5 b=1; 0 a=x, b=x, c=x, sum=x, cout=x
#5 a=1; 5 a=0, b=0, c=1, sum=1, cout=0
#5 a=0; b=0; c=0; 10 a=0, b=1, c=1, sum=0, cout=1
#5 $finish; 15 a=1, b=1, c=1, sum=1, cout=1
end 20 a=0, b=0, c=0, sum=0, cout=0
endmodule

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module testbench; T= 5, a=0, b=0, c=1, sum=1, cout=0

reg a, b, c; wire sum, cout; T=10, a=0, b=1, c=1, sum=0, cout=1
full_adder FA (sum, cout, a, b, c); T=15, a=1, b=1, c=1, sum=1, cout=1
T=20, a=0, b=0, c=0, sum=0, cout=0
initial
begin
a=0; b=0; c=1; #5;
$display (“T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b”,$time,a,b,c,sum,cout);
b=1; #5;
$display (“T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b”,$time,a,b,c,sum,cout);
a=1; #5;
$display (“T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b”,$time,a,b,c,sum,cout);
a=0; b=0; c=0; #5;
$display (“T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b”,$time,a,b,c,sum,cout);
#5 $finish;
end
endmodule

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by writing {a,b,c} , a b c have been concatenated ie: they act as a single 3 bit unit
eg: 000, 001, 111 etc 02/09/17

T= 5, a=0, b=0, c=0, sum=0, cout=0

module testbench; T=10, a=0, b=0, c=1, sum=1, cout=0
reg a, b, c; wire sum, cout;
T=15, a=0, b=1, c=0, sum=1, cout=0
integer i;
full_adder FA (sum, cout, a, b, c); T=20, a=0, b=1, c=1, sum=0, cout=1
T=25, a=1, b=0, c=0, sum=1, cout=0
initial T=30, a=1, b=0, c=1, sum=0, cout=1
begin T=35, a=1, b=1, c=0, sum=0, cout=1
for (i=0; i<8; i=i+1) T=40, a=1, b=1, c=1, sum=1, cout=1
begin
{a,b,c} = i; #5;
$display ("T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b",
$time, a, b, c, sum, cout);
end
#5 $finish;
end
endmodule

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module testbench;
reg a, b, c; wire sum, cout; T= 5, a=0, b=0, c=0, sum=0, cout=0
integer i; T=10, a=0, b=0, c=1, sum=1, cout=0
full_adder FA (sum, cout, a, b, c); T=15, a=0, b=1, c=0, sum=1, cout=0
T=20, a=0, b=1, c=1, sum=0, cout=1
initial T=25, a=1, b=0, c=0, sum=1, cout=0
begin
$dumpfile (“fulladder.vcd”);
T=30, a=1, b=0, c=1, sum=0, cout=1
$dumpvars (0, testbench); T=35, a=1, b=1, c=0, sum=0, cout=1
for (i=0; i<8; i=i+1) T=40, a=1, b=1, c=1, sum=1, cout=1
begin
{a,b,c} = i; #5;
$display ("T=%2d, a=%b, b=%b, c=%b, sum=%b, cout=%b",
$time, a, b, c, sum, cout);
end
#5 $finish;
end
endmodule

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module shiftreg_4bit (clock, clear, A, E);

Example 2: input clock, clear, A;
output reg E;
4-bit shiR reg B, C, D;
register always @(posedge clock or negedge clear)
begin
if (!clear) begin B<=0; C<=0; D<=0; E<=0; end
else begin
E <= D;
D <= C;
C <= B;
B <= A;
end
end
endmodule

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module shift_test;
reg clk, clr, in; wire out; integer i;
shiftreg_4bit SR (clk, clr, in, out);

initial
begin clk = 1'b0; #2 clr = 0; #5 clr = 1; end

always #5 clk = ~clk;

initial begin #2;

repeat (2)
begin #10 in=0; #10 in=0; #10 in=1; #10 in=1; end
end

initial
begin
$dumpfile ("shifter.vcd");
$dumpvars (0, shift_test);
#200 $finish;
end
endmodule

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module counter (clear, clock, count);

Example 3: parameter N = 7;
7-bit binary input clear, clock;
output reg [0:N] count;
counter
always @(negedge clock)
if (clear)
count <= 0;
else
count <= count + 1;
endmodule

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module test_counter;
reg clk, clr;
wire [7:0] out;

counter CNT (clr, clk, out); initial

begin
initial clk = 1'b0; $dumpfile ("counter.vcd");
$dumpvars (0, test_counter);
always #5 clk = ~clk; $monitor ($time, " Count: %d", out);
end
initial
begin endmodule
clr = 1'b1;
#15 clr = 1'b0;
#200 clr = 1'b1;
#10 $finish;
end

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0 Count: 0 140 Count: 13

20 Count: 1 150 Count: 14
30 Count: 2 160 Count: 15
40 Count: 3 170 Count: 16
50 Count: 4 180 Count: 17
60 Count: 5 190 Count: 18
70 Count: 6 200 Count: 19
80 Count: 7 210 Count: 20
90 Count: 8 220 Count: 0
100 Count: 9
110 Count: 10
120 Count: 11
130 Count: 12

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module fulladder (a, b, c, s, cout);

Example 4: input a, b, c;
AutomaAc output s, cout;
verificaAon of assign s = a ^ b ^ c;
output
assign cout = (a&b) | (b&c) | (c&a);

endmodule

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module fulladder_test; #5 a=1; b=1; c=1; #5;

if ((s != 1) || (cout != 1))
reg a,b,c; correct = 0;
wire s, cout;
integer correct; #5 a=0; b=1; c=0; #5;
if ((s != 1) || (cout != 0))
fulladder FA (a,b,c,s,cout); correct = 0;

initial #5 $display ("%d", correct);

begin end
correct = 1;
endmodule
#5 a=1; b=1; c=0; #5;
if ((s != 0) || (cout != 1))
correct = 0; Shall display 1 if outputs are correct; and
display 0 otherwise.

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module adder (out, cout, a, b);

Example 5: input [7:0] a, b;
GeneraAng output [7:0] out;
output cout;
random test
vectors assign #5 {cout,out} = a + b;
endmodule

• The system task $random can be used to generate a random number.

• It is called as : $random (<seed>)
• The value of <seed> is opFonal and is used to ensure that the same sequence of
random numbers are generated each Fme the test is run.

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module test_adder;
reg [7:0] a, b; T: 10, a: 00, b: 52, sum: 52
wire [7:0] sum; wire cout; T: 20, a: ca, b: 08, sum: d2
integer myseed; T: 30, a: 0c, b: 6a, sum: 76
adder ADD (sum, cout, a, b); T: 40, a: b1, b: 71, sum: 22
initial myseed = 15; T: 50, a: 23, b: df, sum: 02
initial
begin
repeat (5)
begin
a = $random(myseed);
b = $random(myseed); #10;
$display ("T: %3d, a: %h, b: %h, sum: %h", $time, a, b, sum);
end
end
endmodule

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END OF LECTURE 22

Hardware Modeling Using Verilog 33

Lecture 23: MODELING FINITE STATE MACHINES

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

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IntroducAon
• CombinaFonal and SequenFal Circuits
– In a combinaFonal circuit, the outputs depend only on the applied input
values and not on the past history.
– In a sequenFal circuit, the outputs depend not only on the applied input
values but also on the internal state.
• The internal states also change with Fme.
• The number of states is finite, and hence a sequenFal circuit is also referred to
as a Finite State Machine (FSM).
• Most of the pracFcal circuits are sequenFal in nature.

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Finite State Machine (FSM)

• A FSM can be represented either in the form of a state table or in the form of a
state transi,on diagram.
– VariaFons exist, e.g. Algorithmic State Machine (ASM) chart.
• Example:
– A circuit to detect 3 or more 1’s in a serial bit stream.
– The bits are applied serially in synchronism with a clock.
– The output will become 1 whenever it detects 3 or more consecuFve 1’s in the
stream.

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State Table State Diagram

Reset PS Input NS Output 0/0
1 - - A 0 0/0
0 A 0 A 0 A B
0 A 1 B 0 1/0
0 B 0 A 0 Reset
0/0 1/0
0 B 1 C 0
0 C 0 A 0 0/0
0 C 1 D 1
D C 0/0
0 D 0 A 0 1/1
0 D 1 D 1
1/1 input/output

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Mealy and Moore FSM Types

• A determinisFc FSM can be mathemaFcally defines as a 5-tuple
(Σ, Γ, S, s0, δ, ω)
where Σ is the set of input combinaFons, Γ is the set of output combinaFons,
S is a finite set of states, s0 ε S is the iniFal state, δ is the state-transiFon
funcFon, and ω is the output funcFon.
• Here, δ : S x Σ à S
– Present state (PS) and present input determines the next state (NS).
• For Mealy machine, ω : S x Σ à Γ (output depends on state + inputs)
• For Moore machine, ω : S à Γ (output depends only on the state)

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Pictorial DepicAon

PI NS NS Output Mealy
F/F PS PO
Logic Logic Machine

PI NS NS PS Output
PO Moore
F/F
Logic Logic Machine

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Example 1
• There are three lamps, RED, GREEN and YELLOW, that should glow cyclically
with a fixed Fme interval (say, 1 second).
• Some observaFons:
– The FSM will have three states, corresponding to the glowing state of the lamps.
– The input set is null; state transiFon will occur whenever clock signal comes.
– This is a Moore Machine, since the lamp that will glow only depends on the state
and not on the inputs (here null).
RED
RED
clock GREEN
GREEN YELLOW
YELLOW

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module cyclic_lamp (clock, light);

input clk;
output reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010, YELLOW=3’b001;
reg [0:1] state;
always @(posedge clock)
case (state)
S0: begin // S0 means RED
light <= GREEN; state <= S1;
end default: begin
S1: begin // S1 means GREEN light <= RED;
light <= YELLOW; state <= S2; state <= S0;
end end
S2: begin // S2 means YELLOW endcase
light <= RED; state <= S0; endmodule
end

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module test_cyclic_lamp;
reg clk; 0 RGY: xxx
wire [0:2] light; 5 RGY: 100
cyclic_lamp LAMP (clk, light); 15 RGY: 010
25 RGY: 001
always #5 clk = ~clk;
35 RGY: 100
initial 45 RGY: 010
begin 55 RGY: 001
clk = 1'b0; 65 RGY: 100
#100 $finish; 75 RGY: 010
end
85 RGY: 001
initial 95 RGY: 100
begin
$dumpfile ("cyclic.vcd"); $dumpvars (0, test_cyclic_lamp);
$monitor ($time, " RGY: %b", light);
end
endmodule

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• Some comments on the soluFon:

– The synthesis tool will generate five flip-flops – 2 for state, and 3 for light.
– The three output lines are also gerng stored in flip-flops.
• We have used non-blocking assignment triggered by clock edge.
– But actually we do not need separate flip-flops for the outputs, as the
outputs can be directly generated from the state.
– How to achieve this?
• Modify the Verilog code such that all assignments to light is made in a separate
“always” block.
• Use blocking assignment triggered by state change, and not by clock.

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module cyclic_lamp (clock, light);

input clk;
output reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010, YELLOW=3’b001;
reg [0:1] state;
always @(posedge clk) always @(state)
case (state) case (state)
S0: state <= S1; S0: light = RED;
S1: state <= S2; S1: light = GREEN;
S2: state <= S0; S2: light = YELLOW;
default: state <= S0; default: light = RED;
endcase endcase
endmodule

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• Comment on the soluFon:

– The synthesis tool will be generaFng only 2 flip-flops corresponding to the
first clock-triggered “always” block.
– The second “always” block will be generaFng a combinaFonal circuit that
takes state as input and produces light as outputs.
state (s1s0) Light (RGY)
Logic expressions aser minimizaFon:
S0: 00 100
S1: 01 010 R = s0’.s1’
G = s0
S2: 10 001
Y = s1
11 xxx

Hardware Modeling Using Verilog 45

END OF LECTURE 23

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Lecture 24: MODELING FINITE STATE MACHINES

(contd.)
PROF. INDRANIL SENGUPTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Example 2
• Design of a serial parity detector.
– A conFnuous stream of bits is fed to a circuit in synchronism with a clock. The
circuit will be generaFng a bit stream as output, where a 0 will indicate “even
number of 1’s seen so far” and a 1 will indicate “odd number of 1’s seen so far”.
– Also a Moore Machine.

0/0 0/1
1/1
x
z EVEN ODD
clk
IniFal 1/0
state

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module parity_gen (x, clk, z);

input x, clk;
output reg z;
reg even_odd; // The machine state
parameter EVEN=0, ODD=1;
always @(posedge clk)
case (even_odd) This design will cause the
EVEN: begin synthesis tool to generate
z <= x ? 1 : 0; a latch for the output
even_odd <= x ? ODD : EVEN; “even_odd”.
end
ODD: begin
z <= x ? 0 : 1;
even_odd <= x ? EVEN : ODD;
end
default: even_odd <= EVEN;
endcase
endmodule Hardware Modeling Using Verilog 49

module test_parity;
reg clk, x; wire z;
parity_gen PAR (x, clk, z);
initial
begin
$dumpfile ("parity.vcd"); $dumpvars (0, test_parity);
clk = 1'b0;
end
always #5 clk = ~clk;
initial
begin
#2 x = 0; #10 x = 1; #10 x = 1; #10 x = 1;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 $finish;
end
endmodule
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module parity_gen (x, clk, z);

input x, clk; output reg z;
reg even_odd; // The machine state
parameter EVEN=0, ODD=1;
always @(posedge clk)
case (even_odd) This design will not cause
EVEN: even_odd <= x ? ODD : EVEN;
the synthesis tool to
ODD: even_odd <= x ? EVEN : ODD;
default : even_odd <= EVEN; generate a latch for the
endcase output “z”.
always @(even_odd)
case (even_odd)
EVEN: z = 0;
ODD: z = 1;
endcase
endmodule

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Example 3
• Design of a sequence detector.
– A circuit accepts a serial bit stream “x” as input and produces a serial bit stream “z”
as output.
– Whenever the bit padern “0110” appears in the input stream, it outputs z = 1; at all
other Fmes, z = 0.
– Overlapping occurrences of the padern are also detected.
– This is a Mealy Machine.
– Example: x :- 0 1 0 1 0 1 1 0 1 1 0 0 1 0 1 1 0 1 1 1 0
z :- 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0

Hardware Modeling Using Verilog 53

x The input bits “x” are applied in

z
clock synchronism with the clock.

reset
1/0
1/0 0/0
0/0 1/0 1/0
S0 S1 S2 S3

0/0
reset 0/1

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// Sequence detector for pattern “0110”

module seq_detector (x, clk, reset, z); S1: begin
input x, clk, reset; z = x ? 0 : 0;
output reg z; NS = x ? S2 : S1;
parameter S0=0, S1=1, S2=2, S3=3; end
reg [0:1] PS, NS; S2: begin
z = x ? 0 : 0;
always @(posedge clk or posedge reset)
NS = x ? S3 : S1;
if (reset) PS <= S0;
end
else PS <= NS;
S3: begin
always @(PS,x) z = x ? 0 : 1;
case (PS) NS = x ? S0 : S1;
S0: begin end
z = x ? 0 : 0; endcase
NS = x ? S0 : S1; endmodule
end

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module test_sequence;
reg clk, x, reset; wire z;
seq_detector SEQ (x, clk, reset, z);
initial
begin
$dumpfile ("sequence.vcd"); $dumpvars (0, test_sequence);
clk = 1'b0; reset = 1'b1;
#15 reset = 1'b0;
end
always #5 clk = ~clk;
initial
begin
#12 x = 0; #10 x = 0; #10 x = 1; #10 x = 1;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 $finish;
end
endmodule

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Example 4
• Design a sequence detector for the bit padern “101010”.
– Work out the state diagram in a similar way.
– Then code the state diagram in Verilog.

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END OF LECTURE 24

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