Problem 1: Why is a flip-flop called a bistable device?

A flip-flop is called a bistable device because it has two stable states. These two states are:

1. Logic 1 (high)
2. Logic 0 (low).

It can remain in either of these states indefinitely until a specific input signal causes it to switch
to the other state. This two-state characteristic is fundamental to its use as a basic memory
element.

Problem 2: Differentiate between a latch and a flip-flop.

Feature Latch Flip-Flop

Clock Input No clock input Has a clock input

Level-sensitive. Its output can Edge-triggered. Its output changes

Triggering change whenever the enable input only at the positive or negative edge of
is active. the clock signal.

Used for synchronous circuits,

Used for asynchronous circuits, data
Application counters, registers, and sequential
storage, and simple latches.
logic.

Synchronization Asynchronous operation. Synchronous operation.

Example SR latch, D
JK flip-flop, T flip-flop
latch.
Problem 3: Compare the timing behavior of SR, JK, D, and T flip-flops. Which one is most
suitable for counters? Why?

• SR Flip-flop: The output changes based on the S and R inputs. The S=1, R=1 input
combination is forbidden as it leads to an unpredictable state.

• JK Flip-flop: It behaves like an SR flip-flop but resolves the forbidden state. The J=1, K=1
input combination toggles the output.

• D Flip-flop: The output follows the D input, but only at the active clock edge. It's
essentially a one-bit delay element.

• T Flip-flop: The output toggles its state (T for "toggle") whenever the T input is high and
a clock pulse arrives.

Most suitable for counters: The T flip-flop and JK flip-flop are most suitable for counters.

Counters are designed to toggle their state in a sequential manner. A T flip-flop's primary
function is to toggle, which perfectly aligns with the operation of a counter. A JK flip-flop with
J=1 and K=1 also operates in toggle mode, making it an excellent choice as well.
Problem 4: Design a synchronous 3-bit up-down counter using T flip-flops.

Circuit Diagram :

Wave form :
Problem 5: Explain the difference between edge-triggered and level-triggered flip-flops.

Feature Edge-Triggered Level-Triggered

Response Only when signal transitions While the signal is HIGH or
LOW
Behavior Captures input at clock edge Continuously reacts to input
only
Example Device Flip-Flop Latch
Application Synchronous sequential circuits Simple data storage,
(counters, registers, etc.). asynchronous logic.

Problem 6: Why can't we use an SR flip-flop when both inputs are 1?

When both S (Set) and R (Reset) inputs of an SR flip-flop are 1, the output is unpredictable. In
the NOR-gate based SR latch, both outputs Q and Q' are forced to 0. When the inputs return to
S=0, R=0, the final state of the flip-flop depends on which NOR gate's output responds faster,
leading to a race condition. The resulting state is unknown and unstable, making this input
combination "forbidden."

Problem 7: Compare asynchronous (ripple) and synchronous flip-flop-based circuits in terms

of propagation delay.

Feature Asynchronous (Ripple) Synchronous

Only first FF clocked directly; others triggered by All FFs triggered by same
Clock triggering
previous outputs clock

Propagation Limited to longest logic

Cumulative (n × tp)
delay path

Speed Slower for large n Faster, scalable

Glitches More prone Minimal

Circuit
Simple Slightly more complex
complexity
Problem 8: A JK flip-flop is often called a universal flip-flop. Justify this statement.

A universal flip-flop means it can emulate other basic flip-flops by appropriate selection of
inputs.

The JK flip-flop is considered universal because it can be configured to operate as an SR, D, or T

flip-flop.

1. To behave like an SR flip-flop:

o Use J = S, K = R, but avoid J = K = 1 (to prevent toggle).

o So it can perform Set and Reset operations like an SR flip-flop.

2. To behave like a D flip-flop:

o Connect inputs as: J = D, K = D‾\overline{D}D

o Then Q(next) = D

o It replicates a D flip-flop’s behavior.

3. To behave like a T flip-flop:

o Connect J = K = T

o Then Q(next) = Q ⊕ T (toggle behavior)

o It acts exactly like a T flip-flop.

Problem 9: Compare serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-
out (PISO), and parallel-in parallel-out (PIPO) registers in terms of speed and hardware
complexity.

Register
Speed Hardware Complexity
Type

Slowest. Requires n clock cycles to load and n Least complex. Simple chain of
SISO
clock cycles to unload an n-bit word. flip-flops.

Relatively slow for loading. Requires n clock

More complex than SISO.
SIPO cycles to load a word. Fast for reading. All bits
Requires additional output lines.
are available simultaneously.

Fast for loading. All bits are loaded in one clock More complex than SIPO.
PISO cycle. Slow for reading. Requires n clock cycles to Requires parallel load control
shift out the data. logic and multiplexers.

Fastest. Loading and reading are both parallel, Most complex. Each flip-flop
PIPO
taking only one clock cycle for each operation. requires a parallel load input.

Problem 10: A 4-bit right shift register is initially loaded with the value 1011.