Voltage Loop Compensation Procedure
START
STEP 1 - Disable Non-Linear Control STEP 4 - PID Optimization at Low
Non-Linear Control ATR/FATR/Non-Linear Frequency Load Transient
Disable ATRH1/2, ATRL, FATR, non-linear Ki
and zero out PID during ATR
STEP 5 – Load Frequency Sweep
and further optimize PID
STEP2 - Enter Output Model Non-Linear Control may need to be
added to fix the excessive overshoot
or undershoot
N Started with
Y
good config
file?
N Able to
STEP3 – Copy meet spec?
Recommended PID
Click on Calculate and Y
Copy Rec. PID<<<
Increase switching STEP 6 – Measure Bode Plot
frequency, add more with Network Analyzer
output caps, or reduce
output inductance
Sufficient N
phase & gain
margin?
Y
END
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Feedback loop
Bode Plot Type:
Pull down menu where different types Bode plot
of Bode plots can be selected Shown for the condition that is selected
under the Bode Plot Type button
Phase /Gain Margin is calculated
based on the parameters entered in
Model tab
BW Bandwidth. Where gain passes 0dB
PM Phase Margin
GM Gain Margin
For Information these parameters are
shown
Double Pole: The pole due to output L
and C
Fsw: Switching frequency
Nph: Number of phases
Input voltage: Used for calculations
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Feedback loop Model
Recommend to start with the Model tab as
Bode plot depends on Model being set up
with what values used.
Any derating of Ceramic capacitors must be
considered before entering Capacitor
values.
Lbuck:
Here the Inductor value is entered. This
Inductance value is saved in a register
inside the controller and important to set
correct for calculations to be right.
Other L and C related values on this page
is used by GUI only for Bode plot and
simulations. They are not saved in
controller
Model simulates a CPU in a socket. Cap
bank 1 and 2 are MLCC and bulk
capacitors after inductors. Bank 3 and 4 are
MLCC capacitors inside the socket.
Parasitic inductor L2 and RL2 simulate the
impedance of the copper traces into the
socket
Ext Vsen Filter:
Simulates any resistance and capacitance
in the feedback path. i.e. A 10ohm resistor
that is used to inject signals for Bode
measurments
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Feedback loop Soft Start
Slew rate is for information and can be
selected in another place.
During softstart the PID values can be
reduced to slower settings.
They do not need to be as fast responding
during soft start as during normal operation.
i.e. Not the same big transients to handle.
The lower settings allow a smoother
monotonic ramp of Vout
PID compensation can be optimized during
soft start.
Startup Rate
–Effective startup ramp rate
–The startup rate can be changed in the
On/Off Settings dialog
PID Coefficients
–During start up: adjust the voltage
feedback loop compensation during the
initial start up period only
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Feedback loop PID
Poles >>> PID button
Poles / Zeros can be converted to
PID Coefficients by clicking this
button
Copy <<< PID button:
copies Recommended PID
Coefficients to the PID Coefficients
Selected Phase: For information the
PID coefficients for different number
of phases can be shown for
information.
PID Coefficients: the coefficients
can be entered directly or calculated
by the GUI using the buttons.
Recommended PID Coefficients
GUI can calculate a set of
recommended coefficients
– Calculate button: displays the
calculated PID coefficients
based on the entered values in
the Model tab, Vin and Vout
Vout: Output voltage Used for
internal calculations of PID in the GUI
PID Scaling Weight Poles / Zeros
Vin Scale Enable
Enter the parameters for the desired Poles and Zeros. GUI
See next 2 slides for explanation can convert this to PID coefficients
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Vin scaled PID
› Kp, Ki, Kd can be programmed to be scaled over Vin to
– Maintain the same zeros and poles location
– Keep the same gain
Note: Kfp2, Kfp1 and Kp(avp) are unchanged over Vin
p2 p1
Kfp2 and Kfp1 are not changed over Vin
Vin
Ki
z1 z2
Vin
Kd
Vin
Kp
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PID scaling over Nph change (1 of 2)
p2 p1
Nph Gain
Kfp2
Ki is not changed
Nph Ki
Kfp1
Kfp1 Kd Kfp2
-20dB
Kp
PID compensator
z1 z2
Nph
Nph
Kd
Kp
Ensure -20dB at cross over
0dB
› Kp, Kd, Kfp2, Kfp1 and Kpavp will be
scaled automatically as the Nph is being LC filter
added or dropped. Note: Ki is not changed
› As Nph is increasing
-40dB
– Kp, Kd is decreasing
– Kfp2, Kfp1, Kpavp is increasing
› Change of Kd is proportional to Nph and
Kp, Kfp2, Kfp1 and Kpavp are proportional
to square root of Nph
› z1, z2, p2, p1 are moved to the higher
frequency when Nph is increasing because
double pole location is moved to higher
frequency fo fz1 fLC fz2 fc fp2 fesr fp1 fanti_alias
frequency
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Feedback Loop PID:
Compensator – Steady State (Voltage Loop)
PID coefficients
Gain
– PID compensator: similar to Type III
compensator Ki Kfp
• fz1: 1st zero of PID compensator Kd
-20dB
(Ki and Kp intersection)
Kp
• fz2: 2nd zero of PID compensator PID compensator
(Kp and Kd intersection)
• fo: pole at origin (Ki)
Ensure -20dB at cross over
• fp: high frequency pole (Kd and
Kfp intersection) 0dB
LC filter
• fanti_alias: high frequency anti-alias
pole @ around 10MHz for LoopA/B
• LC filter: -40dB
o fLC: output LC filter double pole
o fesr: ESR zero of Cout
fo fz1 fLC fz2 fc fp fesr fanti_alias frequency
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Feedback Loop PID: Recommendations for
Designing a Stable Voltage Feedback Loop
› The first zero should be placed on the left side of the LC filter’s double poles, and the second
zero placed on the right side of the double poles
› The cross-over frequency (fc) or bandwidth (BW) should not exceed 1/4 of the switching
frequency
› The Gain should cross the 0dB threshold with a slope of -20dB /dec
› Kp/Ki/Kd/Kfp values are larger for lower phase-count than that for higher phase-count
› PID coefficients are non-linear. Coefficient index delta of 32 is equivalent to 6dB change in
gain
› Kp(AVP) should be smaller for VR’s where a large DC load-line setting is required
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Feedback Loop PID: Steady State Voltage
Loop Compensation Kp impact on transient
Higher Kp leads to wider
Vtarget Gain split between the two zeros
Ki Kfp
Vout @ Kp = 180 Kd
Vout @ Kp = 148 -20dB Kp
PID compensator
Vout @ Kp = 116
Ensure -20dB at cross over
0dB
LC filter
-40dB
fo fz1fLC fz2 fc fp fesr fanti_alias frequency
› P term is proportional to Verr. The higher the Kp the higher the BW, but the higher the ring
back
› From the time domain transient response:
– Kp mainly affects the first ring back amplitude
– Kp has some impact on first undershoot beyond 100ns of load stepping
Note: Kp affects the transient response within the first 5us
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Feedback Loop PID: Steady State Voltage
Loop Compensation Ki impact on transient
Higher Ki moves the first zero
Gain to higher frequency
Vtarget
Ki Kfp
Vout @ Ki = 159 Kd
Vout @ Ki = 127 -20dB Kp
PID compensator
Vout @ Ki = 95
Ensure -20dB at cross over
0dB
LC filter
-40dB
fo fz1fLC fz2 fc fp fesr fanti_alias frequency
› I is the integral term used to drive the DC value of Verr to zero
› From the time domain transient response, Ki mainly affects:
– The settling trend of VOUT after the initial transient response
– If Ki is too high, VOUT overshoots Vtarget in the highlighted region
– If Ki is too low, VOUT may lag Vtarget in the highlighted region can cause extra undershoot
Note: Ki affects the transient response after the initial 10us to 40us
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Feedback Loop PID: Steady State Voltage
Loop Compensation Kd impact on transient
Higher Kd moves the second
zero to lower frequency
Vtarget Gain
Ki Kfp
Vout @ Kd = 390 Kd
-20dB Kp
Vout @ Kd = 360
PID compensator
Vout @ Kd = 328
Ensure -20dB at cross over
0dB
LC filter
-40dB
fo fz1fLC fz2 fc fp fesr fanti_alias frequency
› D is the derivative term. The higher the Kd, the higher the BW but with less phase margin
› From the time domain transient response, Kd mainly affects:
– The first undershoot beyond the 100ns of load stepping. The higher the Kd, the less the
undershoot
– But too high of Kd will cause VOUT ringing due to insufficient phase margin
Note: Kd affects the transient response within the first 5us
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Feedback Loop PID: Steady State Voltage
Loop Compensation Kfp impact on transient
Higher Kfp pushes the polefp to
Vtarget higher frequency
Gain
Ki Kfp
Vout @ Kfp = 164 Kd
-20dB Kp
Vout @ Kfp = 132
PID compensator
Vout @ Kfp = 100
Ensure -20dB at cross over
0dB
LC filter
-40dB
fo fz1fLC fz2 fc fp fesr fanti_alias frequency
› Kfp provides a high frequency pole to roll off the gain introduced by the P and D terms. If Kfp is too
high, the D term gain at high frequency will not be attenuated and hence results in less phase
margin
› From the time domain transient response, Kfp mainly affects:
– The first undershoot beyond the 100ns of load stepping. The higher the Kfp, the less the
undershoot
– But if Kfp is too high it will lead to VOUT ringing due to insufficient phase margin
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Feedback Loop PID: Steady State Voltage Loop
Compensation Kp (AVP) impact on transient
Vtarget @ Kp (AVP) = 171
Vout @ Kp (AVP) = 171
Vtarget @ Kp (AVP) = 139
Vout @ Kp (AVP) = 139
Vtarget @ Kp (AVP) = 95
Vout @ Kp (AVP) = 95
› Kp(AVP) is the low pass filter of the AVP loop.
› From the time domain transient response, Kp(AVP) mainly affects:
– how fast the target voltage can track the changing inductor current during transient
conditions
– If Kp(AVP) is too low, VOUT will take longer to settle to the final DC target
– The higher the Kp(AVP) , the higher the AVP loop BW, and it may overlap with the
voltage loop to induce extra undershoot or ringing at VOUT
Note: Kp(AVP) affects the transient response in 5us to 20us
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Feedback Loop PID:
Compensator – Steady State (Voltage Loop)
Gain
Ki Kfp
Kd
-20dB Kp
PID compensator
Ensure -20dB at cross over
0dB
LC filter
-40dB
fo fz1fLC fz2 fc fp fesr fanti_alias frequency
Poles/Zeroes
– Z1: first zero at fZ1
– Z2: Second zero at fZ2
– P_Low: pole at fp
– P_High: pole at fanti_alias
– Gain @ 1Hz: DC gain
– AVP BW: AVP bandwidth
– Poles>>>PID button: calculates and populates
the desired PID coefficients based on Poles and
Zeros information entered
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