IITBBS Digital System Design and Synthesis MOSart Labs
Date: August 19, 2025
Assignment-2
1. Consider an 8-bit ripple-carry adder built using eight full-adders. Each full adder is built using a two-
level sum-of-products circuit for the carry-out and a 3-input XOR gate for the sum. In this adder
assume that the delay through a gate is:
Gate delay = 1 + 0.1 ×(#Inputs-1) ns,
where # Inputs is the number of inputs to the gate.
Using this equation, the delay through an inverter is equal to 1 ns, the delay through a 2-input gate
(any type) is 1.1 ns, and so on.
(a) What is the critical path delay in the ripple-carry adder? (Recall: the critical path is the longest
(slowest) path in the circuit.) Give your answer in ns.
(b) Consider next a carry lookahead adder, as discussed in class. If you can use gates of any size
(number of inputs), what is the critical path delay in the 8-bit carry lookahead adder?
(c) Now assume that you can use gates with a fanin of no more than four inputs. What is the critical
path delay for the carry lookahead adder in this case?
2. Design a four-bit combinational 2’s complementer circuit. (The output generates the 2’s complement of
the input binary number.) Show that the circuit can be constructed with exclusive-OR gates. Can you
predict what the output functions are for a five-bit 2’s complementer?
3. Design a combinational circuit whose input A is a vector of 7-bits and its output Z is a 3-bit vector
which counts the number of “1”s present in the input. For instance, A = 1001001 or A = 1010100 both
will results in Z = 011, indicating that both input vectors have three numbers of “1”s. Please note that
you have to use only full-adders while building this circuit.
4. In computer arithmetic, it is often necessary to perform comparisons. The logic diagram shown
in Figure 1 is a four-bit adder/subtractor circuit that can be used for comparison by performing A − B,
where A = A3 A2 A1 A0 and B = B3 B2 B1 B0 . The three outputs of the circuit denote the following:
• Z = 1 if the result is 0; otherwise Z = 0
• N = 1 if the result is negative; otherwise N = 0
• V = 1 if arithmetic overflow occurs; otherwise V = 0
Show how Z, N , and V can be used to determine the cases A = B, A < B, A ≤ B, A > B, and A ≥ B.
5. The following circuit shown in Figure 2 will compare two binary numbers A and B each has two bits
(A1 A0 ) and (B1 B0 ) then will output 1 if the two numbers are equal, and zero otherwise. Design the
circuit using an 8-to-1 multiplexer.
6. Design a circuit that takes in a BCD digit and produces a two digit BCD number. This two digit
number is nothing but input BCD digit multiplied by 5.
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SD6L101 Digital System Design and Synthesis Page 2 of 3
N
Z
Figure 1: Four-bit adder/subtractor for performing the comparison.
A1
A0
Equal Y
B1
B0
Figure 2: Two-bit equality comparator
7. Complete the following table.
Representation
Decimal Signed Magnitude 1’s complement 2’s complement
1110
1111
100
01110
Table 1: Number conversions
8. Sketch the circuit that computes |A − B|, where A, B are 4-bit unsigned numbers. For example, A =
0101, B = 1101 → |A − B| = |5 − 13| = 8. You can only use full adders (or multi-bit adders) and
logic gates. Your circuit must avoid overflow: design your circuit so that the result and intermediate
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SD6L101 Digital System Design and Synthesis Page 3 of 3
operations have the proper number of bits.
9. Design a multiplier circuit that takes in one BCD digit and multiplies it with 5 to produce a two digit
BCD number. Your circuit should use minimum number of logic gates.
10. Using a 2 × 1 multiplexer, build NOT, AND, OR, D-latch, and D-FlipFlop.
11. Design/sketch your idea for a 4-bit magnitude comparator that works for both signed and unsigned
numbers. You circuit should use minimum number of logic gates.
12. Using only 2:1 mux structures, design a block that compares two 8-bit values (unsigned, simple 0-255
values) – A,B. if A>B then the output is 1 else 0. Try to use minimum number of muxes
End of Assignment
