Specification Document for Packet Encoder
RTL Design
1. Overview
The purpose of this document is to outline the specifications for an RTL (Register Transfer
Level) design of a packet encoder. The encoder will generate packets that consist of three key
components:
Header: Contains metadata about the packet.
Payload: Contains the actual data to be transmitted.
CRC/Parity: Ensures data integrity.
The encoder will assemble these components into a single, properly formatted packet for
transmission.
2. Packet Structure
Each packet generated by the encoder will have the following structure:
Field Size Description
Header 2 Bytes Contains the destination address and number of payload bytes.
Payload Variable Contains the actual data to be transmitted.
CRC/Parity 1 Byte Contains error-checking information for data integrity.
2.1 Header Structure
Sub-field Size Description
Destination Address 1 Byte Identifies the target recipient. (AA,BB,CC,DD)
Payload Byte Count 1 Byte Specifies the number of bytes in the payload.
2.2 Payload
The payload will carry the actual data. Its size is variable and specified in the header.
2.3 CRC/Parity
A CRC or parity field will be appended to the packet for error detection. The method and size
are configurable (8-bit CRC).
3. Functional Requirements
3.1 Input Ports
Signal Name Width Description
clk 1 Clock signal for synchronous operation.
reset_n 1 Active-low reset signal.
payload_data_in 8 Input data for the payload.
Indicates when payload data is valid. It should be high
as long as the payload_data_in is being sent in.
ip_valid 1
Also, First clock of the ip_valid indicates
payload_size as well as destination_addr.
destination_addr 8 Destination address for the packet.
payload_size 8 Size of the payload in bytes.
3.2 Output Ports
Signal Name Width Description
packet_out 8 Assembled packet output.
Packet_valid Indicates when a valid
1
packet is ready.
4. Block Diagram
5. Functional Description
1. Packet Assembly:
o The encoder receives the payload_data_in, destination_addr,
and payload_size as inputs.
o The header is created using destination_addr and payload_size.
o The payload is appended to the header.
o A CRC or parity field is calculated based on the header and payload and
appended to the end of the packet.
2. Error Checking:
o The encoder uses a 8bit CRC or parity generator for error checking.
3. Output:
o When the packet is fully assembled, it is output on packet_out,
and packet_valid is asserted.
6. Configuration Parameters
Parameter Name Description Default Value
ADDR_WIDTH Width of the destination address field in bits. 8 bits
PAYLOAD_MAX_SIZE Maximum size of the payload in bytes. 256 bytes
CRC_WIDTH Width of the CRC field in bits. 8 bits
HEADER_WIDTH Width of the header in bits. 8 bits
7. Timing Requirements
The encoder will operate on the rising edge of clk.
All inputs must be valid at least one clock cycle before being processed.
The packet_valid signal will remain asserted throughout when a valid packet is
ready.
8. Reset Behavior
On assertion of reset_n (active-low reset), all internal states and outputs will be
cleared.
No packets will be output until the reset is deasserted and valid input data is provided.
