Simulation Report for 4-Stage Pipelined Processor Design
in Verilog
Name: Md. Sameer Ahmed
Internship Domain: VLSI
Task: Design a 4-stage pipelined processor with basic instructions: ADD, SUB, AND, LOAD
Objective
To design and simulate a simple 4-stage pipelined processor using Verilog HDL, supporting basic
instructions such as ADD, SUB, AND, and LOAD. The processor is implemented with
instruction fetch, decode, execute, and memory/write-back stages.
Tools Used
- Language: Verilog HDL
- Simulator: Icarus Verilog
- Waveform Viewer: GTKWave
Processor Architecture
The processor design follows a 4-stage pipeline:
1. Instruction Fetch (IF): Fetch instruction from instruction memory.
2. Instruction Decode (ID): Decode instruction and read operands from registers.
3. Execute (EX): Perform ALU operations or memory address calculation.
4. Memory/Write-Back (MEM/WB): Read data from memory or write result back to register.
Pipelined Processor Verilog Code (with Comments)
module PipelinedProcessor (
input clk, // Clock signal
input reset // Reset signal
);
reg [15:0] instr_mem [0:15]; // Instruction memory
reg [7:0] data_mem [0:15]; // Data memory
reg [7:0] regfile [0:7]; // 8 registers (R0-R7)
// Pipeline registers
reg [15:0] IF_ID;
reg [15:0] ID_EX;
reg [7:0] EX_MEM_result;
reg [2:0] EX_MEM_rd;
reg EX_MEM_mem_read;
reg EX_MEM_reg_write;
reg [7:0] MEM_WB_result;
reg [2:0] MEM_WB_rd;
reg MEM_WB_reg_write;
reg [3:0] PC;
// Instruction fields
wire [3:0] opcode = IF_ID[15:12];
wire [2:0] rd = IF_ID[11:9];
wire [2:0] rs1 = IF_ID[8:6];
wire [2:0] rs2 = IF_ID[5:3];
// IF Stage
always @(posedge clk or posedge reset) begin
if (reset) begin
PC <= 0;
IF_ID <= 0;
end else begin
IF_ID <= instr_mem[PC];
PC <= PC + 1;
end
end
// ID Stage
reg [7:0] reg_rs1, reg_rs2;
always @(posedge clk) begin
reg_rs1 <= regfile[rs1];
reg_rs2 <= regfile[rs2];
ID_EX <= IF_ID;
end
// EX Stage
reg [7:0] alu_result;
always @(posedge clk) begin
case (ID_EX[15:12])
4'b0001: alu_result <= reg_rs1 + reg_rs2; // ADD
4'b0010: alu_result <= reg_rs1 - reg_rs2; // SUB
4'b0011: alu_result <= reg_rs1 & reg_rs2; // AND
4'b0100: alu_result <= data_mem[reg_rs1]; // LOAD
default: alu_result <= 8'b00000000;
endcase
EX_MEM_result <= alu_result;
EX_MEM_rd <= ID_EX[11:9];
EX_MEM_mem_read <= (ID_EX[15:12] == 4'b0100);
EX_MEM_reg_write <= 1;
end
// MEM/WB Stage
always @(posedge clk) begin
if (EX_MEM_mem_read)
MEM_WB_result <= EX_MEM_result;
else
MEM_WB_result <= EX_MEM_result;
MEM_WB_rd <= EX_MEM_rd;
MEM_WB_reg_write <= EX_MEM_reg_write;
end
// Write Back Stage
always @(posedge clk) begin
if (MEM_WB_reg_write)
regfile[MEM_WB_rd] <= MEM_WB_result;
end
endmodule
Testbench Verilog Code (with Comments)
module tb_PipelinedProcessor;
reg clk;
reg reset;
// Instantiate processor
PipelinedProcessor uut (
.clk(clk),
.reset(reset)
);
// Clock generation
always #5 clk = ~clk;
// Load instructions and data
initial begin
clk = 0; reset = 1;
#10 reset = 0;
// Instruction Memory Initialization
uut.instr_mem[0] = 16'b0001_001_010_011_000; // ADD R1 = R2 + R3
uut.instr_mem[1] = 16'b0010_100_101_110_000; // SUB R4 = R5 - R6
uut.instr_mem[2] = 16'b0011_000_001_010_000; // AND R0 = R1 & R2
uut.instr_mem[3] = 16'b0100_011_100_000_000; // LOAD R3 = MEM[R4]
// Register Initialization
uut.regfile[2] = 8'd10;
uut.regfile[3] = 8'd5;
uut.regfile[5] = 8'd20;
uut.regfile[6] = 8'd7;
uut.regfile[4] = 4; // For LOAD base address
// Data Memory Initialization
uut.data_mem[4] = 8'd99;
#100 $finish;
end
endmodule
Simulation Output (Expected)
Cycle by cycle, the instructions move through the pipeline stages. Expected outputs:
- ADD: R1 = 10 + 5 = 15
- SUB: R4 = 20 - 7 = 13
- AND: R0 = R1 & R2 = 15 & 10 = 10
- LOAD: R3 = MEM[R4] = 99
Conclusion
The 4-stage pipelined processor was successfully implemented using Verilog. It supports ADD,
SUB, AND, and LOAD instructions and simulates correct data flow through IF, ID, EX, and
MEM/WB stages.
