AN1258

Op Amp Precision Design: PCB Layout Techniques

Author: Kumen Blake THERMOCOUPLE JUNCTION

Microchip Technology Inc. BEHAVIOR
While thermocouples are a common temperature
INTRODUCTION sensor [5], it is not commonly known that every PCB
design includes many unintended thermocouple
This application note covers Printed Circuit Board junctions that modify the signal voltages. This section
(PCB) effects encountered in high (DC) precision op covers the physics behind this effect and gives
amp circuits. It provides techniques for improving the practical illustrations.
performance, giving more flexibility in solving a given
design problem. It demonstrates one important factor
necessary to convert a good schematic into a working
Seebeck Effect
precision design. When two dissimilar conductors (or semiconductors)
This material is for engineers who design slow are joined together, and their junction is heated, a
precision circuits, including those with op amps. It is voltage results between them (Seebeck or
aimed at those engineers with little experience in this thermoelectric voltage); this is known as the Seebeck
kind of design, but can also help experienced effect. This voltage is roughly proportional to absolute
engineers that are looking for alternate solutions to a temperature. There are many references that discuss
design problem. this effect in detail, including the “Temperature
Products” section of reference [8]; see especially
The information in this application note can be applied
pages Z-13, Z-14 and Z-23 through Z-32.
to all precision (DC) analog designs, with some thought
and diligence. The focus is on common op amp circuits Figure 1 shows the Seebeck voltage as a function of
so that the reader can quickly convert this material into temperature for the standard type K thermocouple.
improvements in their own op amp designs. Notice that the response is not strictly linear, but can be
linearized over small temperature ranges (e.g., ±10°C).
Additional material at the end of the application note
includes references to the literature and the schematic
of a PCB used in the design example. 60
55 ITS-90
ocouple Voltage (mV)

50 Type K Thermocouple
45
Key Words and Phrases 40
35
• Op Amp 30
25
• Temperature 20
15
• Thermal Gradient 10
Thermo

5
• Thermocouple Junction 0
-5
• Thermoelectric Voltage -10
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400

• IC Sockets
• Contact Potential Thermocouple Temperature (°C)

• PCB Surface Contamination

FIGURE 1: Type K Thermocouple’s
Response.
Related Application Notes
Most thermocouple junctions behave in a similar
The following application notes, together with this one, manner. The following are examples of thermocouple
form a series about precision op amp design topics. junctions on a PCB:
They cover both theory and practical methods to
improve a design’s performance. • Components soldered to a copper pad
• Wires mechanically attached to the PCB
• AN1177 on DC Errors [2]
• Jumpers
• AN1228 on Random Noise [3]
• Solder joints
• PCB vias

 2009-2012 Microchip Technology Inc. DS01258B-page 1

AN1258
The linearized relationship between temperature and TABLE 1: ASSUMED THERMOCOUPLE
thermoelectric voltage, for small temperature ranges, is JUNCTION PARAMETERS
given in Equation 1. The Seebeck coefficients for the
junctions found on PCBs are typically, but not always, VREF kJ
Junction No.
below ±100 µV/°C. (mV) (µV/°C)
1 10 40
EQUATION 1: SEEBECK VOLTAGE 2 -4 -10
VTH  k J  T J – T REF  3 4 10
VTH = V REF + V TH 4 -10 -40
Where: Note 1: VREF and kJ have polarities that assume a left-
to-right horizontal direction.
VTH = Change in Seebeck voltage (V) 2: TREF = 25 °C.
kJ = Seebeck coefficient (V/°C)
TJ = Junction Temperature (°C) CONSTANT TEMPERATURE
TREF = Reference Temperature (°C) In this illustration, temperature is constant across the
PCB. This means that the junctions are at the same
VTH = Seebeck voltage (V)
temperature. Let’s also assume that this temperature is
VREF = Seebeck voltage at TREF (V) +125°C and that the voltage on the left trace is 0V. The
results are shown in Figure 3. Notice that VTH is the
voltage change from one conductor to the next.
Illustrations Using a Resistor
Three different temperature profiles will be shown that 14 mV 9 mV 14 mV
illustrate how thermocouple junctions behave on PCB
0 mV 0 mV
designs. Obviously, many other components will also
produce thermoelectric voltages (e.g., PCB edge
connectors).
Figure 2 shows a surface mount resistor with two metal
(copper) traces on a PCB. The resistor is built with end
caps for soldering to the PCB and a very thin
conducting film that produces the desired resistance.
Thus, there are three conductor types shown in this +125.00°C +125.00°C
figure, with four junctions. +125.00°C +125.00°C

VREF VTH VTH

Location
Resistor Copper Resistor (mV) (mV) (mV)
Film Traces End Caps
Junction #1 10 4 14
Junction #2 -4 -1 -5
Junction #3 4 1 5
Junction #4 -10 -4 -14

FIGURE 3: Constant Temperature

Results.

TEMPERATURE CHANGE IN THE NORMAL

Junction #1 Junction #4 DIRECTION
Junction #2 Junction #3
In this illustration, temperature changes vertically in
FIGURE 2: Resistor and Metal Traces Figure 2 (normal to the resistor’s axial direction), but
on PCB. does not change in the axial direction (horizontally).
The metal areas maintain almost constant voltages in
For illustrative purposes, we’ll use the arbitrary values
the normal direction, so this case is basically the same
shown in Table 1. Notice that junctions 1 and 4 are the
as the previous one.
same, but the values are shown with opposite
polarities; this is one way to account for the direction Note: When temperature is constant along the
current flows through these junctions (the same applies direction of current flow, the net change in
to junctions 2 and 3). thermoelectric voltage between two
conductors of the same material is zero.

DS01258B-page 2  2009-2012 Microchip Technology Inc.

 AN1258
TEMPERATURE CHANGE IN THE AXIAL PREVENTING LARGE
DIRECTION THERMOELECTRIC VOLTAGES
In this illustration, temperature changes horizontally in
This section includes several general techniques that
Figure 2 (along the resistor’s axial direction), but does
prevent the appearance of large temperature gradients
not change in the normal direction (vertically). Let’s
at critical components.
assume 0V on the left copper trace, +125°C at
Junction #1, a temperature gradient of 10°C/in
(0.394°C/mm) from left to right (0 in the vertical Reduced Heat Generation
direction) and a 1206 SMD resistor. When a PCB’s thermal gradient is mainly caused by
The resistor is 0.12 inches long (3.05 mm) and components attached to it, then find components that
0.06 inches wide (1.52 mm). Assume the end caps are dissipate less power. This can be easy to do (e.g.,
about 0.01 inches long (0.25 mm) and the metal film is change resistors) or hard (change a PICmicro®
about 0.10 inches long (2.54 mm). The results are microcontroller).
shown in Figure 4. Increasing the load resistance, and other resistor
values, also reduces the dissipated power. Choose
8.999 mV lower power supply voltages, where possible, to further
reduce the dissipated power.
14.000 mV 14.010 mV
0 mV -0.038 mV Redirect the Heat Flow
Changing the direction that heat flows on a PCB, or in
its immediate environment, can significantly reduce
temperature gradients. The goal is to create nearly
constant temperatures in critical areas.

ALTERNATE HEAT PATHS

+125.0°C +126.1°C
+125.1°C +126.2°C Adding heat sinks to parts that dissipate a lot of power
will redirect the heat to the surrounding air. One form of
VREF VTH VTH heat sink that is often overlooked is either ground
Location
(mV) (mV) (mV) planes or power planes in the PCB; they have the
advantage of making temperature gradients on a PCB
Junction #1 10 4.000 14.000
lower because of their large (horizontal) thermal
Junction #2 -4 -1.001 -5.001 conductivity.
Junction #3 4 1.011 5.011 Adding a fan to a design will also redirect heat to the
Junction #4 -10 -4.048 -14.048 surrounding air, which reduces the temperature drop
on the PCB. This approach, however, is usually
FIGURE 4: Axial Gradient Results. avoided to minimize other design issues (random
temperature fluctuations, acoustic noise, power, cost,
Thus, the temperature gradient of 10°C/in (1.2°C
etc.). It is important to minimize air (convection)
increase from left to right) caused a total of -38 µV to
currents near critical components. Enclose either the
appear across this resistor. Notice that adding the
parts with significant temperature rise, or the critical
same temperature change to all junction temperatures
parts. Conformal coating may also help.
will not change this result.
Note: Shifting all of the junction temperatures by ISOLATION FROM HEAT GENERATORS
the same amount does not change the It is possible to thermally isolate critical areas on the
temperature gradient. This means that the PCB. Regions with little or no metal act like a good
voltage drop between any two points in the thermal insulator. Signals that need to cross these
circuit using the same conductive material regions can be sent through series resistors, which will
is the same (assuming we’re within the also act as poorly conducting thermal elements.
linear region of response).
Place heat sources as far away from critical points as
possible. Since many heat sources are in the external
environment, it can be important to place these critical
points far away from the edges of the PCB.
Components that dissipate a lot of power should be
kept far away from critical areas of the PCB.

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AN1258
Low profile components will have reduced exposure to CURING THERMOELECTRIC
the external environment. They may have the
VOLTAGE EFFECTS
additional advantage of reduced electrical crosstalk.
Thermal barriers, such and conformal coating and PCB This section focuses on methods that minimize the
enclosures, can be helpful too. They usually do not effects of a given temperature gradient. They can be
have to be added unless there are other compelling powerful aids in improving a design because they tend
reasons to do so. to be low cost.

Slow Temperature Changes Metallurgy

In some applications, sudden changes in Critical points, that need to have the same total
thermoelectric voltages can also be a concern. thermoelectric voltage, should use the same
conductive material. For example, the inputs to an op
Avoid power-up and power-down thermal transient amp should connect to the same materials. The PCB
problems by minimizing the currents drawn during traces will match well, but components with different
these times. Also, reducing the times can help. constructions may be a source of trouble.
Quick changes in voltages at heavy loads can be It is possible to find combinations of metals and solders
another source of concern. If the load cannot be made that have low Seebeck coefficients. While this
lighter, then isolation is usually the best approach to obviously reduces voltage errors, this can be
solving this problem. complicated and expensive to implement in
manufacturing.

Following Contour Lines

Place critical components so that their current flow
follows constant temperature contour lines; this
minimizes their thermoelectric voltages. Figure 5
shows an inverting amplifier that will be used to
illustrate this concept; RN, RG and RF are the critical
components in this circuit.

RG RF
VIN VOUT
VDD
RN
C1
U1

FIGURE 5: Inverting Amplifier.

Figure 6 shows one implementation of this concept.
Constant temperature contour lines become
reasonably straight when they are far from the heat
source. Placing the resistors in parallel with these lines
minimizes the temperature drop across them.

Constant
Heat Source Temperature
Contour
Lines

VIN RF U1 VDD
RG
RN C1
VOUT

FIGURE 6: Resistors Aligned with

Contour Lines.

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 AN1258
The main drawback to this technique is that the contour The output has a simple relationship to the inputs (VIN
lines change when the external thermal environment and the three VTHx and VTHy sources):
changes. For instance, picking up a PCB with your
hands adds heat to the PCB, usually at locations not EQUATION 2:
accounted for in the design.
G N = 1 + RF  R G
Cancellation of Thermoelectric Voltages VOUT =  V IN + V THx G N – V THx  G N – 1  + V THy
= V IN G N + V THx + VTHy
It is possible to cancel thermoelectric voltages when
the temperature gradient is constant. Several
examples will be given to make this technique easy to When the gain (GN) is high, the thermoelectric voltage
understand. contributes little to the output error. This layout may be
good enough in that case. Notice that the cancellation
TRADITIONAL OP AMP LAYOUT APPROACH between RN and RG is critical to good performance.
Figure 7 shows a non-inverting amplifier that needs to When the gain is low, or the very best performance is
have the resistors’ thermoelectric voltage effect desired, this layout needs improvement. The following
minimized. The traditional approach is to lay out the sections give guidance that helps achieve this goal.
input resistors (RN and RG) close together, at equal
distances from the op amp input pins and in parallel. SINGLE RESISTOR SUBSTITUTIONS
A single resistor on a PCB will produce a thermoelectric
U1 voltage, as discussed before. Replacing that resistor
VDD with two resistors that are properly aligned will cancel
VIN
RN C1 the two resulting thermoelectric voltages.
Figure 9 shows the original resistor and its model on
VOUT the top, and a two series resistor substitution and its
RG RF model on the bottom.
The original resistor has a thermally induced voltage
FIGURE 7: Non-inverting Amplifier.
VTHx that is based on the temperature gradient in the
Figure 8 shows one layout that follows the traditional x-direction (horizontal).
approach, together with a circuit diagram that includes
The two resistors on the bottom have thermally induced
the resulting thermoelectric voltages (VTHx and VTHy). voltages VTHy that are based on the temperature
VTHx is positive on the right side of a horizontally
gradient in the y-direction (vertical); they are equal
oriented component (e.g., RN). VTHy is positive on the
because the temperature gradient is constant and the
top side of a vertically oriented component (e.g., RF). resistor lengths are equal. Due to their parallel align-
ment, these voltages cancel; the net thermally induced
RF VDD voltage for this combination (as laid out) is zero.
U1
RG
RN C1 VTHx
VIN R1 R1
VOUT
C1
VDD
VIN U1 VTHy VTHy
RN VTHx R1A R1B
R1A R1B
VOUT
RG V RF V
THx THy
Where:
FIGURE 8: One Possible Layout (not R1A = R1B = R1/2
recommended) and its Thermoelectric Voltage
FIGURE 9: Series Resistor Substitution.
Model.
Note: The orientation of these two resistors (R1A
and R1B) is critical to canceling the
thermoelectric voltages.

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AN1258
Figure 10 shows the original resistor and its model on
the top, and a two parallel resistor substitution and its
RF U1 VDD
model on the bottom.
RG
The original resistor has a thermally induced voltage RN C1
VTHx that is based on the temperature gradient in the VIN
VOUT
x-direction (horizontal).
The two resistors on the bottom have thermally induced C1
voltages VTHy that are based on the temperature gradi- VDD
VIN U1
ent in the y-direction (vertical); they are equal because
the temperature gradient is constant and the resistor RN VTHx
lengths are equal. Due to their orientation, and
VOUT
because R1A = R1B, these voltages produce currents
RG V RF V
that cancel. The net thermally induced voltage for this THx THx
combination (as laid out) is zero.
FIGURE 12: First Layout (not recom-
mended) and its Thermoelectric Voltage Model.
R1 VTHx
R1 The output has a simple relationship to the inputs (VIN
and the three VTHx sources):

R1A EQUATION 3:
VTHy R1B
G N = 1 + RF  R G
R1A VTHy VOUT =  V IN + V THx G N – V THx  G N – 1  + V THx
R1B = V IN G N + 2V THx

Where:
R1A = R1B = 2R1 When the gain (GN) is high, the thermoelectric
voltage’s contribution to the output error is relatively
FIGURE 10: Parallel Resistor small. This layout may be good enough in that case.
Substitution. Notice that the cancellation between RN and RG is
critical.
NON-INVERTING AMPLIFIER We have a better layout shown in Figure 13.
Figure 11 shows a non-inverting amplifier. We will start Recognizing that subtracting the last term in the VOUT
with the layout in Figure 12 (previously shown in equation (middle equation in Equation 3) completely
Figure 6). The resistor RF is horizontal so that all of the cancels the thermoelectric voltages, the resistor RF
thermoelectric voltages may be (hopefully) cancelled. was oriented in the reverse direction.
The model shows how the thermoelectric voltages
modify the circuit. VDD
RF U1
RG
U1 RN C1
VDD VIN
VIN
C1 VOUT
RN
C1
VOUT VDD
RG RF VIN U1
RN VTHx
FIGURE 11: Non-inverting Amplifier.
VOUT
RG V RF V
THx THx

FIGURE 13: Second Layout and its

Thermoelectric Voltage Model.

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 AN1258
With the reversed direction for RF, the output voltage is
now: RF VDD
– U1
RG
VIN
EQUATION 4: RG C1
+
RF
GN = 1 + RF  RG
VREF VOUT
V OUT =  VIN + VTHx G N – VTHx  G N – 1  – VTHx
VTHx VTHx
= VIN G N RG RF
VREF
The cancellation between RN and RG is critical to this C1
layout; the change to RF’s position is not as important. + VDD
VIN U1
INVERTING AMPLIFIER –
Inverting amplifiers use the same components as non-
VOUT
inverting amplifiers, so the resistor layout is the same;
see Figure 14. RG V RF V
THx THx

FIGURE 16: Difference Amplifier Layout

RF U1 VDD
VIN and its Thermoelectric Voltage Model.
RG
RN The output has a simple relationship to the inputs (VIN,
C1
VREF and the four VTHx sources):
VOUT
RG RF EQUATION 5:
VIN VOUT G = RF  R G
VDD
RN VOUT =  V IN + V THx – V THx G
C1
U1 +  V REF + V THx – VTHx 
= V IN G + V REF
FIGURE 14: Inverting Amplifier.

DIFFERENCE AMPLIFIER INSTRUMENTATION AMPLIFIER INPUT

STAGE
Figure 15 shows a difference amplifier. This topology
has an inherent symmetry between the non-inverting Figure 17 shows an instrumentation amplifier input
and inverting signal paths, which lends itself to stage, which is sometimes used to drive the input of a
cancelling the thermoelectric voltages. Figure 16 differential ADC. While this is a symmetrical circuit,
shows the layout and its model. achieving good thermoelectric voltage cancellation on
the PCB presents difficulties. It is best to use a dual op
amp, so the RF resistors have to be on both sides of the
RG RF op amp, while RG connects both sides; the distances
VREF between resistors are too large to be practical (thermal
+ U1 gradient is not constant).
VDD
VIN C1
– U1A
VDD
VOUT
RN C1
RG RF

FIGURE 15: Difference Amplifier. + +

RF
VIN RG VOUT
RF
– –

RN

U1B

FIGURE 17: Instrumentation Amplifier

Input Stage (not recommended).

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AN1258
The solution to this problem is very simple; split RG into The VTHx sources cancel, for the reasons already
two equal series resistors so that we can use the given, so the differential output voltage is simply:
non-inverting layout (see Figure 13) on both sides of
the dual op amp. Each side of this amplifier will cancel EQUATION 6:
its thermoelectric voltages independently; this is shown
in Figure 18 and Figure 19. G = 1 + 2R F  R G
VOUT = V IN G
U1A
VDD
MODIFICATIONS FOR NON-CONSTANT
RN C1 TEMPERATURE GRADIENTS
Temperature gradients are never exactly constant. One
+ RG/2 RF + cause is the wide range of thermal conductivities (e.g.,
VIN VOUT traces vs. FR4) on a PCB, which causes complex tem-
RG/2 RF perature profiles. Another cause is that many heat
– –
sources act like point sources, and the heat is mainly
conducted by a two dimensional object (the PCB); the
RN temperature changes rapidly near the source and
slower far away.
U1B
Non-constant temperature gradients will cause the
FIGURE 18: Instrumentation Amplifier temperature profile to have significant curvature, which
Input Stage. causes all of the previous techniques to have less than
perfect success. Usually, the curvature is small enough
so that those techniques are still worth using. Some-
C1 times, additional measures are needed to overcome
RF U1 the problems caused by the curvature.
RF
RG/2 One method is to minimize the size of critical compo-
RG/2
RN nents (e.g., resistors). If we assume that temperature
RN
has a quadratic shape, then using components that are
VDD
VOUT+

VOUT–

VIN+
VIN–

half as long should reduce the non-linearity error to

about one quarter the size.
Another method is to keep all heat sources and sinks
C1 far away from the critical components. This makes the
VDD contour lines straighter.
U1A
The contour lines can be deliberately changed in
RN VTHx
shape. Using a ground plane (also power planes) to
conduct heat away from the sources helps equalize the
+ RG/2 V RF V + temperatures, which reduces the non-linear errors.
VIN THx THx
VOUT Adding guard traces or thermal heat sinks that
surround the critical components also help equalize the
– RG/2 VTHx RF VTHx –
temperatures.
We can modify the sizes of the critical components so
RN VTHx that the cancellation becomes closer to exact. In order
U1B to match resistors, for instance, we need to make sure
that the temperature change across each of the
FIGURE 19: Instrumentation Amplifier matched resistors is equal; see Figure 20 for an illus-
Input Stage Layout and its Thermoelectric tration.
Voltage Model.

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 AN1258
MEASUREMENT OF TEMPERATURE
(T = +1.0°C) RELATED QUANTITIES
+25.0°C +26.0°C
While the techniques previously shown are a great help
in producing an initial PCB layout, it is important to
verify that your design functions as specified. This
section includes methods for measuring the response
of individual components and of a PCB. With this
information, it is possible to make intelligent design
tweaks.

TEMPERATURE
There are many ways to measure temperature [4, 5, 6].
We could use thermocouples, RTDs, thermistors,
diodes, ICs or thermal imagers (infrared cameras) to
measure the temperature.
Figure 21 shows a circuit based on the MCP9700 IC
+25.1°C +26.1°C +26.3°C temperature sensor. Because all of the components
(T = +1.0°C) draw very little current, their effect on PCB temperature
will be minimal. There is enough filtering and gain to
FIGURE 20: Example of Mismatching the make VOUT easy to interpret. This circuit can be built on
Component Sizes. a very small board of its own, which can be easily
placed on top of the PCB of interest.

VDD = 5.0V

U1 100 nF
C1 MCP9700
1.0 µF
Temp.
Sensor TPCB
R1
100 kΩ
VDD C4
100 nF
VDD
U2
R2 MCP6041
113 kΩ
VOUT
R3 R4 R5 R6
12.4 kΩ 100 kΩ 1.00 MΩ 1.00 kΩ
C2
1.0 µF C3
22 nF

FIGURE 21: IC Temperature Sensor

Circuit.
The MCP9700 outputs a voltage of about 500 mV plus
10.0 mV/°C times the board temperature (TPCB, in °C).
The amplifier provides a gain of 10 V/V centered on
500 mV (when VDD = 5.0V), giving:

EQUATION 7:
VOUT =  500 mV  + T PCB  100 mV/C 

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AN1258
Since the MCP9700 outputs a voltage proportional to
temperature, VOUT needs to be sampled by an ADC VDD
RF 10 Ohm
that uses an absolute voltage reference. U1
RG +
The absolute accuracy of this circuit does not support VDD/2 VX
our application, so it is important to calibrate the errors. RG C1 –
Leave the PCB in a powered-off state (except for the RF
temperature sensor) for several minutes. Measure VREF VOUT 1W
VOUT at each point, with adequate averaging. The
VTHx VTHx
changes in VOUT from the calibration value represents RG RF
the change in TPCB from the no power condition. VREF
VDD C1
THERMAL GRADIENTS
To measure thermal gradients, simply measure the VDD/2 U1
temperature at several points on the PCB. The gradient
is then the change in temperature divided by the
distance between points. More points give better VOUT
resolution on the gradient, but reduce the accuracy of RG V RF V
THx THx
the numerical derivative.
FIGURE 22: Difference Amplifier with
PACKAGE THERMAL RESISTANCE Deliberately Unbalanced Thermoelectric
The way to estimate the temperature (T in °C) of a com- Voltages and Heat Generating Resistor.
ponent is to multiply its dissipated power (P in W) by the
package thermal resistance (JA in °C/W). This helps We can also place a short across one component, of a
establish temperature maximum points. matched pair, with a copper trace on the PCB.
Figure 23 shows a non-inverting amplifier layout that
To measure JA, when it is not given in a data sheet, shorts RN (with a copper trace) to unbalance the
place the temperature sensor at the IC (usually, a thermoelectric voltages. It also connects the two inputs
thermocouple between the package and the PCB). together, and uses larger resistors, to simplify
Insert a small resistor in the supply to measure the measurements (VOUT = VDD/2, ideally). The short is
supply current when on (IDD in A). Measure the change easily removed from the PCB.
in temperature (T in °C) between the off and on
conditions, supply voltage (VDD in V) and IDD. Then,
RF VDD 10 Ohm
EQUATION 8: U1 +
RG
VDD/2 VX
T (RN) C1 –
 JA = --------------------
V DD I DD
VOUT 1W
VDD C1
THERMOELECTRIC VOLTAGES VTHx
RN
The easiest way to measure thermoelectric voltages is U1
to thermally imbalance a difference amplifier circuit.
The thermoelectric voltages have a polarity that adds VDD/2
(instead of cancelling) in Figure 22 (compare to VOUT
Figure 16). The differential input voltage is zero, and RG V RF V
THx THx
the resistors are larger to emphasize the thermoelectric
voltages. FIGURE 23: Shorted Resistor (RN) that
The large resistor on the right of the layout can be used Unbalances Thermoelectric Voltages.
to generate heat, causing a horizontal temperature
With the unbalance, we now have the thermoelectric
gradient at the resistors RG and RF. The gain (G) is set
voltage:
high to make the measurements more accurate. The
thermoelectric voltage (VTHx) across one resistor is:
EQUATION 10:
EQUATION 9: G N = 1 + RF  R G
G = RF  RG VOUT – VDD  2
V THx = -------------------------------------
VOUT – VREF –GN
V THx = ---------------------------------
2G + 2

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 AN1258
TROUBLESHOOTING TIPS AND TRICKS LEAKAGE CURRENTS
Using a strip chart to track the change in critical DC Leakage currents cause voltage drops when they flow
voltages over time helps locate the physical source of through either resistors or parasitic resistances. This
the errors. Not only can it show how large the change section focuses on parasitic resistances presented by
is between two different thermal conditions (e.g., on the PCB: surface resistance and bulk (through the
and off), but it shows the time constants of these shifts. dielectric) resistance.
They can be roughly divided into the following three
categories: Leakage currents cause voltage ramps when they flow
into a capacitor. Common examples are the gain
• Time constant << 1 s, within component (e.g., capacitor of a transimpedance amplifier (see
thermal crosstalk within an op amp) Figure 32) and the non-inverting input of an op amp
• Time constant  1 s, single component (e.g., in with no DC path to ground (not recommended).
an eight lead SOIC package)
Op amp leakage (bias) currents are discussed in [2].
• Time constant >> 1 s, PCB and its environment
To quickly and easily change the temperature at one High Impedance Sources
location on a PCB, do the following. Use a clean
drinking straw to blow air at the location (component) of High impedance signal sources are susceptible to
interest. Use a piece of paper to re-direct the airflow errors caused by leakage currents. These sources are
away from other nearby components. When usually modeled as a current source with a high parallel
troubleshooting, the paper can be used to divide a PCB resistance (a Norton model):
area in half to help locate the problem component. This
approach does not give exact numbers, but can be VIN
used to quickly find problem components on a PCB.
You can use a heat sink (with electrically insulating heat IS RS
sink compound) to reduce the temperature difference
between two critical points on your PCB. The greater
the area covered at both ends of the heat sink, the FIGURE 24: Norton Source Model.
quicker and better this thermal “short” will work.
One sensor that is modeled as a Norton current source
is the photodiode [1]. A common op amp circuit used
for photocurrent measurements is the transimpedance
amplifier (see Figure 32).
Sometimes, high impedance sources are modeled as a
voltage source with a high series resistance (a
Thevenin model):

VIN
RS
VS

FIGURE 25: Thevenin Source Model.

The pH electrode [1] is one example with a Thevenin
source. A common op amp implementation is a non-
inverting amplifier.

PCB Surface Leakage

PARASITIC SURFACE RESISTANCES
Surface contamination on a PCB creates resistive
paths for leakage currents. These leakage currents can
cause appreciable voltage shifts, even in well-designed
circuits. The contamination can be humidity (moisture),
dust, chemical residue, etc.

 2009-2012 Microchip Technology Inc. DS01258B-page 11

AN1258
On a PCB, leakage currents flow on the surface, to a CLEANING
sensitive node (high resistance), from nearby bare
A standard PCB clean step helps minimize surface
metal objects (including traces) at a different voltage.
contamination, but may not eliminate the problem. An
To model sensitivity to surface contamination in your additional cleaning step, using isopropyl alcohol, is
circuit, add resistors between the high impedance node needed to clean the residue left by some PCB cleaning
and other nearby nodes. For example, Figure 26 solvents. This can then be blown dry using compressed
shows an amplifier circuit with a Thevenin source (VS air (with an in-line moisture trap).
and RS). Since RS is high and the amplifier’s input is
high impedance, VIN is a high impedance node. Para- COATING
sitic resistances (RP1 to RP4) are connected to all other In order to maintain the PCB cleanliness after the initial
(nearby) voltage nodes (traces on a PCB), including clean, you may coat the PCB surface. The coating
ground. RP1 to RP4 are open-circuited for most design needs to be a barrier to moisture and other
work. For leakage current design calculations, they contaminants; solder mask, epoxy and silicone rubber
take on high resistance values (usually one at a time). are examples.
The coating will have internal (bulk) leakage currents;
this effect needs to be evaluated for your design.
RP1 VDD
GUARD RINGS
VIN
RS RP2 Guard rings surrounding critical signal traces, when
VOUT properly applied, can significantly reduce PCB surface
leakage currents into critical (high resistance) nodes.
VS These guard rings have no solder mask so that the
RP4 RP3
leakage currents flow into them, instead of into the
sensitive trace. The guard ring is biased at the same
FIGURE 26: Thevenin Source and Para- voltage as the sensitive node; it needs to be driven by
sitic Leakage Resistances. a low impedance source.
Guard rings increase the capacitance at critical nodes.
Figure 27 shows an amplifier circuit with a Norton
Since they are driven by low impedance sources, these
source.
capacitances have little effect on performance.

Unity Gain Buffer

RP1 VDD Figure 28 shows a unity gain buffer with a guard ring.
This guard ring is biased by VOUT and protects
VIN (surrounds) the op amp’s non-inverting input (and all
RP2
top metal connected to it) on the PCB surface. The
VOUT
diagram is for surface mount components only. RN is
IS RS an 0805 SMD to give sufficient clearance for the guard
RP3 ring trace between its pads.

FIGURE 27: Norton Source and Parasitic U1 VDD

Leakage Resistances.
The parasitic resistor values (RP) depend on your PCB VIN C1
layout. For a typical layout, with today’s geometries RN
(traces are close and short) and materials, we have: VOUT
• RP ~ 1000 GΩ, low humidity and contamination VDD C1
• RP ~ 1 GΩ, high humidity and contamination
These RP values need to be modified for atypical VIN U1
geometries; see Appendix B: “PCB Parasitic Resis- RN
tance”. These RP values also need to be modified for
the worst case conditions for your application. VOUT
Measurements in your conditions, and with your PCB
layout, will give better estimates of RP. FIGURE 28: Unity Gain Buffer with Guard
Ring.

DS01258B-page 12  2009-2012 Microchip Technology Inc.

 AN1258
The parasitic resistances are connected as shown in The parasitic resistances are connected as shown in
Figure 29. RP2 injects current into U1’s non-inverting Figure 31. Similar to the Unity Gain Buffer in the last
input (the high impedance node). The other parasitic section, U1’s offset voltage (VOS) is across RP2, which
resistors inject current into the guard ring, which is greatly reduces its leakage current. The other parasitic
driven by VOUT; they do not affect the performance. resistances are driven by VOUT, RF and RG; they do not
The voltage across RP2 is U1’s offset voltage (VOS), so affect the performance. The leakage current is typically
the leakage current is greatly reduced. For instance, if reduced by a factor of about 1000.
VOS  ±2 mV and the voltage without the guard ring is
2V, the leakage current would be reduced by a factor of VDD
about 1000. RP1 RP3
RP2
VDD
RP3 VIN U1 C1
RP1
RP2 RN
RN
VIN U1 C1 VOUT
RP4 RG RF

VOUT RP4 RP5

FIGURE 29: Equivalent Circuit for Unity FIGURE 31: Equivalent Circuit for Non-
Gain Buffer with Guard Ring. inverting Amplifier with Guard Ring.
One example of an application that sometimes uses
Transimpedance Amplifier
unity gain op amps are pH meters. In that case, how-
ever, both VIN and RN are located off the PCB; the Figure 32 shows a photo-diode at the input of a
guard ring only needs to surround U1’s non-inverting transimpedance amplifier, with a guard ring. This guard
input. ring is biased at ground; it protects (surrounds) the op
amp’s inverting input (and all top metal connected to it)
Non-inverting Gain Amplifier on the PCB surface. RF is high valued for the DC gain
Figure 30 shows a non-inverting gain amplifier with a (VOUT/ID1).
guard ring. This guard ring is biased by VOUT, RF and
RG; it protects (surrounds) the op amp’s non-inverting VDD
input (and all top metal connected to it) on the PCB RF U1
surface. RF and RG are low impedance, to drive the
guard ring properly. RN is a low valued resistor that CF
cancels thermojunction voltage effects, but has little C1
effect on bias current errors (e.g., IBRN << ±1 mV). D1
VOUT

RF CF
VDD
U1 RF
RG
VOUT
ID1
VIN C1 VDD
RN U1 C1
VOUT D1

VDD C1
FIGURE 32: Photo-diode and
VIN U1 Transimpedance Amplifier, with Guard Ring.
RN The parasitic resistances are connected as shown in
Figure 33. Similar to the Non-inverting Gain Amplifier in
VOUT the last section, U1’s offset voltage (VOS) is across RP1,
RG RF which greatly reduces its leakage current. The other
parasitic resistances are connected to ground; they do
FIGURE 30: Non-inverting Gain Amplifier not affect the performance. The leakage current is
with Guard Ring. typically reduced by a factor of about 1000.

 2009-2012 Microchip Technology Inc. DS01258B-page 13

AN1258

Top Trace
CF RP2
RP1
RF RP1
VOUT
ID1
VDD Bottom Trace
U1 C1 FIGURE 34: Equivalent Circuit for
D1
Parallel Traces, Opposite Surfaces.
RP3
Any two metal areas on the PCB (on a surface or buried
in an inner layer), at different potentials, will have a
FIGURE 33: Equivalent Circuit for Photo- leakage current between them. The value of the
diode and Transimpedance Amplifier, with Guard parasitic (bulk) resistance depends on:
Ring. • The geometry of the areas
- The distance between
Guard Rings on Both PCB Surfaces
- The cross sectional area seen by the current
For op amps in through-hole packages (e.g., PDIP),
• Nearby metal objects (e.g., a guard ring) that
guard rings are needed on both top and bottom
modify the current flow path
surfaces. The same design principles apply to both
surfaces. • The volume resistivity (ρV)
- Dielectric material
Any jumper traces (via to other surface, trace and via
back to the original surface), connected to traces with - Exposure to chemicals (e.g., water)
guard rings, also need guard rings around the jumper The following discussion shows simple techniques to
traces. It is better, when possible, to avoid jumper minimize these leakage currents. See Appendix B:
traces for critical nodes. “PCB Parasitic Resistance” for ways to estimate bulk
leakage currents.
PCB Bulk Leakage
SEPARATION
The dielectric material used in a PCB (e.g., FR4) is an
Moving traces to the surfaces, from inner layers,
insulator. Its resistance to leakage currents through the
increases the distance between them (e.g.,
bulk (the dielectric) is described by its volume resistivity
Example 1).
(ρV). ρV values vary considerably, depending on the
dielectric and on ambient conditions. Example 2 shows two parallel traces, with a distance
separating them. This extra distance increases the
Usually, bulk leakage currents are much smaller than
parasitic resistance.
surface leakage currents; they can be neglected in
many designs. Designs that minimize surface leakage
currents, however, may be affected by bulk currents. EXAMPLE 2: TWO PARALLEL TRACES,
WITH OFFSET
Example 1 shows one example of how bulk leakage
currents occur. Two traces run in parallel and are Top View
separated by the dielectric. The leakage current
between the traces, flowing through the dielectric, is
modelled by a parasitic resistor (see RP1 in Figure 34).

EXAMPLE 1: PARALLEL TRACES,

OPPOSITE SURFACES End View Side View

Top View

End View Side View

DS01258B-page 14  2009-2012 Microchip Technology Inc.

 AN1258
CROSSED TRACES GUARD PLANE
When two traces must cross, place them on opposite Example 5 shows a trace on the left (node 1), a guard
surfaces and in normal directions to minimize the plane (node 2) and a sensitive trace (node 3). The
parasitic resistance; see Example 3. guard plane behaves similar to a guard ring, except
that it forms a distributed attenuator to the input voltage
EXAMPLE 3: TWO NORMAL TRACES (see Figure 36); this attenuation can be much greater.

Top View EXAMPLE 5: TWO PARALLEL TRACES,

WITH GUARD PLANE
Top View

End View Side View

End View Side View

GUARD RINGS
Example 4 shows a trace on the left (node 1), a guard
ring (node 2) and a sensitive trace (node 3). The guard RPB1 RPB3 RPB5 RPB7
ring provides a low resistance path that redirects some V1 V3
of the current between node 1 and node 3 to itself. RPB2 RPB4 RPB6 RPB8
RPB2 in Figure 35 acts as an attenuator to the input
voltage (V1). When V2 ≈ V3, the parasitic current (into
V3) is significantly reduced.
V2 (guard plane)
EXAMPLE 4: TWO PARALLEL TRACES, FIGURE 36: (Lumped) Equivalent Circuit
WITH GUARD RING for Two Parallel Traces, With Guard Plane.
Top View
DIELECTRIC MATERIAL
Changing the dielectric material changes its bulk
resistivity (ρV) and susceptibility to humidity. For
designs that need exceptional performance, this is an
option worth exploring.

MOISTURE CONTROL
When a dielectric is exposed to moisture for an
extended period of time, it can become wet. This
End View Side View
reduces its bulk resistivity (ρV).
Measures to control exposure to moisture reduce this
effect. One possibility is the use of coatings.

RPB1 RPB3 ISOLATING SENSITIVE NODES

V1 V3 Another way to minimize PCB leakage currents is to
RPB2 isolate sensitive nodes (wires, package pins, etc.) from
the board (i.e., not touching).
One approach is to use teflon stand-offs. This has
V2 (guard ring) technical advantages, but can be costly to implement.
FIGURE 35: Equivalent Circuit for Two Another approach is to keep sensitive nodes in the air.
Parallel Traces, With Guard Ring. Bending package leads and routing holes in the PCB
are possible techniques to accomplish this.

 2009-2012 Microchip Technology Inc. DS01258B-page 15

AN1258
OTHER TIPS DESIGN EXAMPLE
This section discusses other effects and design tips. This section goes over the thermal design of a thermo-
couple PCB available from Microchip. This PCB has
Packages the following descriptors:
• MCP6V01 Thermocouple Auto-Zeroed Reference
IC packages contribute to leakage currents. Pins that
Design
are close together (fine pitch) will see greater leakage
currents, due to dust and shorter leakage paths. The • 104-00169-R2
package itself will have bulk leakage, which depends • MCP6V01RD-TCPL
on its chemistry. The application of this PCB is discussed in detail in
reference [7].
Piezoelectric Effect
Some capacitors accumulate extra charge from Circuit Description
mechanical stress (a variable capacitor), creating a DC Figure 37 shows the general functionality of this design
shift. Some ceramic capacitors (not all) suffer from this (the schematic is shown in Figure A-1).
effect. Minimize stresses with acoustic noise reduction
techniques, and by making the PCB assembly more
PC MCP1541
rigid. (Thermal Management Software) 4.1V Reference

Triboelectric Effect USB

Mechanical friction can cause charges to accumulate PIC18F2250

(USB) Microcontroller
(a variable capacitor), causing a DC shift. Air flow over
VREF
a PCB is one source of mechanical friction. Flexing 10-bit ADC
I2C™ Port CVREF
Module
wires and coax cables excessively can also cause this
to happen. Shield against air flow, and make bends in
wiring with a large radius. For remote sensors, use low SDA, VOUT2
SCLK, 3 ×1
noise coax or triax cable. nd
2 Order,
ALERT
Low-pass
Contact Potential Filter
MCP9800 VSHIFT
Temp. Sensor VOUT1
Sometimes, for convenience on the bench, a PCB has
sockets for critical components (e.g., an op amp). (cold junction
compensation) MCP6V01
While these sockets make it easy to change TCJ Difference Amp.
components, they cause significant DC errors in high Type K VP VM
precision designs. Thermocouple
(welded bead)
The problem is that the socket and the IC pins are TTC
made of different metals, and are mechanically forced
into contact. In this situation, there is a (contact) voltage Connector
(cold junction)
potential developed between the metals (the Volta
effect). Physicists explain this phenomenon through FIGURE 37: Thermocouple Circuit’s
the difference between their work functions. In our Block Diagram.
bench tests of our auto-zeroed op amps, we saw
voltage potentials of ±1 µV to ±2 µV due to the IC The (type K) thermocouple senses temperature at its
hot junction (TTC) and produces a voltage at the cold
socket.
junction (at temperature TCJ). The conversion constant
The solution is very simple; do not use sockets for for type K thermocouples is roughly 40 µV/°C. This
critical components. Instead, solder all critical voltage (VP – VM) is input to the Difference Amplifier
components to the PCB. (MCP6V01).
The MCP9800 senses temperature at the Type K
Thermocouple’s cold junction (TCJ). The result is sent
to the PICmicro microcontroller via an I2C™ bus. The
firmware corrects the measured temperature for TCJ.
The difference amplifier uses the MCP6V01
auto-zeroed op amp to amplify the thermocouple’s
output voltage. The VREF input shifts the output voltage
down so that the temperature range includes -100°C.
The VSHIFT input shifts the output voltage, using a

DS01258B-page 16  2009-2012 Microchip Technology Inc.

 AN1258
digital POT internal to the microcontroller (CVREF), so 1. The Difference Amplifier is as close to the
that the temperature range is segmented into 16 sensor as possible, and is on the opposite PCB
smaller ranges; this gives a greater range (-100°C to surface from the PICmicro microcontroller. This
+1000°C) with reasonable accuracy. minimizes electrical and thermal crosstalk
The MCP1541 provides an absolute reference voltage between the two active devices.
because the thermocouple’s voltage depends only on 2. Small resistors (0805 SMD) reduce the
temperature (not on VDD). It sets the nominal VOUT and thermoelectric voltages, for a given temperature
serves as the reference for the ADC internal to the gradient.
microcontroller. 3. The resistors that are a part of the Difference
nd
The 2 Order, Low-pass Filter reduces noise and Amplifier play a critical role in this design’s
aliasing at the ADC input. A double R-C filter was accuracy.
chosen to minimize DC errors and complexity. a) R6 and R7 are at the input from the thermo-
couple, and give a gain of 1000 V/V to
CVREF is a digital POT with low accuracy and highly
VOUT1. They are arranged so that their
variable output resistance. The buffer (×1 amplifier)
thermoelectric voltages cancel.
eliminates the output impedance problem, producing
the voltage VSHIFT. Since CVREF has 16 levels, we can b) R9 and R10 are at the input from the range
shift VOUT1 by 16 different amounts, creating 16 selection circuitry (VSHIFT), and give a gain
smaller ranges; this adds 4 bits resolution to the of 17.9 V/V to VOUT1. Changing their
measured results (the most significant bits). The 10 bits location and orientation on the PCB might
produced by the ADC are the least significant bits; they improve the performance.
describe the measured values within one of the 16 c) R8 and R11 convert the inputs to the output
different smaller ranges. voltage (VOUT1). Changing their location
and orientation may not improve the
VSHIFT is brought back into the PICmicro microcon-
performance enough to be worth the
troller so that it can be sampled by the ADC. This gives
trouble.
VSHIFT values the same accuracy as the ADC (“10
bits”), which is significantly better than CVREF’s accu- Figure 39 shows the top metal layer of the PCB. The
racy. The measured value of VOUT2 is adjusted by this sensitive analog and sensor circuitry is connected to
measured VSHIFT value. this layer.
The overall accuracy of this mixed signal solution is set
by the 10-bit ADC. The resolution is 14 bits, but the
accuracy cannot be better than the ADC, since it 4
calibrates the measurements.
6
PCB Layout 5
In the figures in this section (Figure 38 through 7
Figure 43), the red numbers (inside the circles) point to
key design choices, which are described by a list after 6
each figure.
Figure 38 shows the top silk screen layer of the PCB 4
designed for the MCP6V01 Thermocouple
Auto-Zeroed Reference Design.
FIGURE 39: 1st Layer – Top Metal.
4. Metal fill, connected to the ground plane,
minimizes thermal gradients at the cold junction
connector.
5. The MCP9800 Temperature Sensor (cold
3 junction compensation) is centered at the cold
junction connector to give the most accurate
reading possible.
2
1
6. Sensor traces are separated from power (top
layer) and digital (bottom layer) traces to reduce
crosstalk.
7. The MCP9800’s power traces are kept short,
straight and above ground plane for minimal
FIGURE 38: 1st Layer – Top Silk. crosstalk.

 2009-2012 Microchip Technology Inc. DS01258B-page 17

AN1258
Figure 40 shows the power plane. It minimizes noise 14. This ground plane extension provides better
conducted through the power supplies and isolates the isolation between digital signals and the
analog and digital signals. MCP9800’s power supply. It also helps protect
the thermocouple signal lines. However, it
increases the thermal conduction between the
left and right sides of the PCB.
8 10 9
Figure 42 shows the bottom silk layer.

15

16
17

FIGURE 40: 2nd Layer – Power Plane.

8. The power plane on the left helps keep the
temperature relatively constant near the
auto-zeroed op amp. It also provides isolation
from the microcontroller’s electrical and thermal FIGURE 42: 4th Layer – Bottom Silk.
outputs. 15. The USB connector and its components are
9. The power plane on the right helps keep the isolated from the rest of the circuit.
temperature relatively constant near the 16. The crystal (XTAL) oscillator is as far from every-
thermocouple’s cold junction and MCP9800 thing else as possible, except from the clock
cold junction temperature sensor. input pins of the microcontroller.
10. The FR4 gap provides attenuation to heat flow 17. The microcontroller produces both thermal and
(a relatively high temperature drop) between the electrical crosstalk, so it is isolated from the ana-
active components on the left (MCP6V01 and log components.
PIC18F2550) and the sensors on the right (ther-
mocouple and MCP9800). Figure 43 shows the bottom metal layer of the PCB.
The digital circuitry is connected to this layer.
Figure 41 shows the ground plane. It also minimizes
noise conducted through the power supplies and
isolates the analog and digital signals.
18

11 13 12
19

14

FIGURE 43: 4th Layer – Bottom Metal.

18. Metal fill, connected to the ground plane,
FIGURE 41: 3rd Layer – Ground Plane. minimizes thermal gradients at the cold junction.
19. The digital traces that run under the ground
11. Same function as #8.
plane extension have series resistors inserted
12. Same function as #9. inside the FR4 gap. This reduces the thermal
13. Same function as #10. conduction between the sides that solid traces
would produce; otherwise this would become
the worst case thermal conductor between the
microcontroller and the temperature sensors.

DS01258B-page 18  2009-2012 Microchip Technology Inc.

 AN1258
SUMMARY REFERENCES
This application note covers thermal effects on Printed
Circuit Boards (PCB) encountered in high (DC) Related Application Notes
precision op amp circuits. Causes, effects and fixes [1] AN990, “Analog Sensor Conditioning Circuits –
have been covered. An Overview,” Kumen Blake; Microchip
Thermocouple junctions are everywhere on a PCB. Technology Inc., DS00990, 2005.
The Seebeck effect tells us that these junctions create [2] AN1177, “Op Amp Precision Design: DC
a thermoelectric voltage. This was shown to produce a Errors,” Kumen Blake; Microchip Technology
voltage across resistors (and other components) in the Inc., DS01177, 2008.
presence of a temperature gradient.
[3] AN1228, “Op Amp Precision Design: Random
Preventing large thermoelectric voltages from Noise,” Kumen Blake; Microchip Technology
occurring is usually the most efficient way to deal with Inc., DS01228, 2008.
thermocouple junctions. The amount of heat generated
on the PCB can be reduced, and the heat flow
Other Application Notes
redirected away from critical circuit areas. It also pays
to keep any temperature changes from occurring too [4] AN990, “Analog Sensor Conditioning Circuits –
quickly. An Overview,” Kumen Blake; Microchip
Any remaining thermoelectric voltage effects need to Technology Inc., 2005.
be reduced. Choosing the metals, in critical areas, to [5] AN684, “Single Supply Temperature Sensing
have approximately the same work function will with Thermocouples,” Bonnie C. Baker; Micro-
minimize the thermoelectric coefficients of the metal chip Technology Inc., DS00684, 1998.
junctions. Critical components can be oriented so that
[6] AN679, “Temperature Sensing Technologies,”
they follow constant temperature contour lines. It is
Bonnie Baker,” Microchip Technology Inc.,
possible to cancel most of the thermoelectric voltage
DS00679, 1998.
effects at the input of op amps by correctly orienting
them. Smaller components, spaced closer together, will
also help. Other References
Once a design has been implemented on a PCB, it [7] User’s Guide, “MCP6V01 Thermocouple
pays to measure its thermal response. Information on Auto-Zeroed Reference Design,” Microchip
where to focus design effort can greatly speed up the Technology Inc., DS51738, 2008.
design process. Information has been given on [8] “The OMEGA® Made in the USA Handbook™,”
measuring temperature, thermal gradients, package Vol. 1, OMEGA Engineering, Inc., 2002.
JA‘s and troubleshooting tips and tricks.
Leakage current effects also need to be minimized.
Methods to accomplish this for surface and bulk
leakage currents have been shown.
Other effects were also discussed.
A design example using the MCP6V01 Thermocouple
Auto-zeroed Reference Design PCB illustrates the
theory and recommendations given in this application
note. The circuit operation is described, then the PCB
layout choices are covered in detail.
At the end of this application note, references to the
literature and an appendix with the design example’s
schematic are provided.

 2009-2012 Microchip Technology Inc. DS01258B-page 19

 J2
HDR1X6

N/C
VDD

FIGURE A-1:
VDD

DS01258B-page 20
U1
APPENDIX A:

1 28
AN1258

MCLR/VPP/RE3 RB7/KBI3/PGD
VDD R5
2 27 10K
VOUT RA0/AN0 RB6/KBI2/PGC
C11 3 26
0.1UF VSHIFT RA1/AN1 RB5/KBI1/PGM ALERT
U3 R14 U2 VDD
4 RA2/AN2/VREF–/CVREF 25
1.0K VREF CVREF RB4/AN11/KBI0
1 VDD SDA 5 VOUT 2 VDD
SDA 5 24
2 3 VDD C5 RA3/AN3/VREF+ RB3/AN9/CCP2/VPO
VSS VSS R1
3ALERT SCLK4
SCL VIN 1uF 6 23 10K
R16 1 RA4/TOCKI/C1OUT/RCV RB2/AN8/INT2/VMO R2
ALERT R15
MCP1541 7 22
RA5/AN4/SS/HLVDIN/C2 RB1/AN10/SCK/SCL
C9 10K SCL
1.0K MCP9800_SOT23-5 1.0K C12
0.1uF 22pF 8 VSS 21
RB0/AN12/SDI/SDA SDA
9 VDD
Y1 OSCI/CLKI VDD 20
20 MHz 10
OSC2/CLKO/RA6 VSS 19 C1
11 18 0.1UF
RC0/T1OSO/T13CKI RC7/RX/DT/SDO
C10 12 17
22pF RC1/T1OSI/CCP2/UOE RC6/TX/CK
13 16
RC2/CCP1 RC5/D+/VP
14 15
VUSB RC4/D–/VM
C8
REFERENCE DESIGN)

0.47uF
PIC18F2550–SOIC28
VDD R3 L1
1 OHM 10uH
N/C

1 2 3 4 5
VDD C3 R4 9
C2 C4 6
1uF 10uF 10uF 100K 10 11
U4 C14 J3
0.1UF 8 7
1 VOUT VDD

THERMOCOUPLE CIRCUIT’S SCHEMATIC.

2 VSS
R9 R8 USB CONN
3 VIN+ VIN– 5.6K 100K
CVREF
4
VSHIFT
MCP6001_SOT23-5 VSHIFT VDD

C13
J1 U5 0.1UF 2nd Order RC
THERMO_CONN Low-Pass Filter
1 NC NC 8
R6 100 2 VIN– 7 VOUT2
VDD
3 6 R12 R13
VIN+ VOUT VOUT
R7 100 4 5 499 499
VSS NC
C6 C7
MCP6V01_SOIC 0.1uF
VOUT1 0.1uF

R10 R11
5.6K 100K
VREF

VREF

VDD TP2 SDA TP4 ALERT

PCB SCHEMATIC (MCP6V01 THERMOCOUPLE AUTO-ZEROED

SCL TP3 TP5

TP1

 2009-2012 Microchip Technology Inc.

 AN1258
APPENDIX B: PCB PARASITIC Example B-2 shows two parallel planes on opposite
PCB surfaces. This geometry is useful for measuring
RESISTANCE
ρV on a given PCB process. Make the planes as large
The body of this application note emphasized better as possible, to maximize the bulk leakage current.
PCB designs. For this reason, detailed analyses of For instance, a 6 in × 6 in PCB (60 mil thick) could
leakage currents were not included. have two planes 5 in long and 5 in wide. With
This appendix shows you how to estimate parasitic ρS = 1 × 105 MΩ and ρV = 1 × 106 MΩ cm, we can
resistances on a PCB. This will help adjust designs estimate RPS ≈ ∞ and RPB ≈ 0.9 GΩ.
sensitive to leakage currents.
EXAMPLE B-2: PARALLEL PLANES
B.1 PCB Resistivities
Top View
Surface resistivity (ρS, in units of MΩ, or equivalent)
describes the local, physical behavior of a PCB surface
under a voltage gradient field. The aggregate behavior
over all such points creates an equivalent, parasitic
surface resistance (RPS) between any two points.
Bulk resistivity (ρV, in units of MΩ cm, or equivalent)
describes the local, physical behavior inside a PCB’s
dielectric under a voltage gradient field. The aggregate End View Side View
behavior over all such points creates an equivalent,
parasitic bulk resistance (RPB) between any two points.
Typical resistivities for FR4, based on several
manufacturer’s data, are: Be sure to measure ρS and ρV under various conditions
• ρS ≈ 1 × 105 MΩ seen by your circuit. These values will also change
• ρV ≈ 1 × 106 MΩ cm between different manufacturers and processes.

Different operating conditions and manufacturing flows

will produce different values; sometimes by two or
B.3 Numerical Solutions
three orders of magnitude in either direction.
B.3.1 COMMERCIAL SOFTWARE
B.2 Measuring Resistivities When optimizing a complicated PCB geometry, it may
pay to use a PDE (partial differential equation) solver.
Example B-1 shows two parallel, serpentine traces on Searching the internet for “partial differential equation
the same PCB surface. This geometry is useful for software,” or the equivalent, should bring up several
measuring ρS on a given PCB process. Make the commercially available software packages.
traces as long as possible, and as close together as
possible, to maximize the surface leakage current. B.3.2 USING SPICE
For example, a 6 in × 6 in PCB (60 mil thick) could It is possible to use SPICE to implement a network of
have two serpentine traces 10 mil wide and 10 mil resistors representing heat flow between adjacent
apart. If the overlap area is 5 in × 5 in, the equivalent points.
length would be 1250 in. With ρS = 1 × 105 MΩ and Select an array of equally spaced points. Resistors
ρV ≈ 1 × 106 MΩ cm, we estimate RPS ≈ 0.8 MΩ and connect adjacent points and represent the local
RPB ≈ 2 GΩ. resistance to current flow, in that direction.
To simulate a particular parasitic resistance, force a
EXAMPLE B-1: PARALLEL TRACES
voltage at its input and measure the current at its
Top View output. The voltage-to-current ratio is that resistance.
Figure B-1 shows a typical array point, in a two
dimensional (2D) array. The central point is at voltage
V0. The four adjacent points are connected by the four
resistors R1, R2, R3 and R4.

 2009-2012 Microchip Technology Inc. DS01258B-page 21

AN1258

V2
R2
R1
V0 V1
V3
R3
R4
V4

FIGURE B-1: TYPICAL 2D ARRAY.

The resistors represent the local resistivity between
adjacent points. Use very low valued resistors for
points connected by metal. For instance, R1 is:

EQUATION B-1:
R1 = ρS ∆x / ∆y, for surface calculations
= ρV ∆x / (∆y ∆z), for bulk calculations
Where:
ρS = Local Surface Resistivity (MΩ)
ρV = Local Bulk Resistivity (MΩ cm)
∆x = grid spacing in the x-direction
∆y = grid spacing in the y-direction
∆z = z-dimension (common to all objects)

This approach is easily extended to three dimensions

(3D).

B.3.3 USING A SPREADSHEET

It is possible to simulate in a spreadsheet by using an
iterative approach. Set up the resistive array like the
last section. The iteration equation at V0 is:

EQUATION B-2:
V0 = (V1/R1 + V2/R2 + V3/R3 + V4/R4)
/ (1/R1 + 1/R2 + 1/R3 + 1/R4)
= (V1 + V2 + V3 + V4) / 4, all Rs equal

The convergence can be slow, so this approach should

be used for simple problems.
Once the voltages are determined, it is a simple matter
to calculate the sum of currents into (or out of) a node
of interest.
This approach is easily extended to three dimensions
(3D).

DS01258B-page 22  2009-2012 Microchip Technology Inc.

 AN1258
APPENDIX C: REVISION HISTORY

Revision B (July 2012)

The following is the list of modifications:
1. Added power supply components to circuit
diagrams.
2. Re-wrote Section “Leakage Currents”,
starting on page 11.
a) Added information on high impedance
sources and parasitic leakage resistances.
b) Corrected guard ring connections so they
are driven by a low impedance source.
c) Added current source examples.
d) Added discussion of bulk leakage currents.
e) Expanded discussion on isolating sensitive
connections from a PCB.
3. Added Section “Other Tips”, on page 16.
4. Added AN990 to Section “References”, on
page 19.
5. Added Appendix B: “PCB Parasitic
Resistance”, starting on page 21.
6. Added Appendix C: “Revision History”, on
page 23.

Revision A (March 2009)

• Original Release of this Document.

 2009-2012 Microchip Technology Inc. DS01258B-page 23

AN1258
NOTES:

DS01258B-page 24  2009-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-62076-404-6

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2009-2012 Microchip Technology Inc. DS01258B-page 25

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DS01258B-page 26  2009-2012 Microchip Technology Inc.