UNIT – 1

8085 Micro Processor

INTRODUCTION:-
The 8085 microprocessor is an 8-bit microprocessor developed by Intel in 1976. It
is a part of the 8-bit microprocessor family and is widely used in embedded
systems and educational applications. The 8085 microprocessor operates with a
single +5V power supply. It has a 16-bit address bus, allowing it to access up to
64KB of memory, and an 8-bit data bus for data transfer. Known for its simplicity
and ease of use, the 8085 includes features like a built-in clock generator, serial
I/O control, and five hardware interrupts, making it a fundamental learning
platform for understanding microprocessor architecture and programming.

Features of 8085 Microprocessor

8-bit Processor: It processes 8 bits of data at a time.
16-bit Address Bus: Can address up to 64KB (65,536 bytes) of memory.
8-bit Data Bus: Transfers 8 bits of data simultaneously.
Operating Frequency: Typically runs at 3 MHz, though versions at 5 MHz also
exist.
Single +5V Power Supply: Simplifies circuit design.
74 Instructions: Supports a relatively simple instruction set, making it easy to
learn.
246 Opcodes: Provides a wide range of operations.
Built-in Clock Generator: No need for an external clock; simplifies system design.
5 Interrupts: Includes 5 interrupt signals – TRAP (non-maskable), RST7.5, RST6.5,
RST5.5, and INTR.
Serial I/O Control: Provides SID (Serial Input Data) and SOD (Serial Output Data)
pins for serial communication.
16-bit Program Counter (PC): Keeps track of the memory address of the next
instruction.
16-bit Stack Pointer (SP): Used for stack operations.
Accumulator and Flag Register: 8-bit accumulator and five condition flags (Sign,
Zero, Auxiliary Carry, Parity, Carry).
Six General Purpose Registers: B, C, D, E, H, and L – can be used individually or as
register pairs (BC, DE, HL).
Simple and Cost-Effective: Ideal for learning and small embedded applications.

MICROPROCESSOR V/S MICROCONTROLLER

Feature Microprocessor Microcontroller
A CPU (Central Processing Unit) on a A complete computer system on a
Definition
single chip. single chip.
Only the processor; memory and I/O Includes CPU, memory (RAM,
Components
must be added externally. ROM), and I/O ports built-in.
Used in general-purpose computing Used in embedded systems (e.g.,
Usage
(e.g., laptops, desktops). washing machines, cars).
Power
Higher Lower
Consumption
More expensive due to additional
Cost Cheaper and compact.
external components.
Processing Higher performance for complex Limited performance, optimized for
Power tasks. specific tasks.
Highly flexible, can support complex Less flexible, usually runs real-time
Flexibility
OSs like Windows/Linux. or minimal OS.
Arduino (AVR), PIC, ARM Cortex-
Examples Intel Core i7, AMD Ryzen, Intel 8086
M

Hardware architecture of 8085 Microprocessor

Input Unit:- In the 8085 microprocessor, the input unit refers to the part of the system that
allows data to be received from external devices (like a keyboard, sensor, or switch) into the
microprocessor for processing.

CPU:- In micro processor, CPU stands for central processing unit.

Main Components of the 8085 CPU:
Arithmetic and Logic Unit (ALU):
Performs arithmetic operations (like addition, subtraction).
Performs logical operations (like AND, OR, XOR, compare).

Registers:
Accumulator (A): Main register used in operations.
General-purpose registers: B, C, D, E, H, L (can be used in pairs like BC, DE, HL).
Program Counter (PC): Holds the address of the next instruction.
Stack Pointer (SP): Points to the top of the stack in memory.
Temporary Register: Used internally by the ALU.
Flag Register: Holds status flags (Sign, Zero, Auxiliary Carry, Parity, Carry).

Timing and Control Unit:

Generates control signals (like RD̅ , WR̅ , ALE, etc.).
Synchronizes all operations with the system clock.
Controls communication between CPU and memory/I/O.

Control Signals:
These are managed by the CPU to read/write data:
RD̅ (Read)
WR̅ (Write)
IO/̅M (Distinguishes memory vs I/O)
ALE (Address Latch Enable)
INTA̅ (Interrupt Acknowledge)

Output unit:-In the 8085 microprocessor, the output unit refers to the mechanism that
allows the microprocessor to send data to external output devices, such as:
1)LEDs Displays (like 7-segment or LCD)
2)Printer
3)Motors
4)Speakers
Pin diagram of 8085 MicroProcessor

Power Supply & Clock (4 pins)Vcc (pin 40):

+5 V power supply.
Vss (pin 20): Ground.
X1/X2 (pins 1–2): Connect crystal or RC/LC network; internal clock runs at half the crystal
frequency.
CLK OUT (pin 37): Outputs internal clock signal to other devices.

Address & Data Buses

AD0–AD7 (pins 12–19): Multiplexed lower 8 bits of address/data bus

A8–A15 (pins 21–28): Upper 8 bits of the address bus
ALE signal helps demultiplex AD0–AD7 so address bits can be latched externally

Control & Status Signals

ALE: Address Latch Enable—high during T1 to latch AD0–AD7, then low for data phase IO/M’,
S1, S0: Status bits to distinguish operations (memory vs I/O, opcode fetch/read/write)
RD’ (pin 32): Active‑low read control
WR’ (pin 31): Active‑low write control
READY: Indicates if peripheral is ready, otherwise micro enters wait state

Interrupts & Externally Initiated Signals

INTR: General interrupt request
RST 7.5/6.5/5.5: Vectored maskable interrupts
TRAP: Non-maskable, highest priority interrupt
INTA’: Interrupt acknowledge signal

Serial I/O
SID (pin 4): Serial Input Data
SOD (pin 5): Serial Output Data
DMA Control
HOLD (pin 38): External device requests bus takeover
HLDA (pin 39): Acknowledges HOLD; CPU releases buses

Reset Signals
RESET IN (pin 36): Active‑low; resets PC to 0000H and tri‑states buses
RESET OUT (pin 3): Active‑high; resets connected peripherals

Memory organization-I/O Ports and data transfer

1) Memory and I/O Port Organization in 8085 Memory Organization:

8085 can address up to 64 KB (65536 bytes) of memory.
Uses a 16-bit address bus (A0–A15) → Address range: 0000H to FFFFH.
Memory is divided into program memory (stores code) and data memory (stores
variables/data).

I/O Port Organization:

8085 supports two types of I/O mapping:
8-bit address for I/O ports → Supports 256 I/O ports (00H to FFH).
Uses special instructions: IN and OUT
I/O and memory spaces are separate.
Memory-Mapped I/O
No separate IN/OUT instructions needed.
Assigned 16-bit addresses (just like RAM/ROM).
I/O devices are treated like memory locations.

2. Data Transfer Types in 8085

There are four major types of data transfer methods:
1. Programmed I/O :-
CPU directly communicates with the I/O port using IN and OUT.
Slow, since CPU waits for each operation.
2. Interrupt-
Driven I/O Device interrupts CPU when it's ready to transfer data.
CPU temporarily halts main program to service the I/O.
3. DMA (Direct Memory Access)
Data transferred directly between memory and I/O without CPU involvement.
CPU gives up control of buses via HOLD and HLDA pins.
4. Memory-Mapped I/O Transfer
Data is transferred using memory-like read/write operations to I/O devices.

Interrupts:-
Interrupts in the 8085 are signals that temporarily stop the CPU’s normal execution to give
attention to an urgent task (like reading input from a keyboard or sensor). Once the interrupt is
handled, the CPU resumes its previous task.
Types of interrupts:-

1. TRAP
Non-maskable, cannot be disabled.
Used for emergency tasks (e.g., power failure, restart).
Fixed vector address: 0024H
2. RST 7.5, RST 6.5, RST 5.5
Maskable (can be enabled/disabled via software).

Automatically jump to specific memory locations :

RST 7.5 → 003CH
RST 6.5 → 0034H
RST 5.5 → 002CH
3. INTR (Interrupt Request)
General-purpose maskable interrupt.
Needs external hardware to send the address using INTA̅ (Interrupt Acknowledge).
Priority: Lowest

8086 ARCHITECTURE

8086 Microprocessor Architecture

1. Basic Features

 Data bus: 16-bit (can transfer 16 bits of data at a time)

 Address bus: 20-bit (can address up to 1 MB of memory)
 Registers: 16-bit general and special-purpose registers
 Instruction Queue: 6 bytes (for pipelining)
 Clock speed: Typically 5 MHz to 10 MHz
2. Functional Units
The 8086 architecture is divided into two main units:

A. Bus Interface Unit (BIU)

Handles all data and address transfers on the buses. It fetches instructions from memory, queues
them, and sends/receives data to/from memory or I/O.

Components of BIU:

 Instruction Queue (6 bytes): Supports pipelining by prefetching instructions

 Segment Registers:
o CS (Code Segment)
o DS (Data Segment)
o SS (Stack Segment)
o ES (Extra Segment)
 Instruction Pointer (IP): Points to the next instruction in the code segment
 Address Generation Circuitry

B. Execution Unit (EU)

Executes the instructions fetched by BIU. It takes instructions from the queue and decodes and
executes them.

Components of EU:

 ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations

 General-purpose registers:
o AX (Accumulator)
o BX (Base)
o CX (Count)
o DX (Data)
 Index and pointer registers:
o SI (Source Index)
o DI (Destination Index)
o BP (Base Pointer)
o SP (Stack Pointer)
 Flag Register: 16-bit register with status flags (e.g., zero, sign, carry, overflow)

3. Pipelining (Instruction Queue)

 While the EU is executing an instruction, the BIU fetches the next instructions and places
them in the queue.
 This allows overlapping of fetch and execution cycles → improves performance.
4. Memory Segmentation
8086 uses segmented memory to access a larger memory space (1 MB) despite having only 16-
bit registers.

Each memory address is calculated as:

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Physical Address = Segment Register × 16 + Offset

Example:

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CS = 1234h, IP = 0010h
→ Physical Address = 12340h + 0010h = 12350h

5. Instruction Set Overview

8086 supports a rich instruction set including:

 Data transfer (MOV, PUSH, POP)

 Arithmetic (ADD, SUB, MUL, DIV)
 Logic (AND, OR, XOR, NOT)
 Control flow (JMP, CALL, RET)
 String operations
 Flag manipulation

PIN DIAGRAM OF 8086 MICROPROCESSOR

GND : Ground
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead of AD,
for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19: High order address bus. These are multiplexed with status signals.
S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus
controller for generating all the memory and I/O operation) access control signals. Any change
in S2, S1, S0 during T4 indicates the beginning of a bus cycle.

S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
A17/S4 A16/S3Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access
HE'/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use
BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2,
T3 and T4.
RD': This is used for read operation. It is an output signal. It is active when low.

READY : This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the microprocessor. The signal is active
high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of
each instruction for determining the availability of the request. If any interrupt request is found
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked
after resulting the interrupt enable flag. This signal is active high(1) and has been synchronized
internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally by software. A transition made
from low(0) to high(1) initiates the interrupt at the end of the current instruction. This input has
been synchronized internally.

INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
MN/MX' : Minimum/Maximum. This pin signal indicates what mode the processor will operate
in.
RQ'/GT1', RQ'/GT0' : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor's current bus cycle.
Each of the pin is bi-directional. RQ'/GT0' have higher priority than RQ'/GT1'.
LOCK' : Its an active low pin. It indicates that other system bus masters have not been allowed
to gain control of the system bus while LOCK' is active low(0). The LOCK signal will be active
until the completion of the next instruction.

TEST' : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
continue, else the processor remains in an idle state. The input is internally synchronized during
each of the clock cycle on leading edge of the clock.

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus
control activity. Its an asymmetric square wave with a 33% duty cycle.

RESET : This pin requires the microprocessor to terminate its present activity immediately. The
signal must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction
queue according to the table shown below:
QS1 QS0 Status
0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

M/IO': This signal is used to distinguish between memory and I/O operations. The M Signal is
Active high whereas the IO' Signal is Active Low. When this Pin is High, the memory operations
takes place. On the other hand, when the Pin is low, the Input/Output operations from the
peripheral devices takes place.

DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an
8286 or 8287 data bus transceiver. The direction of data flow is controlled through the
transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum
system which uses transceiver. DEN is active low(0) during each memory and input-output
access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an
active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an
acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the
8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is
never floated, is always integer.

8086 MICROPROCESSOR FAMILY

The 8086 Microprocessor Family refers to a set of microprocessors and closely related
components that are based on the Intel 8086, which was one of the earliest 16-bit
microprocessors developed by Intel. This family laid the foundation for the x86 architecture,
which is still in use today.
Intel 8086 Microprocessor - Overview

Feature Description

Introduced 1978

Manufacturer Intel

Architecture 16-bit

Clock Speed 5 MHz to 10 MHz

Address Bus 20-bit (can address 1 MB memory)

Data Bus 16-bit

Instruction Set x86

General-purpose (AX, BX, CX, DX), Segment (CS, DS, SS, ES), Pointer/index (SP, BP,
Registers
SI, DI), Flags

Mode of
Minimum mode (single processor), Maximum mode (multiprocessor system)
Operation

Package 40-pin DIP

Key Members of the 8086 Family

Chip Description

8086 Original 16-bit microprocessor with 20-bit address bus.

8088 Similar to 8086 but with an 8-bit external data bus (used in IBM PC).

80186 / 80188 Enhanced versions with built-in peripherals like timers, DMA, interrupt controller.

Introduced protected mode and better multitasking support; precursor to 32-bit

80286
processors.

8087 Coprocessor for floating-point arithmetic (used with 8086/8088).

8284 Clock generator and driver.

8288 Bus controller (used in maximum mode).

 Chip Description

8255, 8259, 8237,

Peripheral chips for I/O, interrupts, and DMA control.
etc.

Key Features of 8086

1. Pipelined Architecture:
o Uses a fetch-execute overlap mechanism with a 6-byte instruction queue (pre-
fetching).
o Allows faster instruction execution.
2. Segmentation:
o Uses segment:offset addressing (e.g., CS:IP) for accessing memory.
o Divides memory into four segments: Code, Data, Stack, and Extra.
3. Operating Modes:
o Minimum mode: For single CPU systems.
o Maximum mode: For multiprocessor systems (uses 8288 bus controller).
4. Interrupt System:
o Supports hardware and software interrupts.
o 256 interrupt vectors (from INT 00h to INT FFh).

INTERRUPTS AND INTERRUPTS RESPONSE

An interrupt is a mechanism by which the microprocessor temporarily halts its current
execution, saves its state, and executes a service routine (Interrupt Service Routine, or ISR) to
respond to an event.

Types of Interrupts in 8086

8086 supports two main categories of interrupts:

1. Hardware Interrupts

2. Software Interrupts

Each type can be further classified:

1. Hardware Interrupts

These are triggered by external devices through the INTR or NMI pins.
 Pin Name Type Vector Description

Non-Maskable Edge-triggered, Urgent tasks like power

NMI Type 2 (INT 2)
Interrupt cannot be disabled failure or hardware error

Interrupt Maskable, can be Provided by external device Can be prioritized using a

INTR
Request disabled using IF flag via interrupt vector table PIC like 8259A

On receiving an interrupt:

 8086 pushes FLAGS, CS, and IP onto the stack.

 Clears IF and TF flags to disable further interrupts.
 Jumps to the ISR (Interrupt Service Routine).

2. Software Interrupts

These are triggered by executing the INT instruction within a program.

Instruction Type Vector

INT n Software Interrupt n can be 0–255

INT 21h DOS Interrupt (e.g., for I/O) 33 (decimal)

INT 10h Video BIOS services 16 (decimal)

Predefined/Internal Interrupts (Exceptions)

These are triggered automatically by specific conditions or instructions.

Type Name Cause

0 Divide Error Division by zero or overflow in division

1 Single Step Trap flag is set (used in debugging)

2 NMI Non-maskable external interrupt

3 Breakpoint Triggered by INT 3 instruction (debugging)

4 Overflow Triggered by INTO instruction if OF = 1

Interrupt Vector Table (IVT)

  Location: Memory from 00000h to 003FFh (1 KB)
 Contains 256 entries (for INT 00h to INT FFh)
 Each entry = 4 bytes (2 bytes for IP, 2 bytes for CS)
 Address of ISR = vector_number × 4

Example:

 For INT 13h (disk services):

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ISR address = 13h × 4 = 4Ch

Memory locations 4Ch–4Fh store CS:IP of ISR.

Enabling/Disabling Interrupts
Instruction Description

Set Interrupt Flag

STI
(enable INTR)

Clear Interrupt
CLI Flag (disable
INTR)

Return from ISR

IRET (restores FLAGS,
CS, IP)

8086 SYSTEM TIMING – Complete Explanation

System timing in the 8086 microprocessor refers to the sequence of signals

and control operations that occur during instruction execution, memory
access, I/O operations, etc. Understanding timing is crucial for designing
hardware and interfacing peripherals.

8086 Modes of Operation

8086 can operate in two modes, which affect the system timing:
 Instruction Description

Mode Description

Minimum Used in single-processor systems. 8086 directly generates control

Mode signals.

Maximum Used in multiprocessor systems. Requires an external bus controller

Mode (8288) to generate control signals.

8086 Clock Signal (from 8284)

 8086 requires a clock input to function.
 Clock is provided by Intel 8284 Clock Generator.
 Typical frequency: 5 MHz to 10 MHz.
 A clock cycle is called a T-state (T1, T2, etc.).

Basic Bus Cycle Timing in Minimum Mode

Each bus cycle (memory or I/O access) typically consists of 4 T-states (T1 to
T4), and may extend with wait states (Tw) if needed.

Read Cycle Timing (Minimum Mode)

T-State Activity

T1 Address is placed on address bus; ALE = 1 to latch address

T2 RD = 0 (active), address held stable

T3 Data is read from memory or I/O

T4 RD = 1 (inactive), bus is released

If slower memory is used, WAIT states (Tw) are inserted between T3 and T4.

Write Cycle Timing (Minimum Mode)

T-State Activity

T1 Address is placed on address bus; ALE = 1

T2 WR = 0 (active), data is placed on data bus

 Instruction Description

T3 Data is written to memory or I/O

T4 WR = 1, bus is released

Timing Signals (Minimum Mode)

Signal Function

ALE (Address Latch Enable) High during T1 to latch address

RD Read control signal (low-active)

WR Write control signal (low-active)

DT/R Data Transmit/Receive

DEN Data Enable (enables data transceivers)

M/IO Selects between memory (1) and I/O (0)

INTA Interrupt Acknowledge

READY Wait state control (from memory/peripheral)

Maximum Mode Timing Overview

In maximum mode, control signals like RD, WR, ALE, etc., are generated by the 8288 Bus
Controller based on status signals (S0, S1, S2) from 8086.

8086 Pins Description

S0–S2 Status signals for 8288 to decode operation

RQ/GT Request/Grant pins for bus access in multiprocessor setups

LOCK Locks the bus for exclusive access

QS0–QS1 Queue status (for instruction prefetch info)

Sample Bus Cycle Duration

Assuming a 5 MHz clock:
  1 clock cycle (T-state) = 200 ns
 One read/write cycle (T1–T4) = 800 ns
 With 1 wait state: 1000 ns

MINIMUM MODE OF 8086 MICROPROCESSOR

If a system includes several interfaces then to increase current sourcing/sinking capacities it is

necessary to use drivers and receivers (transceiver) for data bus also. The Intel 8286 device is
used to implement the transceiver block shown in Fig. 10.2. The 8286 contains 16 tristate
elements, eight receivers, and eight drivers. Therefore two 8286s are required to service 16
data lines of 8086.
TIMMING DIAGRAM FOR MINIMUM MODE

1. When processor is ready to initiate the bus cycle, it applies a pulse to ALE during T1. Before
the falling edge of ALE, the address, BHE, M/IO, DEN and DT/R must be stable i.e. DEN =
high and DT/R = 0 for input or DT/R = 1 for output.
2. At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
3. During T2 the address signals are disabled and S3-S7 are available on AD16/S3-AD19/S6 and
BHE/S7. Also DEN is lowered to enable transceiver.
4. In case of input operation, RD is activated during T2 and AD0 to AD15 go in high impedance
preparing for input.
5. If memory or I/O interface can perform the transfer immeaiately; there are no wait states and
data is output on the bus during T3.
6. After the data is accepted by the processor, RD is raised high at the beginning of T4.
7. Upon detecting this transition during T4, the memory or I/O device will disable its data signals.
8. For an output operation, processor applies WR = 0 and then the data on the data bus during T2.
9. In T4, WR is raised high and data signals are disabled.
10. For either input or output operation, DEN is raised during T4 to disable the Also M/IO is set
according to the next transfer at this time or during next T1 state. Thus length of bus cycle in
8086 is four clock cycle. If the bus is to be inactive after completion of bus cycle, then the gap
between the successive cycles is filled by ideal state clock cycles.

When the memory or I/O device is not able to respond quickly during transfer, wait states
(Tw) are inserted between T3 and T4 by disabling the READY input of the 8086. The bus
activity during wait state is same as during T3.