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Design and Simulation of 8 to 3 Binary Encoder

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 Design and Simulation of 8 to 3 Binary Encoder
Yeasin Arafat1 Fahim Ahmed Sunny2
ID: 1802009 ID: 1802030
Department of Electrical and Electronic Engineering,
Department of Electrical and Electronic Engineering,
Chittagong University of Engineering and Technology
Chittagong University of Engineering and Technology
Chittagong, Bangladesh
Chittagong, Bangladesh 2
1 u1802030@[Link]
u1802009@[Link]

Abstract— Binary encoders play a crucial role in digital circuit (MSB) and E0 being the least significant bit (LSB), the
design by transforming multiple input lines into a compact subscript numbers reflect the bit locations.
binary representation. The primary objective of this study is to
efficiently encode eight input lines into a three-bit binary code
while ensuring minimal propagation delay and power
consumption. The design process involves the translation of the
truth table into a minimized Boolean expression.

Keywords— gpdk090, DRC, LVS, Layout, Schematic, I/O pad.

I. INTRODUCTION
A digital circuit known as an encoder transforms a collection
of binary inputs into a specific binary code. To determine
which particular input is active, the binary code, which
Fig. 1 Octal to Baniry Encoder
represents the position of the input, is employed [1]. In digital
systems, encoders are frequently employed to transform a
parallel set of inputs into a serial code. Truth table of Octal to Binary Encoder:
A combinational digital circuit known as an 8-to-3 binary
encoder converts an 8-bit binary input to a 3-bit binary output,
INPUT OUTPUT
with only one of the output lines asserted (set to 1) based on D D6 D5 D4 D3 D2 D1 D0 E2 E1 E0
the input value. The position of the most significant bit (MSB), 7
which is set to 1, in the input corresponds to the active output 0 0 0 0 0 0 0 1 0 0 0
line [2].
0 0 0 0 0 0 1 0 0 0 1
II. SYSTEM DESIGN OF 8 TO 3 BINARY ENCODER 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
• FUNCTIONAL ANALYSIS:
Understanding an 8-to-3 binary encoder's function, inputs, 0 0 0 1 0 0 0 0 1 0 0
outputs, and truth table is necessary for functional analysis. A 0 0 1 0 0 0 0 0 1 0 1
digital circuit known as an encoder transforms input data from 0 1 0 0 0 0 0 0 1 1 0
one format to another. The 8-to-3 binary encoder in this
situation converts an 8-bit input into a 3-bit output, enabling 1 0 0 0 0 0 0 0 1 1 1
you to express one of eight input states with less bits [3].

Input: The 8-to-3 binary encoder's 8-bit input is commonly • ARCHITECTURAL ANALYSIS:
represented by the symbol D[7:0]. The bit positions are Digital logic gates like AND gates and OR gates can be used
indicated by the subscript numerals, with D7 denoting the to construct the architecture of an 8-to-3 binary encoder. Let's
most significant bit (MSB) and D0 denoting the least step-by-step dissect the architectural analysis:
significant bit (LSB). Step 1: Enter The 8-bit binary input that the encoder receives
typically consists of 8 distinct signals for the letters D7, D6,
Output: The encoder has a 3-bit output, which is generally D5, D4, D3, D2, D1 and D0.
represented as E[2:0]. With E2 being the most significant bit Step 2: Priority encoding logic, which determines where the
most significant bit should be set to 1, is at the heart of the
encoder and creates the appropriate 3-bit output. The logic
behind priority encoding is as follows:
• Test each input bit (D7, D6, D5, D4, D3, D2, D1 and
D0) using multiple AND gates.
• Join the OR gates' inputs to the outputs of AND
gates.
• By combining the outputs of the AND gates, the OR
gates will choose which of the output lines (E2, E1,
or E0) will be active.

Logical expression for E2, E1, and E0.

E2 = D7 + D6 + D5 + D4 Fig. 3 Symbol creation of 4 input OR Gate

E1 = D7 + D6 + D3 + D2
E0 = D7 + D5 + D3 + D1
Step 3: Produce Three signals—E2, E1, and E0—represent
the active output line in the output, according to the logic used
for priority encoding. The other signals will all be set to 0, and
only one of these signals will be set to 1.
Step 4: Turn off the output lines. The non-active output lines
should be disabled by setting their outputs to 0 in order to
guarantee that only one output line is active at a time. The use
of additional logic gates, such as NOT gates, can accomplish
this.
State Diagram: Unfortunately, a state diagram cannot be
used in the construction of an 8 to 3 Binary Encoder circuit. A
state diagram is used to represent the behaviour of a system as
a set of states and transitions between those states. An encoder
is a combinational circuit, which means that its output is only
dependent on the values of the current input and is Fig. 4 Simulation Output of 4 input OR Gate
independent of any previous inputs or outputs. In light of this,
describing the behaviour of an encoder does not require the
use of a state diagram.

III. SCHEMATIC DESIGN

In this section, required schematic diagrams and symbols
to design an 8 to 3 binary encoder were designed. This
includes a 4 input or gate circuit.

Fig. 5 Gate level schematic design of 8 to 3 binary encoder

Fig. 2 Gate level schematic design of 4 input or gate

 Fig 6: Transistor Level Design of 8 to 3 binary encoder.

IV. SYMBOL
. The designed symbol from fig 6 is shown in figure 7 Fig. 9 Post Layout Simulation

To check the design transient analysis needed to be done

before and after layout design. At first, the environment was
created. The input output pin to be plotted was selected. After
giving input in the “stimuli” the output was plotted and
verified with the equations and truth table.

VI. LAYOUT DESIGN

In the design procedure after schematic comes layout
design. At first, layout of 4 input OR gate was designed. And
it’s DRC and LVS check was done to ensure the design
Fig. 7 Symbol creation of 8 to 3 Binary Encoder parameters.

V. SIMULATION RESULT

Fig 8 Pre-Simulation Output of 8 to 3 Binary Encoder Fig. 10 Cell Layout of 4 input OR Gate Transistor level Design
 Fig. 14 Parameter for DRC test

Fig. 11 Top Level Layout of 8 to 3 Binary Encoder

VII. DRC & LVS CHECK

The DRC and LVS test were done with Cadance. There
were some errors found after checking the DRC and LVS test.
By some modifications, the errors were solved, and the
Fig. 15 Encoder Layout with No DRC error
designed layout didn’t contain and error.

Fig 12: OR gate DRC check result.

Fig 13: LVS check result of OR gate

Fig. 16 Parameter for Checking LVS
 IX. PARASITIC EXTRACTION

Parasitic extraction was executed to find out the inbuild

resistors and capacitors in the design. For that below setup
was done.

Fig. 17 Run LVS

Fig. 20: Parameter for Assura Parasitic Extraction Run

Fig. 18 Schematic and Layout Match of Encoder circuit (LVS check)

VIII. COMPLETE CHIP LAYOUT WITH I/O PAD

Fig. 19 Complete Chip Layout With I/O Pad

Fig. 21 Parasitic Extraction
 Fig22: Assura RCX run

X. TAPE OUT

In case of tape out, in the Cadance CIW File → Export →

Stream was clicked, and a form was filled. After that, the Fig. 24 Tap-Out Log File
layout shown in Fig. 19 was translated and the tape out was
done.
XI. RESULT ANALYSIS AND DISCUSSION

The design and analysis of the 8-to-3 binary encoder were

conducted using the Cadence design tools, a suite of industry-
standard software for electronic design automation (EDA).
The utilization of Cadence tools allowed for an in-depth
exploration of the encoder's performance metrics, enabling a
comprehensive evaluation of its functionality and potential
applications.
Layout and Area Utilization: Cadence tools facilitate
layout design and optimization, ensuring efficient area
utilization on the chip. By generating layouts and performing
layout-versus-schematic (LVS) checks, the encoder's physical
footprint can be accurately assessed. The analysis confirms
that the layout adheres to design specifications and occupies a
reasonable amount of chip area.
Performance Trade-offs and Optimization: Cadence
tools provide insights into potential performance trade-offs
and opportunities for optimization. Through sensitivity
analysis and parameter sweeps, designers can identify design
choices that impact metrics like propagation delay, power
Fig. 23 Paramatic Setup for Tap-Out
consumption, and area. This enables informed decision-
making to achieve the desired trade-offs.
 XII. ADVANTAGES & DISADVANTAGES ACKNOWLEDGMENT
Advantages: All credits go to the Almighty, for his boundless grace in
Compact Representation: The primary advantage of a successful completion of this project. Then we like to
binary encoder is its ability to compactly represent a large gratitude to our honourable teacher Muhammad Mahmudul
number of input combinations into a smaller binary output. In Hasan Tareq sir. Assistant Professor, Department of Electrical
the case of an 8-to-3 binary encoder, it reduces eight input and Electronic Engineering, CUET, for his affectionate
lines to just three output bits, saving space and simplifying guidance, valuable suggestions and inspirations throughout
circuitry. this work made this project possible.
Speed and Propagation Delay: A well-designed binary
encoder can provide fast data processing due to its minimal
propagation delay. This is important in applications requiring References
rapid response times and high-speed operations. [1] “electronicshub,” binary-encoder, [Online]. Available:
Reduced Power Consumption: Binary encoders are often [Link].
designed to minimize transitions between states, which can
[2] [Online]. Available:
lead to reduced dynamic power consumption. This energy-
[Link]
efficient behaviour is advantageous in battery-operated
encoder.
devices and other low-power applications.
[3] “coa_prilims_solution,” [Online]. Available:
Disadvantages: [Link]
1. Limited Resolution: One notable limitation is the [Accessed 12 2013].
reduced resolution when encoding multiple inputs
into a smaller number of output bits. This can lead to
data loss or loss of information if fine distinctions
among input states are necessary.
2. Input Dependence: The functionality of a binary
encoder depends on the priority and logic of the input
signals. If the input patterns do not align with the
encoding scheme, it could lead to incorrect or
unexpected outputs.
3. Complex Design Process: Designing an efficient
binary encoder involves careful consideration of the
logic design, optimization techniques, and priority
schemes. This complexity can increase design time
and effort.

XIII. APPLICATIONS
The applications of 8 to 3 binary encoder are:
➢ Address Decoding
➢ Multiplexers
➢ Control Signal Generation
➢ Priority Encoding
➢ Arithmetic Logic Units (ALUs)
➢ Display Drivers
➢ Data Compression
➢ Embedded Systems

XIV. CONCLUSIONS
Creating an 8 to 3 Binary Encoder and its symbol was the goal
of this effort. We additionally examine the DRC, Tap-out and
LVS from ASSURA. We had to maintain the given criterion.
Nevertheless, we were able to create the desired circuit by
adhering to the criteria. Initial DRC problems were present,
but we were able to successfully resolve them, and eventually
the LVS tab revealed no mismatch between the schematic and
the layout.

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