Embedded System ET

Unit 2 Microcontroller Architecture

C.D.Pophale
Lecturer in Electronics & Telecommunication Government Polytechnic,
Pune
Harvard Vs Von Neumann

Feature Harvard Von Neumann

Memory type Separate code/data Unified code/data
Speed Higher (no bottleneck) Lower (shared bus)
Complexity More complex hardware Simpler design
Instruction/data fetch Can be parallel Sequential
Common in Microcontrollers, DSPs PCs, general CPUs
Hybrid Architectures
Modern processors (especially ARM) often use a modified Harvard architecture, where:
•Separate caches are used for instructions and data.
•The main memory may still be unified like in Von Neumann.
This allows improved performance without fully separating physical memory
 Difference between the RISC and CISC
Processors
Sr. No. RISC CISC

1 It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

It emphasizes on software to optimize It emphasizes on hardware to

2 the instruction set. optimize the
instruction set.
It requires multiple register sets to store the It requires a single register set to
3 instruction. store the instruction.

4 RISC has simple decoding of instruction. CISC has complex decoding of instruction.

5 Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
 Difference between the RISC and CISC
Processors
Sr. No. RISC CISC
It uses a limited number of instruction It uses a large number of instruction that requires
6 that requires less time to execute the more time to execute the instructions.
instructions.

It uses LOAD and STORE that are It uses LOAD and STORE instruction in the memory- to-
7 independent instructions in the register- to- memory interaction of a program.
register a program's interaction.

RISC has more transistors on memory CISC has transistors to store complex instructions.
8 registers.

9 The execution time of RISC is very short. The execution time of CISC is longer.
 Difference between the RISC and CISC
Processors
Sr. No. RISC CISC

10 It has fixed format instruction. It has variable format instruction.

The program written for RISC Program written for CISC architecture tends to
11 architecture needs to take more take less space in memory.
space in memory.

Example of RISC: ARM, PA-RISC, Examples of CISC: VAX, Motorola 68000

12 Power Architecture, Alpha, AVR, family, System/360, AMD and the Intel x86
ARC and the SPARC. CPUs.
• A microcontroller is a single Integrated Circuit (IC) which is
comparable to a little stand alone computer
• It is designed to perform the specific tasks of embedded
systems.
• A microcontroller contains processing unit and small amount of
memory (ROM, RAM etc.), few I/O ports for peripherals, timer
etc.
• AVR ,ARM,PIC comes under the family of micro-controller.
 AVR Micro-Controller

• AVR micro-controller is manufactured by Atmel corporation in the year

1996.
• It is based on RISC Instruction set Architecture (ISA) and also called as
Advanced Virtual RISC.
• AT90S8515 was the initial micro-controller belongs to AVR family.
• AVR micro-controller is most popular category of controller and it is
cheap.
• It is used in many robotic applications.
PIC Micro-Controller
• PIC stands for Peripheral Interface Controller.
• PIC micro-controller was developed by Microchip.
• This micro-controller is a very fast simple micro-controller in
implementation and performance point of view.
• This micro-controller is easy to program and also it easy to interface
with other peripherals.
 ARM micro-controller
• ARM micro-controller is Advanced RISC Machine which was introduced
by Acorn computer organization and is manufactured by the companies
Apple, Nvidia, Qualcomm, Motorola, ST Microelectronics, Samsung
Electronics, and TI etc.
• ARM processor belongs to the family of CPUs which are based on
Reduced Instruction Set Computer (RISC) and ARM microprocessor with
RAM, ROM and other peripherals in one single chip, we get an ARM micro-
controller.
• Advantages of ARM Microcontrollers
• High Performance: ARM microcontrollers are well known for their high
level processing performance and perfect for various demanding
applications.
• Energy Efficient: ARM devices and particularly those devices that
embrace the Cortex-M class are forged with an eye on delivering high
performance while consuming the least amount of power as possible.
• Rich Ecosystem: ARM has substantial market shares with massive support
from the industry hence enhancing the development process.
• LPC2148 is an example of ARM micro-controller.
• It is based on RISC Instruction set Architecture (ISA).
• It is cost sensitive and high performance devices and used in a wide
range of embedded application such as industrial instrument control
systems etc.
Disadvantages of ARM Microcontrollers
• Cost: ARM microcontrollers can be more expensive than PIC, especially
when advanced peripherals are involved.
• Complex Architecture: ARM architecture is more complex, which could
result in a steeper learning curve for beginners.
• Higher Power Consumption in Some Cases: While ARM is generally
efficient, higher-end ARM processors can consume more power
compared to low-end PIC microcontrollers in simple applications.
 8051 PIC AVR ARM

Bus width 8-bit for standard core 8/16/32-bit 8/32-bit 32-bit mostly also available
in 64-bit

Communication UART, USART,SPI,I2C PIC, UART, USART, LIN, CAN, UART, USART, SPI, I2C, (special UART, USART, LIN, I2C, SPI, CAN,
Protocols Ethernet, SPI, I2S purpose AVR support CAN, USB, Ethernet, I2S, DSP, SAI
USB, Ethernet) (serial audio interface), IrDA

Speed 12 Clock/instruction cycle 4 Clock/instruction cycle 1 clock/ instruction cycle 1 clock/ instruction cycle
Memory ROM, SRAM, FLASH SRAM, FLASH Flash, SRAM, EEPROM Flash, SDRAM, EEPROM
ISA CISC Some feature of RISC RISC RISC
Memory Harvard architecture Von Neumann architecture Modified Modified Harvard
Architecture architecture
Power Average Low Low Low
Consumption
Families 8051 variants PIC16,PIC17, PIC18, PIC24, PIC32 Tiny, Atmega, Xmega, special ARMv4,5,6,7 and series
purpose AVR

NXP, Atmel, Silicon Labs, Dallas, Apple, Nvidia, Qualcomm,

Manufacturer Cyprus, Infineon, etc. Microchip Average Atmel Samsung Electronics, and TI
etc.
Cost (as
compared to Very Low Average Average Low
features provide)
Popular Atmega8, 16, 32, Arduino LPC2148, ARM Cortex-M0 to
Microcontrollers AT89C51, P89v51, etc. PIC18fXX8, PIC16f88X, PIC32MXX Community ARM Cortex-M7, etc.
Feature AVR ARM PIC 8051

Mostly RISC (8-bit,

Architecture RISC (8-bit mostly) RISC (32-bit, 64-bit) CISC-like (8-bit)
some 16/32-bit)

Reduced (compact & Advanced RISC (e.g., Proprietary, varies by Complex, older
Instruction Set
fast) Cortex-M) series instruction set

Bus Width 8-bit,16 bit,32 bit 32-bit (typical),64 bit 8-bit, 16-bit, 32-bit 8-bit

Fast (1 instruction per Very fast (pipelining, Slower (many cycles

Execution Speed Slower in 8-bit series
cycle) high MHz) per instruction)
AVR Family Classification
Tiny Mega Special Purpose Classic
Atiny13 ATMega8 AT90CAN128 AT90S2313
Atiny24 ATMega16 AT90PWM216 AT90S2323

Atiny32 ATMega32 AT90USB1287 AT90S4433

Atiny64,Atiny85 ATMega64, ATMega1280

The AVR architecture was conceived by two students at the Norwegian Institute of Technology
(NTH),Alf-Egil Bogen and Vegard Wollan.
AVR General Architecture
AVR Program Memory and Data memory.
ROM is used to store the program.
• AVR has up to 8MB of program memory. It may vary from 1k to 256KB
depends on Family member.
• AVR are the first microcontrollers those are using on-chip Flash memory
for program storage.
Data Memory RAM and EEPROM
AVR has maximum of 64kbytes of data RAM.but all family members not
have that much RAM.
Data RAM divided into 3 types.
General purpose register,I/o memory and internal SRAM
All AVRs having 32 general purpose registers. But other vary from chip to
chip.
I/O PINS
• The AVR can have 3 to 86 I/O pins depends on number of pin in
package.
Eg.8 pin IC have 3 pin I/O pins.
100 pins IC have 86 I/O pins.
Peripherals
ADC (10 bit to 16 bit),6 TIMERs with watchdog timer ,USART.
Tiny AVR
• Internal 20 MHz oscillator
• Up to 32 KB of Flash memory
• Up to 2 10-bit ADCs
• 16-bit real-time clock and periodic interrupt timer
• Analog comparator with scalable reference input
• USART/SPI/dual-mode TWI
• 1.8V–5.5V operating voltage range
• –40˚ to 125˚C operating temperature range
2 KB to 32 KB Flash memory,1K-8KB Program memory.
8- to 24-pin packages.
The tinyAVR microcontrollers are well-suited for a wide range of
applications including industrial, consumer, appliances, automotive and
Internet of Things (IoT) sensor nodes.having less instructions .
 Mega AVR
Number Code Data RAM DATA EPROM I/O PINS ADC Timers Package
R0M

ATmega8 8k 1k 0.5k 23 8 3 TQFP32,PDIP28

ATmega16 16K 1K 0.5K 32 8 3 TQFP44,PDFIP40

ATMEGA32 32K 2K 1K 32 8 3 TQFP44,PDIP40

 Features of ATMega AVR
•8-bit RISC architecture
•High clock speed (up to 20 MHz)
•Large Flash memory (up to 256 KB)
•SRAM & EEPROM (up to 8 KB SRAM, 4 KB EEPROM)
•Rich set of peripherals:
•Multiple timers
•ADCs (Analog to Digital Converters)
•UART, SPI, I2C interfaces Applications:
•PWM channels •Arduino-based projects
•Home automation
•Up to 86 general-purpose I/O lines
•Consumer electronics
•In-System Programmable via SPI •Industrial control systems
•Low power consumption modes •Robotics and IoT devices

•ATmega64
•ATmega128
•ATmega2560
• Special Purpose AVR microcontrollers are a subcategory of AVR chips
designed to handle specific application domains rather than general-
purpose control tasks. These microcontrollers are optimized with built-in
peripherals, enhanced functions, or unique interfaces to suit specialized
needs.
• The Classic AVR family refers to the original and foundational AVR
microcontrollers introduced by Atmel (now Microchip). These chips are
simple, efficient, and ideal for basic embedded applications.
Applications

Family Best For

Classic AVR Simple legacy systems, basic learning
TinyAVR Low-cost, space-constrained applications
MegaAVR Arduino boards, robotics, automation
XMEGA High-speed, advanced embedded control

Special Purpose AVR Automotive (CAN), USB devices, secure systems, LCD
interfaces
ATMega 328
• 8-bit AVR RISC-based microcontroller
• Used in Arduino Uno and other embedded platforms
• High performance with low power consumption
• Program Memory: 32 KB
• SRAM: 2 KB
• EEPROM: 1 KB
• Operating Voltage: 1.8V to 5.5V
• Clock Speed: Up to 20 MHz
• 23 Programmable I/O lines
• Timers: 3 (Two 8-bit, One 16-bit)
• 6 PWM Channels
• 10-bit ADC (6 channels)
Communication Interfaces
• USART (Serial Communication)
• SPI (Serial Peripheral Interface)
• I2C (TWI – Two Wire Interface)
Pin Configuration
Pin No. Pin name Description Secondary Function
1 PC6 (RESET) Pin6 of PORTC Pin by default is used as RESET pin. PC6 can only be programmed as
I/O .
2 PD0 (RXD) Pin0 of PORTD RXD (Data Input Pin for USART)

USART Serial Communication Interface

[Can be used for programming]

3 PD1 (TXD) Pin1 of PORTD TXD (Data Output Pin for USART)
USART Serial Communication Interface
[Can be used for programming
INT2( External Interrupt 2 Input)
4 PD2 (INT0) Pin2 of PORTD External Interrupt source 0
Pin No. Pin name Description Secondary Function
5 Pin3 of PORTD/PD3 (INT1/OC2B) External Interrupt OC0A is the output pin that toggles,
s ource1/OC2B( PWM - clears, or sets based on the match
between the Timer/Counter0 (TCNT0)
Timer/Counter2 Output Compare and the OCR0A (Output Compare
Match B Output) Register A).
6 PD4 (XCK/T0) Pin4 of PORTD T0( Timer0 External Counter Input)
XCK ( USART External Clock I/O)
7 VCC Connected to positive voltage

8 GND Connected to ground

9 PB6 (XTAL1/TOSC1) Pin6 of PORTB XTAL1 (Chip Clock Oscillator pin 1 or

External clock input)
TOSC1 (Timer Oscillator pin 1)
10 PB7 (XTAL2/TOSC2) Pin7 of PORTB XTAL2 (Chip Clock Oscillator pin 2)
TOSC2 (Timer Oscillator pin 2)
Pin No. Pin name Description Secondary Function
11 PD5 Pin5 of PORTD T1(Timer1 External Counter Input)OC0B(PWM - Timer/Counter0
Output Compare Match B Output)
(T1/OC0B)

12 PD6 (AIN0/OC0A) Pin6 of PORTD AIN0(Analog Comparator Positive I/P)

OC0A(PWM - Timer/Counter0 Output Compare Match A
Output)
13 PD7 (AIN1) Pin7 of PORTD AIN1(Analog Comparator Negative I/P)

14 PB0 (ICP1/CLKO) Pin0 of PORTB ICP1(Timer/Counter1 Input Capture Pin)

CLKO (Divided System Clock. The divided system clock can be
output on the PB0 pin)
15 PB1 (OC1A) Pin1 of PORTB OC1A (Timer/Counter1 Output Compare Match A Output)
Pin No. Pin name Description Secondary Function
16 PB2 (SS/OC1B) Pin2 of PORTB SS (SPI Slave Select Input). This pin is low when controller acts as slave.
[Serial Peripheral Interface (SPI) for programming]
OC1B (Timer/Counter1 Output Compare Match B Output)
17 P B 3 Pin3 of PORTB MOSI (Master Output Slave Input). When controller acts as slave, the data is
(MOSI/OC2A) received by this pin. [Serial Peripheral Interface (SPI) for programming]
OC2 (Timer/Counter2 Output Compare Match Output)
18 PB4 (MISO) Pin4 of PORTB MISO (Master Input Slave Output). When controller acts as slave, the data is sent
to master by this controller through this pin.
[Serial Peripheral Interface (SPI) for programming]
19 PB5 (SCK) Pin5 of PORTB SCK (SPI Bus Serial Clock). This is the clock shared between this controller and
other system for accurate data transfer.
[Serial Peripheral Interface (SPI) for programming]
20 AVCC Power for Internal ADC Converter

21 AREF Analog Reference Pin for ADC

Pin No. Pin name Description Secondary Function

23 PC0 (ADC0) Pin0 of PORTC ADC0 (ADC Input Channel 0)

24 PC1 (ADC1) Pin1 of PORTC ADC1 (ADC Input Channel 1)

25 PC2 (ADC2) Pin2 of PORTC ADC2 (ADC Input Channel 2)

26 PC3 (ADC3) Pin3 of PORTC ADC3 (ADC Input Channel 3)

27 PC4 (ADC4/SDA) Pin4 of PORTC ADC4 (ADC Input Channel 4)

SDA (Two-wire Serial Bus Data Input/output Line)

28 PC5 (ADC5/SCL) Pin5 of PORTC ADC5 (ADC Input Channel 5)

SCL (Two-wire Serial Bus Clock Line)
Architecture Of ATMega 328p
 AVR CPU Core
• The main function of the CPU core is to ensure correct program execution.
The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.

• In order to maximize performance and parallelism, the AVR uses a harvard

architecture – with separate memories and buses for program and data.
Instructions in the program memory are executed with a single level
pipelining. While one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system
reprogrammable flash memory.
Block Diagram of the AVR Architecture
ALU – Arithmetic Logic Unit

• The high-performance AVR ALU operates in direct connection with all

the 32 general purpose working registers. Within a single clock cycle,
arithmetic operations between general purpose registers or between a
register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format
 Status Register
• The status register contains information about the result of the most
recently executed arithmetic instruction.
• This information can be used for altering program flow in order to
perform conditional operations.
• Note that the status register is updated after all ALU operations, as
specified in the instruction set reference.
.
SREG – AVR Status Register
1. General Purpose Registers (GPRs)
•32 General-Purpose Registers: R0 – R31
•Used by the AVR CPU for data manipulation.
•Can be accessed directly in assembly and C.
•Divided into:
•R0–R15: Direct use
•R16–R31: Used in most arithmetic and logic operations
 Power Management and Sleep Modes
• The ATmega328P microcontroller supports multiple power management
features that help reduce power consumption.
• ATmega328P supports 6 sleep modes to save power.
• SLEEP instruction is used to enter into sleep mode.
• To enter any of the six sleep modes, the SE bit in SMCR must be written to
logic one.
• The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode
(idle, ADC noise reduction, power down, power-save, standby, or extended
standby) will be activated by the SLEEP instruction.
• If a reset occurs during sleep mode, the MCU wakes up and executes from
the reset vector.
Sleep Mode Description Active Modules

Timers, USART, ADC, etc. SPI, USART,

analog comparator, ADC, 2-wire serial
interface, Timer/Counters, watchdog,
Idle CPU stopped; peripherals still run. and the interrupt system to continue
operating. This sleep mode basically
halts clkCPU and clkFLASH, while
allowing the other clocks to run.
When the SM2..0 bits are written to 001,
the SLEEP instruction makes the MCU
enter ADC noise reduction mode,
stopping the CPU but allowing the ADC,
the external interrupts, the 2-wire serial
ADC Noise Reduction Reduces noise during ADC conversions. interface address watch,
Timer/Counter2(1), and the watchdog
to continue operating (if enabled). This
sleep mode basically halts clkI/O,
clkCPU, and clkFLASH, while allowing
the other clocks to run.
• Power-down
• Most modules off; wakes on external interrupt or watchdog.
• Watchdog, external interrupts
• Power-save
• Like Power-down, but keeps asynchronous timer running.
• Timer2, external interrupts
• Standby
• Crystal oscillator running for faster wake-up.
• External interrupts, watchdog
• Extended Standby
• Power-save + oscillator running.
• Same as above
• Power Reduction Register The power reduction register (PRR), provides a
method to stop the clock to individual peripherals to reduce power
consumption.
• Waking up a module, which is done by clearing the bit in PRR, puts the
module in the same state as before shutdown.
• Module shutdown can be used in Idle mode and active mode to
significantly reduce the overall power consumption. In all other sleep
modes, the clock is already stopped
Configuring the Pin
• Each port pin consists of three register bits: DDxn, PORTxn, and PINxn
• PortB,Port D,Port C
MCU Control Register
Port c
• The DDxn bit in the DDRx register selects the direction of this pin.
• If DDxn is written logic one, Pxn is configured as an output pin.
• If DDxn is written logic zero, Pxn is configured as an input pin.
• If PORTxn is written logic one when the pin is configured as an input pin, the
pull-up resistor is activated.
• To switch the pull-up resistor off, PORTxn has to be written logic zero or the
pin has to be configured as an output pin.
• The port pins are tri-stated when reset condition becomes active, even if
no clocks are running.
DDxn Data Direction Bit (0 = Input, 1 = Output) in DDRx register

PORTxn Output value / pull-up control bit in PORTx register

Pull-up Disable bit in MCUCR register (1 = disable pull-ups

PUD globally)
 Program to read input data on Port B with Pull up enable
#include <avr/io.h> ; Set PORTB as input
LDI R16, 0x00
int main(void) { OUT DDRB, R16 ; DDRB = 0 → input
DDRB = 0x00; // Set PORTB as input
PORTB = 0xFF; // Enable pull-up resistors on all ; Enable pull-up resistors
PORTB pins LDI R16, 0xFF
OUT PORTB, R16 ; PORTB = 0xFF → pull-ups enabled
while (1) {
uint8_t data = PINB; // Read input from PORTB loop:
// Use 'data' as needed IN R17, PINB ; Read input from PORTB into R17
} RJMP loop ; Infinite loop
}
 Timers in ATMega 328p
Timer Registrers PWM pins Bit Width Type PWM Support Special Features

TCNT0, TCCR0A,
Timer TCCR0B(Control) D5 (OC0B), D6 8-bit General Purpose Fast PWM, Phase Used for millis()
0 OCR0A, OCR0B (OC0A) Correct in Arduino
TIMSK0, TIFR0

TCNT1H/L, TCCR1A, TCCR1B, D9 (OC1A), D10 Fast, Phase

(OC1B), Input Input Capture,
Timer1 TCCR1C, OCR1A/B, ICR1,
Capture on D8 16-bit Advanced Correct, Servo Control
TIMSK1, TIFR1 (ICP1)
Frequency PWM

TCNT2,
TCCR2A, TCCR2B D3 (OC2B), D11 Fast PWM, Phase Asynchronous
Timer2 OCR2A/B, ASSR (OC2A) 8-bit General Purpose Correct mode (RTC
support)
Basic Working Principle
1.Timer register (e.g., TCNT0) starts at 0.
2.Each clock tick increments the counter.
3.When the counter overflows or reaches a compare value, it can:
•Set a flag (software can check it)
•Trigger an interrupt
4.You can control how fast it counts using a prescaler.

Method Description
Polling Check flag in loop (e.g., TIFR)
Interrupt Timer automatically calls ISR when event
occurs
Mode Description
Normal Mode Timer counts up to max (0xFF or 0xFFFF), then overflows
CTC Mode Timer resets when it matches OCRn value
PWM Modes Timer generates PWM signal (used for motor/LED control)
Input Capture (Timer1) Captures counter value on external signal
FOC0A (Force Output Compare for Channel A) is a control bit used to
force an Output Compare Match event on the Timer/Counter0 without waiting for the timer to reach the OCR0A value
Modes of Operation :The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined
by the combination of the waveform generation mode (WGM02:0) and compare output mode (COM0x1:0) bits.There are 4
modes of operation.
1.Noraml Mode 2. CTC 3.Fast PWM 4.Phase correction PWM

1.Normal Mode: The simplest mode of operation is the normal mode (WGM02:0 = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF)
and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be set in the same timer
clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased
by software.

2.Clear Timer on Compare Match (CTC) Mode In clear timer on compare or CTC mode (WGM02:0 = 2), the OCR0A register is
used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0)
matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater
control of the compare match output frequency. It also simplifies the operation of counting external events. The timing
diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0) increases until a compare match occurs
between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.