Course Curriculum

Course Code: ES208 Credit Units L T P/S SW AS/DS FW No. of PSDA Total Credit Unit
Course Level UG 3 0 2 0 0 0 0 4
Course Title Digital Logic and Computer Architecture

Course
Description :

Course Objectives :

SN
Objectives
.
This course provides introduction to the basics of digital electronics and design of digital circuits with detailed computer architecture. Technical
1
foundations of computing platform and principles of digital design and computer architecture is covered in this course.

Pre-Requisites : General

SN. Course Code Course Name

Course Contents / Syllabus :

SN. Module Descriptors / Topics Weightage

Basic of logic gates and Universal gates, SOP and POS forms, K maps:2, 3 and 4 variable K Maps,
Digital Combinational Logic Modules and their applications, Decoders, encoders, multiplexers, de multiplexers, and their
1 25.00
electronics applications; Parity circuits and comparators; Arithmetic modules- adders, BCD adder, subtractors. Flip Flops: SR
Flip Flop, D Flip Flop, JK Flip Flop and T Flip Flop.
Basics of Computer Architecture: Von Neumann Model of Computing, ALU, Register Transfer Language, Bus and
Basic Computer Memory Transfers, Arithmetic Micro-operations, Logic Micro-operations, Shift Micro-operations, Arithmetic Logic
2 Organizations shift Unit, Instruction Codes, Computer Registers, Computer Instructions, Timing and Control, Instruction Cycle, 25.00
and Design Memory- Reference Instructions, Input-Output and Interrupt, Design of Accumulator Logic. Hardwired and
Microprogrammed control: Control Memory, Address Sequencing, Design of Control Unit
Introduction, General Register Organization, Instruction Formats, Instruction type, Addressing Modes, Data
Central
3 Transfer and Manipulation, Program Control, Reduced Instruction Set, Computer RISC and CISC Computer 20.00
Processing Unit
Arithmetic: Introduction, Multiplication Algorithms, Division Algorithms, Floating-Point Arithmetic Operations
Memory Organization: Memory Hierarchy, Main Memory: RAM and ROM Chips, Address Map, Associative
Memory Memory: Hardware Organization, Match Logic, Read. Operation and Write Operation. Cache Memory:
4 20.00
Organization Associative Mapping, Direct. Mapping, Set-Associative Mapping, Writing into Cache Initialization. Virtual Memory:
Address and Memory Space, Address Mapping.
Pipelining,
Vector Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline, RISC Pipeline, Vector Processing, Array
5 10.00
Processing and Processors. Multiprocessors: Characteristics of Multiprocessors, Interconnection Structure.
Multiprocessors

Course Learning Outcomes :

SN. Course Learning Outcomes

1 Design and use Digital components to create digital circuitry.
2 Learn to use operational basics of ALU and Bus transfers.
3 Explain how arithmetic operations are achieved with digital circuitry.
4 Design and use of different types of memory circuits.
5 Understand advanced concepts in computer architectures.

Pedagogy for Course Delivery :

SN. Pedagogy Methods

1 Classroom teaching using White board and Presentations.
2 Assignments and Tutorials for continuous assessment.

Theory /VAC / Architecture Assessment (L,T & Self Work): 75.00 Max : 100

Attendance+CE+EE : 5+35+60

SN. Type Component Name Marks

1 Attendance 5.00
2 End Term Examination (OMR) 60.00
3 Internal CLASS TEST 15.00
4 Internal VIVA VOCE 10.00
5 Internal INTEGRATED PROJECT 10.00

Lab/ Practical/ Studio/Arch. Studio/ Field Work Assessment : 25.00 Max : 100

Attendance+CE+EE : 5+35+60

SN. Type Component Name Marks

1 Attendance 5.00
2 External PRACTICAL 30.00
3 External VIVA VOCE 30.00
4 Internal PERFORMANCE 15.00
5 Internal PRACTICAL / LAB RECORDS 10.00
6 Internal VIVA VOCE 10.00

Lab/ Practical details, if applicable :

SN. Lab / Practical Details

1 Simulation using ORCAD
2 To design and simulate Half Adder and full adder circuit
3 To design and simulate half and full subtractor Circuit
4 To design and simulate priority encoder.
5 To design and simulate decoder.
6 To design and simulate the common bus using tri-state buffers and decoder
7 To design and simulate the common bus using multiplexers.
8 To design and simulate the logical part of a simple Arithmetic logical Unit
9 To design and simulate a 4-bit binary adder-subtractor circuit
10 To design and simulate one digit BCD Adder.

List of Professional skill development activities :

No.of PSDA : 0
SN. PSDA Point

Text & References :

SN. Type Title/Name Description ISBN/ URL

Harry & Jordan, Computer Systems Design
1 Book & Architecture, Edition 2000, Addison
Wesley, Delhi
Morris Mano, Computer System
2 Book Architecture, 3rd Edition – 1999, Prentice-
Hall of India Private Lim