HyperLynx SI & PI Complete Tutorial
Part 1: Introduction to HyperLynx
HyperLynx is a simulation and analysis tool developed by Mentor Graphics (Siemens EDA) for PCB
design. It is used for Signal Integrity (SI), Power Integrity (PI), Thermal Analysis, and EMI/EMC
compliance checking.
Signal Integrity ensures proper signal quality at high speeds by identifying reflections, crosstalk,
timing issues, and impedance mismatches. Power Integrity ensures clean, stable power delivery,
minimizing voltage drops, noise, and plane resonances.
The software supports multiple PCB layout formats and integrates component models (IBIS),
stackup configurations, and advanced simulation reports.
Part 2: Signal Integrity (SI) Simulation
Module 1: Stack-up Setup
Defining your PCB stack-up controls impedance, return paths, and crosstalk.
Steps:
- Open HyperLynx BoardSim > Setup > Layer Stack-up
- Define signal and plane layers, material Er values, trace widths, spacing, and target impedances.
- Save configuration and assign to net classes.
Module 2: Single-Ended Trace Simulation
Simulates reflections, delay, and ringing in individual traces.
Steps:
- Load PCB layout, select SI Analysis > Single Trace
- Choose nets, assign source/load models
- Run TDR and time domain analysis
- Observe reflections, delay, overshoot/undershoot
- Optional: Eye Diagram Analysis
Module 3: Differential Pair Simulation
Essential for high-speed pairs like USB and PCIe.
Steps:
- Define differential pairs in Setup > Differential Pairs
- Assign driver/load IBIS models
- Run time domain and eye diagram simulations
- Check skew and impedance control
- Optionally perform crosstalk analysis
Module 4: Crosstalk Analysis
Identify NEXT and FEXT on victim nets.
Steps:
- Select SI Analysis > Crosstalk
- Assign aggressor and victim nets
- Set models and rise/fall times
- Run simulation, observe crosstalk waveforms
- Mitigate by increasing spacing or using guard traces
Module 5: Timing and Delay Analysis
Verifies timing for parallel buses and critical nets.
Steps:
- Select SI Analysis > Timing Analysis
- Pick net groups
- Assign IBIS models
- Run propagation delay simulation
- Match delays through layout tuning
- Validate setup/hold windows against simulation results
Part 3: Power Integrity (PI) Simulation
Module A: DC Drop Analysis
Analyzes voltage drops across power planes.
Steps:
- Load PCB layout in BoardSim
- Select PI Analysis > DC Drop
- Define voltage sources and current sinks
- Run simulation and view voltage maps
- Identify excessive drops and optimize via/power plane design
