5 SV & UVM

PROTOCOLS
2 MAJOR PROJECTS
Hands on Training + Certificate
UART | I2C | APB | AHB | AXI
RISC V & DDR 5
th
Batch starting from Sept 20

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+91 91822 80927
 OFFLINE + ONLINE
ONLY WEEKENDS
Timings - Sat, Sun - 10am to 1pm
Duration - 10 weeks
Tool access, Interview preparation
Assignments, Mock Interviews
Placement support

Trainer - Prasanthi Chanda

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+91 91822 80927
Week 1 :
Introduction to Protocols in SOC & IP Level

Week 2 :
RTL Design & Verification UART Protocol

Week 3 :
I2C Protocol Verification using System Verilog

Week 4 :
AMBA APB Protocol APB4 2.0 Verification in SV

Week 5 :
AMBA AHB5 Design & Verification using UVM
AHB to APB Bridge RTL Design
Week 6 :
AMBA AXI5 VIP Development in UVM

Week 7 :
RISC V Processor Detailed explanation

Week 8 :
RTL Design & SV Verification of RISC V Pipeline Architecture

Week 9 :
DDR2 to DDR5 Project Explanation in Fresher level

Week 10 :
RTL design & Verification of DDR
Week 1 : Introduction to Protocols
Detailed Explanation of SOC | IP Level Protocols
Serial Communication Protocols, Interface Protocols
On chip & Off chip Protocols
Inter & Intra Communication Protocols
Serial & Parallel Communication Protocols
Simplex, Half duplex, full duplex Communication Protocols
System on Chip | IP Level Protocols
Peripheral Protocols
Interview Preparation Techniques

Week 2 : UART Protocol

Project 1- UART Protocol - RTL Design Using Verilog HDL
Theory
Introduction to UART Protocol- Features and
Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram
Implementation
Transmitter Design: FSM Implementation, Baud Rate
Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver
Testbench Creation and Simulation
Debugging and Waveform Analysis
Reports and documentation
Week 3 : I2C Protocol
Project - 2 I2C Protocol Implementation and Verification
Theory
I2C Protocol Overview: Features, Signals, and Modes
of Operation, Address recognition and clock
stretching.
Arbitration handling for multi-master systems.
Multi-Master and Multi-Slave Configurations.
Timing Diagram and Bit-Level Analysis
Implementation
RTL Design of I2C Controller
Writing Test Cases in SystemVerilog Testbench
Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

Week 4 : AMBA APB4 Protocol

Project - 3 AMBA APB Protocol Verification using
Systemverilog
Introduction to APB Protocol
APB Protocol Overview
Purpose of APB in low-power peripherals.
Signal and bus architecture.
Timing diagrams and key operations.
Features of APB
Simple interface with minimal control.
Read and Write operations.
Pipelining restrictions.
RTL Design for APB
APB Master and Slave Design
Signal interface (PADDR, PWDATA, PREADY, etc.).
Design of APB state machine.
Address decoding and data transfer logic.
RTL Code Development
APB protocol implementation using Verilog.
Coding examples for read/write transfers.
Design verification using simulation tools.
Simulation and Debugging
Testbench creation for APB RTL.
Waveform analysis for protocol behavior.

Verification of APB Protocol

SV Testbench Architecture
SV components specific to APB.
Sequence creation for read/write operations.
Assertions for APB
Timing checks for PREADY and PSLVERR.
Functional verification with assertions.
Coverage Analysis
Functional coverage for protocol features.
Code coverage metrics and optimization.
Reports and documentation
Week 5 : AMBA AHB5 Protocol
Project - 4 Introduction to AHB Protocol
AHB Protocol Overview
High-performance, pipelined bus system.
Burst transfers and arbitration mechanisms.
Signal descriptions and timing diagrams.
Features of AHB
Single clock-edge operation.
Multiple masters and slaves.
Burst and split transactions.
AHB Master and Slave Design
AHB signal architecture (HADDR, HWRITE, HRESP,
etc.).
State machine design for pipelined operations.
Address decoding and data transfer logic.
RTL Code Development
Implementation of master and slave interfaces.
Coding examples for burst and single transfers.
Simulation and Debugging
Testbench creation for AHB RTL design.
Timing analysis and debugging.
Week 5 : AMBA AHB5 Protocol
UVM Testbench Architecture
UVM environment for AHB verification.
Sequence generation for split and burst transfers.
Assertions for AHB
Timing assertions for arbitration and responses.
Data consistency and burst transaction checks.
Coverage Analysis
Functional coverage for split, retry, and burst
scenarios.
Metrics for arbitration and pipelining.

Week 6 : AMBA AXI5 Protocol

Project - 5 Introduction to AXI Protocol
AXI Protocol Overview
Advanced features of AXI (QoS, out-of-order
execution).
AXI channels (Write, Read, Address, Response).
Signal timing diagrams and concurrent transfers.
Features of AXI
Outstanding transactions and burst operations.
Separate address/control and data phases.
Low latency and high bandwidth.
Week 6 : AMBA AXI5 Protocol
Universal Verification Component (UVC) & VIP Development
UVM Testbench Architecture
UVM environment tailored for AXI.
Handling multiple AXI channels simultaneously.
Assertions for AXI
Checking AXI handshakes (AWVALID, WREADY,
etc.).
Timing checks for out-of-order execution.

Coverage Analysis
Functional coverage for burst types, QoS levels.
Coverage for out-of-order execution scenarios.

Key AXI5 Features in Our Test Plan

Fixed Burst
Incremented Burst
Wrap Burst
Unaligned Transfers
Outstanding Transactions
Out-of-Order Execution
Atomic Transactions
Response Handling
Week 7 : RISC V Processor Detailed Explanation
Introduction to RISC-V
History and significance of RISC-V
Open-source ISA advantages
RISC-V ISA Basics
Instruction formats (R, I, S, B, U, J types)
Registers and addressing modes
Core Concepts
ALU operations
Control unit design
Memory interface (load/store operations)
Pipeline Stages
IF, ID, EX, MEM, WB overview
Hands-on
Writing simple assembly programs
Implementing a single-cycle RISC-V processor in
Verilog

Week 8 : RTL Design & SV Verification of RISC V Pipeline

Architecture
Pipeline Design
5-stage pipeline implementation (IF, ID, EX, MEM, WB)
Handling hazards: structural, data, control
Forwarding and stalling techniques
RTL Implementation
Verilog coding for each stage
Integration into full pipeline
 Verification with SystemVerilog
Writing testbenches
Scoreboarding and assertions
Functional coverage of instructions
Project
Design & verify a pipelined RISC-V CPU
Debugging common pipeline issues

Week 9 : DDR2 to DDR5 Project Explanation (Fresher Level)

Introduction to DDR Memories
What is DDR? (Double Data Rate)
Differences between DDR2, DDR3, DDR4, DDR5
Applications in real-world systems
Architecture Overview
Memory controller design
Timing parameters (CAS latency, refresh cycles)
Data transfer mechanisms (Burst operations, prefetch)
Beginner-Friendly Project
Basic DDR read/write operation explanation
State machine for DDR controller (simplified version)
Example project: DDR3 read/write model
Comparison
Evolution from DDR2 → DDR5
Power efficiency, bandwidth improvements
Week 10 – RTL Design & Verification of DDR
RTL Design of DDR Controller
Command decoder
Bank management
Address mapping
Data path design
SystemVerilog Verification
Writing a DDR memory model
Testbench architecture
Assertions for timing checks
Coverage for read/write/refresh operations
Project
RTL design of simplified DDR controller
Verification using constrained random tests
Industry Insights
DDR in SoC design
Verification challenges in high-speed memory