Q11. Explain the Bus organization of 8085 Microprocessor.

[5
marks]

Definition:
- A bus is a set of shared lines used to transfer address, data, and
control signals between CPU, memory, and I/O.

Main buses in 8085:

- Address bus: 16 lines A15–A0. A15–A8 dedicated, AD7–AD0
multiplexed with data. Unidirectional.
- Data bus: 8 lines D7–D0 (time-shares AD7–AD0). Bidirectional.
- Control/status bus:
- ALE: latches low-order address (AD7–AD0).
- RD¯, WR¯: read/write strobes.
- IO/M¯: 0=memory, 1=I/O.
- Status S1, S0; READY (wait), HOLD/HLDA (DMA), RESET
IN/OUT.
- Interrupts: TRAP, RST7.5/6.5/5.5, INTR/INTA¯; Clock out;
serial SID/SOD.

Operation sequence:
- T1: PC address placed; ALE=1 to latch AD7–AD0 as A7–A0.
- T2–T3: AD7–AD0 carry data; RD¯/WR¯ control memory/I/O
transfer.
Tiny diagram (ASCII):
CPU(8085)
|-- A15–A8 --> Memory/I/O (address high)
|-- AD7–AD0 <-> Latch via ALE -> A7–A0 (then data bus)
|-- Control: ALE, RD¯, WR¯, IO/M¯, READY, HOLD/HLDA,
INTs

Key point:
- Multiplexing saves pins; ALE and an external latch separate
address and data.

------------------------------------------------------------
Q12. Explain the opcode fetch machine cycle for MVI A, 32H with
timing diagram. [5 marks]

Concepts:
- Machine cycle: group of T-states to perform a basic operation.
- MVI A, 32H is 2 bytes: opcode=3E(H), data=32(H).

Cycles:
1) Opcode Fetch (for 3E):
- T1: Put PC on bus; ALE=1 latches AD7–AD0.
- T2: IO/M¯=0, S1=1, S0=1; RD¯=0; memory places 3E on data
bus.
 - T3/T4: CPU samples data; PC←PC+1.

2) Memory Read (for immediate data 32H):

- T1: New address (PC) on bus; ALE=1.
- T2: IO/M¯=0; RD¯=0; memory outputs 32H.
- T3: CPU reads; PC←PC+1.

Timing sketch (ASCII):

Cycle: OFETCH(3E) MEM READ(32)
T: T1 T2 T3 T4 T1 T2 T3
ALE: _/‾\________________ _/‾\______
AD: Addr Data(3E) Addr Data(32)
A15–8: Addr stable Addr stable
RD¯: __ __
\__/ \__/

End state: A←32H; PC advanced by 2.

------------------------------------------------------------
Q13. Explain the 8085 instruction addressing modes with example.
[5 marks]

Definition:
- Addressing mode specifies how an instruction identifies its
operand(s).

Modes with examples:

- Immediate: operand in instruction. Example: MVI B, 2AH.
- Register: operand in register. Example: MOV A, C.
- Direct: 16-bit address in instruction. Example: LDA 2050H.
- Register indirect: address in register pair (HL/BC/DE). Example:
MOV A, M (A←[HL]).
- Implicit/Implied: operand implied. Example: CMA (complements
A).

Notes:
- LXI H, 2500H is immediate to register pair.
- STA addr, SHLD addr are direct stores.

------------------------------------------------------------
Q14. Explain the memory hierarchy with diagram. [5 marks]

Definition:
- Hierarchical organization of storage by speed, cost, and capacity to
optimize average access time.

Levels (top to bottom):

- CPU registers: fastest, bytes, most expensive/bit.
- Cache (L1/L2/L3, SRAM): very fast, small MBs.
- Main memory (DRAM): medium speed, GBs.
- Secondary storage (SSD/HDD): slow, non-volatile, TBs.
- Tertiary/backup (tape/optical/cloud): very slow, archival.

Principle:
- Locality (temporal, spatial) allows caches to give near-register
performance for active data.
- As we go down: speed↓, cost/bit↓, capacity↑, access time↑.

ASCII pyramid:
Registers
↓
L1/L2/L3 Cache
↓
Main Memory
↓
SSD/HDD
↓
Archive/Backup

------------------------------------------------------------
Q15. Explain the organization of Microprogrammed Control Unit.
[5 marks]

Definition:
- A control unit that generates control signals by reading
microinstructions stored in a control memory.

Organization/blocks:
- Control memory (ROM/WCS): stores microprograms.
- Control Address Register (CAR): address of current
microinstruction.
- Microinstruction Register (MIR): holds control word fields.
- Sequencer/Next-Address logic: sequential/branching/conditional
next address.
- Mapping ROM/PLA: maps opcode to start address of its micro-
routine.
- Control signal decoder/distributor: drives datapath signals
(register enables, ALU selects, RD¯/WR¯, etc.).
- Condition inputs: status flags, IR bits.

Working:
- Opcode fetched → mapping ROM → start address in CAR.
- Control memory outputs microinstruction → MIR asserts control
signals.
- Sequencer computes next address (CAR+1 or branch) until End-
of-routine bit; then return to fetch.

Pros/cons:
- Flexible and easy to modify; slower than hardwired CU.

------------------------------------------------------------
Q16. Define control word. Explain the procedure for generating
control word for specific operation. [5 marks]

Definition:
- Control word: a binary microinstruction whose bit-fields specify
which control signals are asserted during one micro-operation cycle.

Typical fields (example):

- Bus source selects, register load enables (LD_A, LD_B, LD_MAR,
LD_IR, LD_PC).
- ALU function select (ADD/SUB/AND/OR/INC/DEC/SHIFT).
- Memory/I-O strobes (RD¯, WR¯), PC increment enable, Flag
update enable.
- Next-address control bits (SEQUENCER:
NEXT/BRANCH/COND).

Procedure (example: execute “ADD B”):

1) Determine micro-operations: ALU←A+B; A←ALU; update
flags.
2) Choose sources: SEL_X=A, SEL_Y=B; set ALU F=ADD.
3) Set destination enables: LD_A=1; FLAG_EN=1; others=0.
4) If memory access needed, set RD¯/WR¯ appropriately (not for
ADD B).
5) Set sequencer bits to go to next micro-step or end.

Result:
- The encoded bits loaded into MIR constitute the control word for
that cycle.

------------------------------------------------------------
Q17. Define instruction pipeline. Explain the four-segment
instruction pipeline with example. [5 marks]

Definition:
- Pipelining executes multiple instructions in overlapped phases to
increase throughput.

Four segments:
- IF: Instruction Fetch.
- ID: Decode and operand fetch.
- EX: Execute/ALU or effective address.
- WB/MEM: Memory access if needed and write back results.
Timeline example:
Cycle: 1 2 3 4 5 6
I1: IF ID EX WB
I2: IF ID EX WB
I3: IF ID EX WB

Notes:
- After fill, one instruction completes per cycle (ideal).
- Hazards: structural, data (RAW), control (branches). Mitigations:
stalls, forwarding, prediction.

------------------------------------------------------------
Q18. Explain the functional block diagram of 8085 Microprocessor.
[10 marks]

Definition:
- 8085 is an 8-bit microprocessor with 16-bit address bus, 8-bit data
bus, accumulator-based ALU, interrupts, serial I/O, and
timing/control logic.

Neat labeled blocks and roles:

1) Register array:
- Accumulator (A).
 - Flag register (S, Z, AC, P, CY).
- General registers: B, C, D, E, H, L (form pairs BC, DE, HL).
- Program Counter (PC), Stack Pointer (SP).
- Temporary/Instruction registers (IR) and buffers.
2) ALU:
- 8-bit arithmetic/logic; updates flags; supports add, sub,
AND/OR/XOR, increment/decrement, compare, rotate, DAA, etc.
3) Address/Data buffers:
- Interface internal buses to external: A15–A8 (address), AD7–
AD0 (address/data).
4) Timing and Control Unit:
- Generates status/control: ALE, RD¯, WR¯, IO/M¯, S1, S0, CLK
OUT, READY, HOLD/HLDA.
- Manages machine cycles (opcode fetch, memory read/write, I/O,
interrupt acknowledge).
5) Interrupt control:
- TRAP (non-maskable), RST 7.5/6.5/5.5 (maskable vectored),
INTR with INTA¯.
- Enable/disable with EI/DI; priority TRAP>7.5>6.5>5.5>INTR.
6) Serial I/O:
- SID (Serial In Data), SOD (Serial Out Data) controlled by
SIM/RIM.
7) Clock and reset:
- Internal clock generator; RESET IN initializes PC=0000H,
interrupts disabled.
8) Incrementer/Address register:
- PC/SP increment/decrement; MAR/temporary address latches
for bus cycles.

ASCII sketch for clarity:

-------------------------------
| Timing & Control (ALE,RD¯,WR¯,|
| IO/M¯,S1,S0,CLK,READY,HOLD…) |
|-------------------------------|
| ALU <-> Accumulator (A) |
| | Flags (S Z AC P CY)
| B C D E H L (pairs BC,DE,HL)|
| PC SP IR Temp registers |
| Address & Data Buffers |
| Interrupt & Serial I/O |
-------------------------------
A15–A8: Address out; AD7–AD0: Addr/Data; Control lines to
system.

Working flow:
- Fetch: PC→bus, memory→opcode; IR loads; PC increments.
- Decode/Execute: Control unit sequences micro-ops; ALU operates;
results to A/regs; flags update.
- Memory/I-O transfers via RD¯/WR¯ with ALE-based
demultiplexing.

Marks distribution tip:

- 2 marks diagram, 6 marks block descriptions, 2 marks
working/notes.

------------------------------------------------------------
Q19. Explain the design and control logic of Accumulator. [10
marks]

Definition:
- Accumulator (A) is an 8-bit register used as a primary operand
and result register for ALU operations; most instructions implicitly
read/write A.

Internal design (conceptual datapath):

- 8-bit D flip-flop register with synchronous load.
- Input MUX:
- Selects from internal data bus, ALU output, or memory via bus.
- Output drivers:
- Tri-state to place A onto internal bus (AOE signal).
- Connection to ALU:
- A feeds one ALU operand directly; the other operand from
B/C/D/E/H/L/M/immediate.
- Flag register coupling:
- On writes to A from ALU, flags (S,Z,AC,P,CY) update.

Control signals and their roles:

- LD_A: load accumulator on clock edge (from selected input).
- OE_A (AOE): drive A onto internal bus.
- SEL_A_SRC[1:0]: select input source (00=bus, 01=ALU,
10=I/O/memory).
- ALU_F[2:0]: function code
(ADD,SUB,AND,OR,XOR,INC,DEC,DAA,Rotate).
- FLAG_EN: enable flag latch from ALU status.
- BUS_ARB: ensures no bus contention when A drives bus.

Micro-operation examples:
- MOV A, M:
- Memory read places [HL] on bus → LD_A=1; FLAG_EN=0.
- ADD B:
- OE_A=1 and OE_B=1 to ALU; ALU_F=ADD; LD_A=1;
FLAG_EN=1.
- CMA:
- ALU_F=NOT(A); LD_A=1; FLAG_EN unchanged (CMA does
not affect flags in 8085).
- RAL/RAR:
- Rotate through carry using ALU/rotator; LD_A=1; update CY.
Design notes:
- Accumulator must support both read and write in consecutive
cycles; hence tri-state drivers and synchronous load.
- Many instructions are implied with A (ANA r, ORA r, XRA r,
ADC r, SBB r), emphasizing centrality of accumulator.

Marks hint:
- 3 marks for structure, 5 for control signals with examples, 2 for
flags/notes.

------------------------------------------------------------
Q20. Explain the different data transfer and manipulation
instructions with example. [10 marks]

Structure answer: list by category, give function, flag effect, and one
example each.

A) Data Transfer Instructions (do not typically affect flags):

- MOV r1, r2 / MOV r, M / MOV M, r:
- Copy between registers/memory (via HL). Example: MOV D, A.
- MVI r, data8 / MVI M, data8:
- Immediate load. Example: MVI L, 40H.
- LXI rp, data16:
 - Load immediate to pair (BC/DE/HL/SP). Example: LXI H,
2050H.
- LDA addr16 / STA addr16:
- A←[addr] / [addr]←A. Example: LDA 3000H.
- LDAX rp / STAX rp:
- A←[BC/DE] / [BC/DE]←A. Example: STAX B.
- LHLD addr16 / SHLD addr16:
- Load/store HL direct from/to addr and addr+1.
- XCHG:
- Swap HL and DE.
- SPHL / PCHL / XTHL:
- SP←HL; PC←HL; exchange HL with top of stack.
- IN port / OUT port:
- Input from / output to I/O port (IO/M¯=1).
- PUSH rp / POP rp:
- Stack transfer of register pairs (PSW for A+Flags).

B) Data Manipulation – Arithmetic:

- ADD r/M / ADI data8:
- A←A+operand; flags: S,Z,AC,P,CY set.
- ADC r/M / ACI data8:
- A←A+operand+CY; flags set.
- SUB r/M / SUI data8:
 - A←A−operand; flags set.
- SBB r/M / SBI data8:
- A←A−operand−CY; flags set.
- INR r/M / DCR r/M:
- Increment/decrement 8-bit; affects S,Z,AC,P; CY unaffected.
- INX rp / DCX rp:
- Increment/decrement 16-bit pair; flags unaffected.
- DAA:
- Decimal adjust after BCD addition; flags updated.

C) Data Manipulation – Logical/Rotate/Compare:

- ANA/ANI: A←A AND operand; Z,S,P set; CY=0; AC=1.
- ORA/ORI: A←A OR operand; Z,S,P set; CY=0; AC=0.
- XRA/XRI: A←A XOR operand; Z,S,P set; CY=0; AC=0.
- CMA: A←NOT A; flags unaffected.
- CMP/CPI: Compare A with operand (A−op); A unchanged; flags
set as for subtraction.
- RLC/RRC: Rotate A left/right; CY receives bit7/bit0 respectively.
- RAL/RAR: Rotate through carry; CY participates.
- STC/CMC: Set/Complement carry.

Illustrative sequence example:

- Task: Add memory byte at 2050H to A and store result at 2060H.
 - LDA 2050H
- ADD B (if B preloaded) or ADI data
- STA 2060H

Marks split suggestion:

- 6–7 marks: well-organized categorized lists with flag effects and
examples.
- 3–4 marks: brief usage example or small sequence showing
practical use.

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