HEF4069UB

Hex unbuffered inverter

Rev. 11 — 5 September 2024 Product data sheet

1. General description
The HEF4069UB is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VDD.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Applications
• Oscillator

4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
HEF4069UBT -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1
body width 3.9 mm
HEF4069UBTT -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; SOT402-1
14 leads; body width 4.4 mm
Nexperia HEF4069UB
Hex unbuffered inverter

5. Functional diagram

1 2
1A 1Y

3 4
2A 2Y

5 6
3A 3Y

9 8
4A 4Y VDD

11 10
5A 5Y
A Y
13 12
6A 6Y
VSS
001aag152 001aag154

Fig. 1. Functional diagram Fig. 2. Schematic diagram (one inverter)

6. Pinning information

6.1. Pinning

1A 1 14 VDD

1Y 2 13 6A

2A 3 12 6Y

2Y 4 HEF4069UB 11 5A

3A 5 10 5Y

3Y 6 9 4A

VSS 7 8 4Y

001aag153

Fig. 3. Pin configuration

6.2. Pin description

Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 input
1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 output
VSS 7 ground (0 V)
VDD 14 supply voltage

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Product data sheet Rev. 11 — 5 September 2024 2 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage -0.5 +18 V
IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage -0.5 VDD + 0.5 V
IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current - 50 mA
Tstg storage temperature -65 +150 °C
Tamb ambient temperature -40 +125 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [1] - 500 mW
P power dissipation per output - 100 mW

[1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

8. Recommended operating conditions

Table 4. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air -40 - +125 °C

9. Static characteristics
Table 5. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min Max Min Max Min Max Min Max
VIH HIGH-level input |IO| < 1 μA 5V 4 - 4 - 4 - 4 - V
voltage 10 V 8 - 8 - 8 - 8 - V
15 V 12.5 - 12.5 - 12.5 - 12.5 - V
VIL LOW-level input |IO| < 1 μA 5V - 1 - 1 - 1 - 1 V
voltage 10 V - 2 - 2 - 2 - 2 V
15 V - 2.5 - 2.5 - 2.5 - 2.5 V
VOH HIGH-level |IO| < 1 μA 5V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage 10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level |IO| < 1 μA 5V - 0.05 - 0.05 - 0.05 - 0.05 V
output voltage 10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V

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Product data sheet Rev. 11 — 5 September 2024 3 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

Symbol Parameter Conditions VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min Max Min Max Min Max Min Max
IOH HIGH-level VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA
output current VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA
VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA
VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA
IOL LOW-level VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
II input leakage 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA
current
IDD supply current all valid input 5 V - 0.25 - 0.25 - 7.5 - 7.5 μA
combinations; 10 V - 0.5 - 0.5 - 15.0 - 15.0 μA
IO = 0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 μA
CI input digital inputs - - - 7.5 - - - - pF
capacitance

10. Dynamic characteristics

Table 6. Dynamic characteristics
Tamb = 25 °C; for waveforms see Fig. 4; for test circuit see Fig. 5.
Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit
tPHL HIGH to LOW nA to nY 5V 18 ns + (0.55 ns/pF)CL - 45 90 ns
propagation delay 10 V 9 ns + (0.23 ns/pF)CL - 20 40 ns
15 V 7 ns + (0.16 ns/pF)CL - 15 25 ns
tPLH LOW to HIGH nA to nY 5V 13 ns + (0.55 ns/pF)CL - 40 80 ns
propagation delay 10 V 9 ns + (0.23 ns/pF)CL - 20 40 ns
15 V 7 ns + (0.16 ns/pF)CL - 15 30 ns
tTHL HIGH to LOW output output nY 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns
transition time 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns
tTLH LOW to HIGH output output nY 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns
transition time 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns

[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

Table 7. Dynamic power dissipation

VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula Where
2
PD dynamic power dissipation 5 V PD = 600 × fi + Σ(fo × CL) × VDD (μW)
fi = input frequency in MHz;
10 V PD = 4000 × fi + Σ(fo × CL) × VDD (μW) fo = output frequency in MHz; 2

2
CL = output load capacitance in pF;
15 V PD = 22000 × fi + Σ(fo × CL) × VDD (μW) Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.

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Product data sheet Rev. 11 — 5 September 2024 4 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

10.1. Waveforms and test circuit

tr tf
VI
90 %
input VM
10 %
0V
tPHL tPLH
VOH
90 %
output VM
10 %
VOL
tTHL tTLH
001aag185

Measurement points: VM = 0.5VDD.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 4. Propagation delay and transition times

VDD

VI VO
G DUT

RT CL

001aag182

For test data refer to Table 8.

Definitions test circuit:
CL = load capacitance including jig and probe capacitance;
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 5. Test circuit for measuring switching times

Table 8. Test data

Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

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Product data sheet Rev. 11 — 5 September 2024 5 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

10.2. Transfer characteristics

001aag159 001aag160
5.0 500 10 10

VO ID VO ID
(V) (µA) (V) (mA)

2.5 250 5 5

(2) (1) (2) (2) (1) (2)

0 0 0 0
0 2.5 5.0 0 5 10
VI (V) VI (V)

a. VDD = 5 V; IO = 0 A b. VDD = 10 V; IO = 0 A
001aag161
20 20

VO ID
(V) (mA)

10 10

(2) (1) (2)

0 0
0 10 20
VI (V)

c. VDD = 15 V; IO = 0 A
(1) VO = output voltage.
(2) ID = drain current.
Fig. 6. Typical transfer characteristics

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Product data sheet Rev. 11 — 5 September 2024 6 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

11. Application information

Some examples of applications for HEF4069UB.
Fig. 7 shows an astable relaxation oscillator using two HEF4069UB inverters and two BAW62
diodes. The oscillation frequency is mainly determined by R1 × C1, provided R1 << R2 and
R2 × C2 << R1 × C1.
The function of R2 is to minimize the influence of the forward voltage across the protection diodes
on the frequency; C2 is a stray (parasitic) capacitance.
The period Tp is given by Tp = T1 + T2,
where:

VST = the signal threshold level of the inverter.

The period is fairly independent of VDD, VST and temperature. The duty factor, however, is
influenced by VST.

VDD
VDD
A
1/6 HEF4069UB 1/6 HEF4069UB
0V
D A B
VDD
C2 R2 R1 C1
B
VSS 0V
C
1.5VDD
VDD

C 0.5VDD
0V

- 0.5VDD

VDD
D 0.5VDD
0V

forward voltage
clamping diode 001aag162

Fig. 7. Astable relaxation oscillator

Fig. 8 shows a crystal oscillator for frequencies up to 10 MHz using two HEF4069UB inverters.
The second inverter amplifies the oscillator output voltage to a level sufficient to drive other Local
Oxidation CMOS (LOCMOS) circuits.

1 MΩ 22 pF 1 MΩ

2 MHz
2.2 kΩ

100 pF 22 pF
1/6 HEF4069UB 1/6 HEF4069UB

001aag155

The output inverter is used to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS
circuits.
Fig. 8. Crystal oscillator

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Product data sheet Rev. 11 — 5 September 2024 7 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

Fig. 9 and Fig. 10 show voltage gain and supply current. Fig. 11 shows the test set-up and an
example of an analog amplifier using one HEF4069UB.

001aag156 001aag157
75 20

IDD
gain (mA)
(VO/VI)
15
50
typ
typ
10

25
5

0 0
0 5 10 15 0 5 10 15
VDD (V) VDD (V)

Fig. 9. Typical voltage gain as a function of supply Fig. 10. Typical supply current as a function of supply
voltage voltage

330 kΩ

1/6 HEF4069UB
001aag158

Fig. 11. Test set-up

Fig. 12 shows typical forward transconductance. Fig. 13 shows the test set-up.

001aag164
10

gfs
(mA/V)
(1)
7.5

(2)

5.0

(3) Rbias = 560 kΩ

2.5 VDD

0.47 µF input output 100 µF

0
0 5 10 15 Vi A Io
VDD (V)
VSS
(1) Average +2σ;
001aag163
(2) Average;
(3) Average -2σ;
at VO is constant.
where ‘σ’ is the standard deviation.
fi = 1 kHz
Fig. 12. Typical forward transconductance as a function
of supply voltage at Tamb = 25 °C Fig. 13. Test set-up

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Product data sheet Rev. 11 — 5 September 2024 8 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

c
y HE v M A

14 8

A2
A3 A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 5 mm
scale

Dimensions (inch dimensions are derived from the original mm dimensions)

Unit A A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y θ

max 1.75 0.25 0.51 0.25 8.75 4.0 6.2 1.27 8°

mm nom 0.25 1.27 1.05 0.2 0.25 0.1
min 0.10 1.25 0.31 0.10 8.55 3.8 5.8 0.4 0°
max 0.069 0.010 0.020 0.010 0.344 0.16 0.244 0.05 8°
inches nom 0.01 0.05 0.041 0.008 0.01 0.004
min 0.004 0.049 0.012 0.004 0.337 0.15 0.228 0.016 0°
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. sot108-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
03-02-19
SOT108-1 MS-012
23-10-27

Fig. 14. Package outline SOT108-1 (SO14)

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Product data sheet Rev. 11 — 5 September 2024 9 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

A2 A3
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 5 mm

scale

Dimensions (mm are the original dimensions)

Unit A A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y θ

max 1.20 0.15 1.05 0.30 0.2 5.1 4.5 6.6 0.75 8°
mm nom 0.25 0.65 1 0.2 0.1 0.1
min 0.05 0.80 0.19 0.09 4.9 4.3 6.2 0.45 0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. sot402-1_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
03-02-18
SOT402-1 MO-153
23-10-27

Fig. 15. Package outline SOT402-1 (TSSOP14)

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Product data sheet Rev. 11 — 5 September 2024 10 / 13

Nexperia HEF4069UB
Hex unbuffered inverter

13. Abbreviations
Table 9. Abbreviations
Acronym Description
ANSI American National Standards Institute
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
ESDA ElectroStatic Discharge Association
HBM Human Body Model
JEDEC Joint Electron Device Engineering Council
LOCMOS Local Oxidation Complementary Metal-Oxide Semiconductor

14. Revision history

Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4069UB v.11 20240905 Product data sheet - HEF4069UB v10
Modifications: • Section 2: ESD specification updated according to the latest JEDEC standard.
• Fig. 14, Fig. 15: Aligned SO and TSSOP package outline drawings to JEDEC MS-012 and
MO-153
HEF4069UB v.10 20220210 Product data sheet - HEF4069UB v.9
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 and Section 2 updated.
• Table 3: Derating values for Ptot total power dissipation updated.
HEF4069UB v.9 20151216 Product data sheet - HEF4069UB v.8
Modifications: • Type number HEF4069UBP (SOT27-1) removed.
HEF4069UB v.8 20111116 Product data sheet - HEF4069UB v.7
Modifications: • Legal pages updated.
• Changes in "General description", "Features and benefits" and "Applications".
HEF4069UB v.7 20110511 Product data sheet - HEF4069UB v.6
HEF4069UB v.6 20091208 Product data sheet - HEF4069UB v.5
HEF4069UB v.5 20090723 Product data sheet - HEF4069UB v.4
HEF4069UB v.4 20080704 Product data sheet - HEF4069UB_CNV v.3
HEF4069UB_CNV v.3 19950101 Product specification - HEF4069UB_CNV v.2
HEF4069UB_CNV v.2 19950101 Product specification - -

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Product data sheet Rev. 11 — 5 September 2024 11 / 13

Nexperia HEF4069UB
Hex unbuffered inverter
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Nexperia HEF4069UB
Hex unbuffered inverter

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description............................................................. 2
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................3
10. Dynamic characteristics............................................ 4
10.1. Waveforms and test circuit........................................ 5
10.2. Transfer characteristics..............................................6
11. Application information..............................................7
12. Package outline.......................................................... 9
13. Abbreviations............................................................ 11
14. Revision history........................................................11
15. Legal information......................................................12

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Date of release: 5 September 2024

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Product data sheet Rev. 11 — 5 September 2024 13 / 13