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Course Name: VLSI PHYSICAL DESIGN
Assignment- Week 12
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 8 Total mark: 8 x 1.25 = 10
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QUESTION 1:
Which of the following statement(s) is/are true?
a. To reduce power dissipation in the pipelining approach, the function must be
implemented as a sequence of simpler pipeline stages, and at the same time the
clock frequency must be increased.
b. To reduce power dissipation in the pipelining approach, the function must be
implemented as a sequence of simpler pipeline stages, and at the same time the
operating voltage must be reduced.
c. None of these.
Correct Answer: b
Detailed Solution: The basic idea behind pipelining is to divide some computation into a
sequence of simpler sub-computations, where each of these is implemented as a separate pipeline
stage. To reduce the power dissipation, the operating voltage can be reduced. Option (a) is false
since increasing clock frequency will increase power dissipation. Option (b) is also false, since
the additional overheads of pipelining will lead to an increase in power dissipation.
The correct option is (b).
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QUESTION 2:
When a long bus is divided into several shorter buses, which of the following is/are true?
a. The overall power dissipation will decrease.
b. The overall power dissipation will increase.
c. There will be no impact on power dissipation.
Correct Answer: a
Detailed Solution: One of the common approaches to reduce power consumption in a bus-based
system is to segment a bus into several buses. In this method, the switched capacitance during
each bus access is significantly reduced. Hence, the correct option is (a).
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QUESTION 3:
In which of the following codes, consecutive count values differ in a single bit position?
a. Binary code
b. Binary coded decimal (BCD) code
c. Gray code
d. None of these.
Correct Answer: c
Detailed Solution: One of the characteristics of Gray code encoding is that the consecutive
count values differ in exactly one bit position.
Hence, the correct option is (c).
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QUESTION 4:
You are given a binary counter and a Gray code counter. Which of the two counters will result
in higher power dissipation as clock pulses are applied at the counter inputs?
a. Binary Counter
b. Gray code counter
c. The power dissipation will be the same
d. None of these.
Correct Answer: a
Detailed Solution: Gray code encoding results in reduced power consumption because only one
bit changes between consecutive count values, resulting in a reduction in dynamic power.
The correct option is (a).
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QUESTION 5:
For a 3-bit binary counter and a 3-bit Gray code counter, the total number of output bit
transitions in one cycle (i.e. 23 = 8 clocks) will be:
a. 16 and 8
b. 14 and 10
c. 256 and 8
d. None of these.
Correct Answer: d
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Detailed Solution: The count values for binary and Gray code encoding for 3-bits over 8 clock
cycles are given in the table below.
Clock cycle Binary Count Gray Code Count
000 000
1 001 001
2 010 011
3 011 010
4 100 110
5 101 111
6 110 101
7 111 100
8 000 000
The total number of output bit transitions for binary count will be 1+2+1+3+1+2+1+3 = 14.
Similarly, the total number of output bit transitions for Gray code count will be 1 x 8 = 8.
Hence, the correct option is (d).
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QUESTION 6:
Suppose we design a 6-bit Gray code counter with outputs F = (f5, f4, f3, f2, f1, f0). We feed F to
the inputs of a 6-input exclusive-OR gate X. If we apply 50 clock pulses to the counter, the
number of signal transitions (i.e., 0 to 1, or 1 to 0) at the output of X will be _________.
Correct Answer: 50
Detailed Solution: For the XOR gate, the output will change state whenever a single bit change
occurs in the input. For Gray code, single bit change occurs between successive count values.
Hence the number of output bit transitions will be 50, one for every clock. This will be
irrespective of the initial count value in the counter.
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QUESTION 7:
In a finite-state machine, clock gating can reduce power dissipation when:
a. The present state and next state are the same.
b. The present state and next state are different.
c. We use Gray code encoding for the states.
d. None of these.
Correct Answer: a
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Detailed Solution: When the present and next states are the same, it helps in implementing clock
gating to reduce power consumption in the circuit for the state generation logic.
The correct option is (a).
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QUESTION 8:
Suppose we have designed a circuit that operates at 100 MHz clock on a sequence of 7,500
input data items that are coming continuously. If we replace the circuit by ten identical copies
each of which operates at 10 MHz, then:
a. The overall throughput remains the same.
b. The power dissipation remains the same.
c. The power dissipation is reduced.
d. The power dissipation will increase.
e. None of these.
Correct Answer: a, b
Detailed Solution: When the clock frequency is reduced 10 times, the throughput reduces by 10
per pipeline. But since there are 10 pipelines, the overall throughput remains the same. The
power dissipation also does not change as each pipeline will dissipate 10 times less power.
The correct options are (a) and (b).
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