Electrical Engineering
Technical Interview
Questions/Review
Verilog Question 1
Q: What is the difference between a Verilog task and a Verilog function?
(Answer)
Verilog Question 2
Q: Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
(Answer)
Verilog Question 3
Q: Given the following snipet of Verilog code,
draw out the waveforms for "clk" and "a".
always @(clk) begin
a = 0;
#5 a = 1;
end
(Answer)
Verilog Question 4
Q: What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
(Answer)
Verilog Question 5
Q: Write the Verilog code to provide a divide-by-3 clock from the standard
clock.
(Answer)
Verilog Question 6
Q: What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;
(Answer)
Verilog Question 7
Q: Using the given, draw the waveforms for the following
versions of a (each version is separate, i.e. not in the same run):
reg clk;
reg a;
always #10 clk = ~clk;
(1) always @(clk) a = # 5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;
Now, change a to wire, and draw for:
(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;
(Answer)
Vera Question 1
Q: What is the difference between a Vera task and a Verilog task?
(Answer)
Vera Question 2
Q: What is the difference between running the following snipet of code
on Verilog vs Vera?
fork {
task_one();
#10;
task_one();
}
task task_one() {
cnt = 0;
for (i = 0; i < 50; i++) {
cnt++;
}
}
(Answer)
Programming Question 1
Q: Given $a = "5,-3,7,0,-5,12";
Write a program to find the lowest number in the string.
(Answer)
Programming Question 2
Q: Write the code to sort an array of integers.
(Answer)
Programming Question 3
Q: Write the code to find the factorial of an integer.
Use a recursive subroutine.
(Answer)
Programming Question 4
Q: In C, explain the difference between the & operator and
the * operator.
(Answer)
Programming Question 5
Q: Write a function to determine whether a string is a palindrome (same
forward as reverse, such as "radar" or "mom").
(Answer)
Programming Question 6
Q: Write a function to output a diamond shape according to the given (odd)
input.
Examples: Input is 5 Input is 7
* *
*** ***
***** *****
*** *******
* *****
***
(Answer)
General Question 1
Q: Given the following FIFO and rules, how deep does the FIFO need to be to
prevent underflowing or overflowing?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%
(Answer)
General Question 2
Q: Draw the state diagram to output a "1" for one cycle
if the sequence "0110" shows up (the leading 0s cannot be
used in more than one sequence).
(Answer)
General Question 3
Q: Explain the differences between "Direct Mapped", "Fully Associative",
and "Set Associative" caches.
(Answer)
General Question 4
Q: Design a four-input NAND gate using only two-input NAND gates.
(Answer)
General Question 5
Q: Draw the state diagram for a circuit that outputs a "1" if the aggregate
serial
binary input is divisible by 5. For instance, if the input stream is 1,
0, 1, we
output a "1" (since 101 is 5). If we then get a "0", the aggregate total
is 10, so
we output another "1" (and so on).
(Answer)
Answers
Verilog Answer 1
Q: What is the difference between a Verilog task and a Verilog function?
A:
The following rules distinguish tasks from functions:
A function shall execute in one simulation time unit;
a task can contain time-controlling statements.
A function cannot enable a task;
a task can enable other tasks or functions.
A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.
A function shall return a single value;
a task shall not return a value.
(Back)
Verilog Answer 2
Q: Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
A:
This is a tricky one! Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this sim cycle, so the "a =
0"
happens, and then the display shows a = 0. If we were to look at the value
of
a in the next sim cycle, it would show 1.
(Back)
Verilog Answer 3
Q: Given the following snipet of Verilog code,
draw out the waveforms for clk and a
always @(clk) begin
a = 0;
#5 a = 1;
end
A:
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
a ___________________________________________________________
This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___
a _______________________| |___________________| |_______
(Back)
Verilog Answer 4
Q: What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
A:
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units
hence.
a = #5 b; The value of b is calculated and stored in an internal temp
register.
After five time units, assign this stored value to a.
(Back)
Verilog Answer 6
Q: What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;
A:
The ? merges answers if the condition is "x", so for instance if foo =
1'bx, a = 'b10, and b = 'b11,
you'd get c = 'b1x.
On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.
(Back)
Verilog Answer 7
Q: Using the given, draw the waveforms for the following
versions of a (each version is separate, i.e. not in the same run):
reg clk;
reg a;
always #10 clk = ~clk;
(1) always @(clk) a = #5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;
Now, change a to wire, and draw for:
(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;
A:
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___ ___ ___ ___ ___ ___
(1)a ____| |___| |___| |___| |___| |___| |___| |_
___ ___ ___ ___ ___ ___ ___
(2)a ______| |___| |___| |___| |___| |___| |___|
(3)a __________________________________________________________
Since the #delay cancels future events when it activates, any delay
over the actual 1/2 period time of the clk flatlines...
With changing a to a wire and using assign, we
just accomplish the same thing...
10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___ ___ ___ ___ ___ ___
(4)a ____| |___| |___| |___| |___| |___| |___| |_
___ ___ ___ ___ ___ ___ ___
(5)a ______| |___| |___| |___| |___| |___| |___|
(6)a __________________________________________________________
(Back)
Vera Answer 1
Q: What is the difference between a Vera task and a Verilog task?
A:
(Back)
Vera Answer 2
Q: What is the difference between running the following snipet of code
on Verilog vs Vera?
fork {
task_one();
#10;
task_one();
}
task task_one() {
cnt = 0;
for (i = 0; i < 50; i++) {
cnt++;
}
}
A:
(Back)
Programming Answer 1
Q: Given $a = "5,-3,7,0,-5,12";
Write a program to find the lowest number in the string.
A:
// BEGIN PERL SNIPET
$a = "5,-5,-1,0,12,-3";
(@temp) = split (/,/, $a);
$lowest = $temp[0];
for ($i=0; $i<6; $i++) {
if ($temp[$i] < $lowest) { $lowest = $temp[$i]; }
}
print "Lowest value found was: $lowest\n";
// END PERL SNIPET
NOTE: You could also replace the for loop with this:
foreach $value (@temp) {
if ($value < $lowest) { $lowest = $value; }
}
(Back)
Programming Answer 2
Q: Write the code to sort an array of integers.
A:
/* BEGIN C SNIPET */
void bubblesort (int x[], int lim) {
int i, j, temp;
for (i = 0; i < lim; i++) {
for (j = 0; j < lim-1-i; j++) {
if (x[j] > x[j+1]) {
temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
} /* end if */
} /* end for j */
} /* end for i */
} /* end bubblesort */
/* END C SNIPET */
Some optimizations that can be made are that a single-element array does
not need to be sorted; therefore, the "for i" loop only needs to go from
0 to lim-1. Next, if at some point during the iterations, we go through
the entire array WITHOUT performing a swap, the complete array has been
sorted, and we do not need to continue. We can watch for this by adding
a variable to keep track of whether we have performed a swap on this
iteration.
(Back)
Programming Answer 3
Q: Write the code for finding the factorial of a passed integer.
Use a recursive subroutine.
A:
// BEGIN PERL SNIPET
sub factorial {
my $y = shift;
if ( $y > 1 ) {
return $y * &factorial( $y - 1 );
} else {
return 1;
}
}
// END PERL SNIPET
(Back)
Programming Answer 4
Q: In C, explain the difference between the & operator and
the * operator.
A:
& is the address operator, and it creates pointer values.
* is the indirection operator, and it dereferences pointers
to access the object pointed to.
Example:
In the following example, the pointer ip is assigned the
address of variable i (&i). After that assignment,
the expression *ip refers to the same object denoted by i:
int i, j, *ip;
ip = &i;
i = 22;
j = *ip; /* j now has the value 22 */
*ip = 17; /* i now has the value 17 */
(Back)
Programming Answer 5
Q: Write a function to determine whether a string is a palindrome (same
forward as reverse, such as "radar" or "mom").
A:
/* BEGIN C SNIPET */
#include <string.h>
void is_palindrome ( char *in_str ) {
char *tmp_str;
int i, length;
length = strlen ( *in_str );
for ( i = 0; i < length; i++ ) {
*tmp_str[length-i-1] = *in_str[i];
}
if ( 0 == strcmp ( *tmp_str, *in_str ) ) printf ("String is a
palindrome");
else printf ("String is not a palindrome");
}
/* END C SNIPET */
(Back)
Programming Answer 6
Q: Write a function to output a diamond shape according to the given (odd)
input.
Examples: Input is 5 Input is 7
* *
*** ***
***** *****
*** *******
* *****
***
A:
### BEGIN PERL SNIPET ###
for ($i = 1; $i <= (($input * 2) - 1); $i += 2) {
if ($i <= $input) {
$stars = $i;
$spaces = ($input - $stars) / 2;
while ($spaces--) { print " "; }
while ($stars--) { print "*"; }
} else {
$spaces = ($i - $input) / 2;
$stars = $input - ($spaces * 2);
while ($spaces--) { print " "; }
while ($stars--) { print "*"; }
}
print "\n";
}
### END PERL SNIPET ###
(Back)
General Answer 1
Q: Given the following FIFO and rules, how deep does the FIFO need to be to
prevent underflowing or overflowing?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%
A:
Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 100 = 4000ns, but we only output for
1000ns,
due to (3), so 3000ns of the enable we are doing no output work.
Therefore, FIFO size = 3000ns/40ns = 75 entries.
(Back)
General Answer 2
Q: Draw the state diagram to output a "1" for one cycle
if the sequence "0110" shows up (the leading 0s cannot be
used in more than one sequence).
A:
(Back)
General Answer 3
Q: Explain the differences between "Direct Mapped", "Fully Associative",
and "Set Associative" caches.
A:
If each block has only one place it can appear in the cache, the cache
is said to be direct mapped. The mapping is usually (block-frame address)
modulo (number of blocks in cache).
If a block can be placed anywhere in the cache, the cache is said to be
fully associative.
If a block can be placed in a restricted set of places in the cache, the
cache
is said to be set associative. A set is a group of two or more
blocks in the cache. A block is first mapped onto a set, and then the
block
can be placed anywhere within the set. The set is usually chosen by bit
selection; that is, (block-frame address) modulo (number of sets in cache).
If there are n blocks in a set, the cache placement is
called n-way set associative.
(Back)
General Answer 4
Q: Design a four-input NAND gate using only two-input NAND gates.
A:
Basically, you can tie the inputs of a NAND gate together to get an
inverter, so...
(Back)
General Answer 5
Q: Draw the state diagram for a circuit that outputs a "1" if the aggregate
serial
binary input is divisible by 5. For instance, if the input stream is 1,
0, 1, we
output a "1" (since 101 is 5). If we then get a "0", the aggregate total
is 10, so
we output another "1" (and so on).
A:
We don't need to keep track of the entire string of numbers - if something
is divisible by 5, it doesn't matter if it's 250 or 0, so we can just reset
to 0.
So we really only need to keep track of "0" through
(Back)
Q. Design a memory system as shown in diagram below.
Note: Only 2000 data entries will be used at a given time. Entries should be
programmable by external CPU.
Q. Create "AND" gate using a 2:1 multiplexer. (Create all other gates too.)
Q. Design XOR gate using just NAND gates.
Q. Design a "Stackable First One" finder.
Design a small unit which processes just 1 bit. Design in such a way that it can be
stacked to accept make input of any length.
Q Micro architect DMA controller block for given specifications
Note:
- Overall performance should be almost same as performance of Encryption
Engine which is 1Gbps.
Q. Design Gray counter to count 6.
Q. Design a block to generate output according to the following timing diagram.
Q. Design a module as shown in following block diagram.
Note: channel_id is 11 bits wide to accomodate 2K entries in 2K deep SRAM.
operation is 1 bit wide.
operation = 00 means write to current location.
operation = 01 means add 1 to existing data
operation = 10 means subtract 1 from existing data in SRAM.
Do not optimize based on operation as in future operations bits can change.
Design such that you can support 1 operation every clock.
Q. Design a hardware to implement following equations without using multipliers or dividers.
out = 7x + 8y;
out = .78x + .17y;
Old Questions
Q. Create 4 bit multiplier using a ROM and what will be the size of the ROM. How can you realize it
when the outputs are specified.
Q. How can you swap 2 integers a and b, without using a 3rd variable
Q. Which one is preferred? 1's complement or 2's complement and why?
Q. Which one is preferred in FSM design? Mealy or Moore? Why?
Q. Which one is preferred in design entry? RTL coding or Schematic? Why?
Q. Design a 2 input OR gate using a 2:1 mux.
Q. Design a 2 input AND gate using a 2 input XOR gate.
Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is
asserted high when this register holds a value which is divisible by 5.
For example:
Input Sequence Value Output
1 1 1 0
0 10 2 0
1 101 5 1
0 1010 10 1
1 10101 21 0
(Hint: Use a FSM to create this)
Q. Design a block which has 3 inputs as followed.
1. system clock of pretty high freq
2. asynch clock input P
3. asynch clock input Q
P and Q clocks have 50% duty cycle each. Their frequencies are close enough and they have phase
difference. Design the block to generate these outputs.
1. PeqQ : goes high if periods of P and Q are same
2. PleQ : goes high if P's period is less than that of Q.
3. PgrQ : goes high if P's period is greater than that of Q.
Q. What's the difference between a latch and a flip-flop? Write Verilog RTL code for each. (This is one
of the most common questions but still some EE's don't know how to explain it correctly!)
Q. Design a black box whose input clock and output relationship as shown in diagram.
__ __ __ __ __ __ __ __ __
clk __| |__| |__| |__| |__| |__| |__| |__| |__| |__
__ __ __ __ __
Output __| |________| |________| |________| |________| |__
Q. Design a digital circuit to delay the negative edge of the input
signal by 2 clock cycles.
______________________
input ________| |_____________
_ _ _ _ _ _ _ _ _ _ _ _ _
clock _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
___________________________
output _________| |___________
Q. Design a Pattern matching block
- Output is asserted if pattern "101" is detected in last 4 inputs.
- How will you modify this design if it is required to detect same "101" pattern anywhere in last
8 samples?
Questions:
Q.
The digital circuit is shown with logic delay (dly3) and two clock buffer delays
(dly1, dly2).
- How will you fix setup timing violations occurring at pin B?
- How will you fix hold violations occurring at pin B?
(Hint: Change the values of three delays to get desired effect)
Q.
Sender sends data at the rate of 80 words / 100 clocks
Receiver can consume at the rate of 8 words / 10 clocks
Calculate the depth of FIFO so that no data is dropped.
Assumptions: There is no feedback or handshake mechanism. Occurrence of data
in that time period is guaranteed but exact place in those clock cycles is
indeterminate.
Optical sensors A and B are positioned at 90 degrees to each other as shown in
Figure. Half od the disc is white and remaining is black. When black portion is
under sensor it generates logic 0 and logic 1 when white portion is under sensor.
Design Direction finder block using digital components (flip flops and gates) to
indicate speed. Logic 0 for clockwise and Logic 1 for counter clockwise.
Will this design work satisfactorily?
Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns.
After reset A = 0, B = 1
Q. Design a 4:1 mux in Verilog.
Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
What are the advantages / disadvantages of each coding style shown above?
How Synthesis tool will give result for above codes?
What happens if default statement is removed in case statement?
What happens if combination 11 and default statement is removed? (Hint Latch inference)
(Comments : Though this questions looks simple and out of text books, the answers to
supporting questions can come only after some experience / experimentation.)
Q. Design a FSM (Finite State Machine) to detect a sequence 10110.
Have a good approach to solve the design problem.
Know the difference between Mealy, Moore, 1-Hot type of state encoding.
Each state should have output transitions for all combinations of inputs.
All states make transition to appropriate states and not to default if sequence is broken. e.g.
S3 makes transition to S2 in example shown.
Take help of FSM block diagram to write Verilog code.
Q. One more sequence detector:
Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0 as shown in timing diagram.
And yes, you have to design this FSM using not more than 4 states!!
Q. Design a state machine to divide the clock by 3/2.
(Hint: 2 FSMs working on posedge and negedge)
Q. Draw timing diagrams for following circuit.
What is the maximum frequency at which this circuit can operate?
What is the minimum width of input pulse and position?
Problem can be given interesting twist by specifying all delays in min and max types.
Q. Design a Digital Peak Detector in Verilog.
Q. Design a RZ (return to zero )circuit. Design a clock to pulse circuit in Verilog / hardware gates.
Q. Miscellaneous Basic Verilog Questions:
What is the difference between Behavior modeling and RTL modeling?
What is the benefit of using Behavior modeling style over RTL modeling?
What is the difference between blocking assignments and non-blocking assignments ?
How do you implement the bi-directional ports in Verilog HDL
How to model inertial and transport delay using Verilog?
How to synchronize control signals and data between two different clock domains?
