Unit I: Processing Unit

By:
Ms. Ashvini D. Tarar

Department of Computer Science and

Engineering

S. B. Jain Institute of Technology, Management and Research,

Nagpur
 Internal organization of a processor

 Recall that a processor has several registers/building blocks:

 Memory address register (MAR)
 Memory data register (MDR)
 Program Counter (PC)
 Instruction Register (IR)
 General purpose registers R0 - R(n-1)
 Arithmetic and logic unit (ALU)
 Control unit.
 How are these units organized and how do they
communicate with each other?

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 Internal organization of a processor
Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Constant 4 R0

Select
MUX

Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry-in
XOR TEMP

Z
 Single bus
organization
 Single bus organization:
 ALU, control unit and all the registers are connected via a
single common bus.
 Bus is internal to the processor and should not be confused
with the external bus that connects the processor to the
memory and I/O devices.
 Data lines of the external memory bus are connected
to the internal processor bus via MDR.
 Register MDR has two inputs and two outputs.
 Data may be loaded to (from) MDR from (to) internal
processor bus or external memory bus.
 Address lines of the external memory bus are
connected to the internal processor bus via MAR.
 MAR receives input from the internal processor bus.
 MAR provides output to external memory bus.

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 Single bus organization
(contd..)
 Instruction decoder and control logic block, or control
unit issues signals to control the operation of all units
inside the processor and for interacting with the
memory bus.
 Control signals depend on the instruction loaded
in the Instruction Register (IR)
 Outputs from the control logic block are connected to:
 Control lines of the memory bus.
 ALU, to determine which operation is to be
performed.
 Select input of the multiplexer MUX to select
between Register Y and constant 4.
 Control lines of the registers, to select the

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 Single bus organization
(contd..)
 Registers Y, Z, and TEMP:
 Used by the processor for temporary storage during
execution of some instructions.
 Note that Registers R0 to R(n-1) are used to store
data generated by one instruction for later use by
another instruction.
 Data is stored in R0 through R(n-1) after the execution
of an instruction.
 Multiplexer MUX selects either the output of register Y
or a constant 4, depending upon the control input
Select.
 Constant 4 is used to increment the value of the PC.

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 Registers and the
bus
bus line 0
bus line 1

bus line m-1 (e.g., 31)

bit 0

register

bit m-1 clock

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 Registers and the bus
(contd..)
 A bus may be viewed as a collection of parallel wires.
 Buses have no memory:
 They are just a collection of wires.
 When data is on the bus, all registers can “see” that
data at their inputs.
 A register may place its contents onto the bus.

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 Registers and the bus
(contd..)
 At any one time, only one register may output its
contents to the bus:
 Which register outputs its content to the bus is
determined by the control signal issued by the control
logic.
 Control signal depends on the instruction loaded
in the instruction register.

 Which registers load data from the bus is determined by
the control signal issued by the control logic.
 Registers are clocked (sequential) entities (unlike ALU
which is purely combinatorial).

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 Riin
Each register Ri has two control signals,
Riin and Riout.
Ri
If Riin=1, the data from the bus is loaded
into the register.
If Riout=1, the data from the register is
Riout loaded onto the bus.
The same holds for registers Y and Z as
Yi well.
n

Constant 4

Select
MUX

A B

ALU

Zin

Zout
 Registers and the bus
(contd..)
Bus

D Q
1
Riout
Q
Clock
Riin

•Each bit in a register may be implemented by an edge-triggered D flip flop.

•Two input multiplexer is used to select the data applied to the input of
an edge triggered flip-flop.
•Q output of the flip-flop is connected to the bus via a tri-state gate.

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Registers and the bus
(contd..)
Bus

D Q
1
Riout
Q
Clock
Riin

Riin = 1:
Multiplexer selects the data on the bus.
Data is loaded into the flip-flop at the rising edge of the clock.
Riin = 0:
Multiplexer feeds back the value currently stored in the flip-flop.
Q output represents the value currently stored in the flip-flop.

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Registers and the bus
(contd..)
Bus

D Q
1
Riout
Q
Clock
Riin

Riout = 1:
Tri-state gate loads the value of the flip-flop onto the bus.
Data is loaded onto the bus at the rising edge of the clock.
Riout = 0:
Gate’s output is in high-impedance (electrically disconnected)
state.
Corresponds to open-circuit state.
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 Registers and the bus
(contd..)
Operation of a tri-state gate
•A tri-state gate can enter one of three output states.
- its output can be in a logic low state (L).
- its output can be in a logic high state (H).
- its output can be effectively an open-circuit (high impedance)
•When a tri-state gate is connected to a bus in high-impedance state, its outputs
are effectively disconnected from the bus.
Riout = 1, output is: Riout = 0:
Logic low, if Q = 0 High impedance
Logic high, if Q = Open circuit condition
1 Bus
Bus

0 0 Riin
D Q
1 1
Clock Q
Riin

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Registers and the bus
(contd..) D Q Clock Q

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Registers and the bus
(contd..)
Operation of an edge-triggered flip-flop

single processor clock period

Low-to-High transition

•Data is loaded from the register to the bus (or to the register from the
bus) at the rising edge of the clock.
•Data is loaded at the L-H transition of the clock.

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 Registers and the bus
(contd..)
 Data transfers and operations take place within time
periods defined by the processor clock.
 Time period is known as the clock cycle.
 At the beginning of the clock cycle, the control signals
that govern a particular transfer are asserted.
 For e.g., if the data are to be transferred from register R0
to the bus, then R0out is set to 1.
 Edge-triggered flip-flop operation explained earlier
used only the rising edge of the clock for data
transfer.
 Other schemes are possible, for example, data transfers
may use rising and falling edges of the clock.
 When edge-triggered flip-flops are not used, two or
more clock signals may be needed to guarantee proper
transfer of data. This is known as multiphase clocking.

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 Simple register transfer
example
Transfer the contents of register R3 to register R4

Clock period

1 2 3

1. Control signals R3out and R4in become 1. They stay valid until the end of
the clock cycle.
2. After a small delay, the contents of R3 are placed onto the bus. The
contents of R3 stay onto the bus until the end of the clock cycle.
3. At the end of the clock cycle, the data onto the bus is loaded into R4. R3out
and R4in become 0.

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 Loading multiple registers from the
bus
Transfer the contents of register R3 to register R4, R5

Clock period

1 2 3

1. Control signals R3out, R4in and R5in become 1. They stay valid until the end of
the clock cycle.
2. After a small delay, the contents of R3 are placed onto the bus. The
contents of R3 stay onto the bus until the end of the clock cycle.
3. At the end of the clock cycle, the data onto the bus is loaded into R4. and R5.
R3out, R4in and R5in become 0.

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 Loading multiple registers from the (contd..
bus )
 It is possible to load multiple registers simultaneously
from the bus.
 For e.g., transfer the contents of register R3 to registers
R4 and R7 simultaneously.
 The number of registers that can be simultaneously
loaded depends on:
 Drive capability (fan-out)
 Noise.
 Note that this is an electrical issue, not a logical issue.
 Distinguish this from multiple registers loading the bus:
 For e.g. load the contents of registers R3 and R4 onto the
bus simultaneously.
 Logically inconsistent event.
 Physically dangerous event.

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 Arithmetic Logic Unit
(ALU)
 ALU is a purely combinatorial
device:
 It has no memory or internal storage.
 It has 2 input vectors:
 These may be called the A- and B-vector or the R- and S-vector
 The inputs are as wide as the registers/system bus (e.g.,
16, 32 bits)
 It has 1 output vector
 Usually denoted F

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Arithmetic Logic Unit (ALU)
(contd..)
Sample functions performed by the ALU
• F = A+B F = A+B+1
• F = A-B F = A-B-1
• F = A and B F = A or B
• F = not A F = not B
• F = not A + 1 F = not B + 1
• F = (not A) and B F = A and (not B)
• F = A xor B F = not (A xor B)
•F=A F=B

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Arithmetic Logic Unit (ALU)
(contd..)

ALU is basically a black-box

A, B Inputs purely combinatorial logic(AND/OR/

NOT/NAND/NOR etc) inside the
ALU
Add --no registers
A B
ALU Sub
control ALU
lines
Carry in
XOR

Output F

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 Arithmetic and Logic Unit (ALU)
(contd..)
ALU connections to the bus

•ALU must have only one input connection

from the bus.
Y
•The other input must be stored in a
Constant 4 holding register called Y register.
Select •A multiplexer selects among register Y and
MUX
4 depending upon select line.
•One operand of a two-operand instruction must be

Control
A B placed into the Y register before the other operand
lines ALU must be placed onto the bus.

Carry-in

Processor bus

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 Arithmetic and Logic Unit (ALU)
(contd..)
ALU connections to the bus

•Identical reasoning tells us that there

must be an output register Z which collects
Y the output of the ALU at the end of each
Constant 4 cycle.
•This way, there can be
Select
MUX --one operand in the Y register
--one operand ON THE BUS
--the result stored in the Z register
A B

Control ALU
lines

Carry-in

Processor bus

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 Performing an arithmetic
operation
Add the contents of registers R1 and R2 and place the result in R3.
That is: R3 = R1 + R2

1. Place the contents of register R1 into the Y register in the first clock cycle.
2. Place the contents of register R2 onto the bus in the second clock cycle. Both
inputs to the ALU are now valid. Select register Y, and assert the ALU command
F=A+B.
3. In the third clock cycle, Z register has latched the output of the ALU. Thus
the contents of the Z register can be copied into register R3.

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 Performing an arithmetic operation
(contd..)
Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 1:
Data
MDR IR R1out, Yin
lines

Y
Constant 4 R1

R2
Select
MUX
R3
Add
A B
ALU Sub R( n - 1)
control
lines ALU

Carry-in
XOR TEMP

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 Performing an arithmetic operation
(contd..)
Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 2:
MDR
Data
IR R2out,
lines SelectY, Add,
Y Zin
Constant 4
R1

R2
SelectY
MUX
R3
Add=1
A B
ALU Sub R( n - 1)
control
lines ALU

Carry-in
XOR TEMP

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 Performing an arithmetic operation
(contd..)
Instruction
PC Control
decoder and
Signals
control logic
Address
lines
MAR
Memory
bus
Clock cycle 3:
Data
MDR IR Zout, R3in
lines

Y
Clock cycle 4:
R1
Constant 4 R3 has the sum.
R2
SelectY MUX
R3
Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry-in
XOR TEMP

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Performing an arithmetic operation
(contd..)

Clock Cycle
1:
R1out, Yin (Y=R1)
Clock Cycle
2:
R2out, SelectY, Add, Zin (Z = R1+R2)

Clock Cycle
3:
Zout, R3in (R3=Z)

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 Performing an arithmetic operation
(contd..)
 Inputs of the ALU:
 Input B is tied to the bus.
 Input A is tied to the output of the multiplexer.
 Output of the ALU:
 Tied to the input of the Z register.
 Z register:

 Input tied to the output of the ALU.

 Output tied to the bus.
 Unlike Riin, Zin loads data from the output of the ALU and
not the bus.

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 Performing an arithmetic operation
(contd..)
Events as seen by the system registers, bus, ALU over time.
cycle: controls active what the bus sees what Y has output of
ALU start of
1 R1out, Yin contents of R1 --unknown --unknown

end of
1 R1out, Yin contents of R1 R1 --unknown
=
start of
2 R2out, F=A+B contents of R2 R1 F=A+B=R1+R2
but this is not
valid yet
end of
2 R2out, F=A+B,Zin contents of R2 R1 F=A+B=R1+R2
(now valid)
=
start of
3 Zout,R3in contents of Z R1 --unknown

end of
3 Zout, R3in contents of Z R1 --unknown (but R3 latches bus
contents)

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 ALU
operations
 RC = RA op RB
 Clock cycle 1:
 Move RA to Y register.
 RAout, Yin
 Clock cycle 2:
 Put RB on the bus, perform F = RA op RB, and transfer
the result to Z.
 RBout, (RA op RB)=1, SelectY, Zin
 Clock cycle 3:
 Put Z on the bus, and load Z into RC.
 Zout, RCin

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 Fetching a word from
memory
 Processor has to specify the address of the memory
location where this information is stored and request a
Read operation.
 Processor transfers the required address to MAR.
 Output of MAR is connected to the address lines of
the memory bus.
 Processor uses the control lines of the memory
bus to indicate that a Read operation is needed.
 Requested information are received from the
memory and are stored in MDR.
 Transferred from MDR to other registers.

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 Fetching a word from memory
(contd..)
Connections for register MDR
Memory-bus
data lines MDRoutE bus
MDRout

MDR

MDR inE MDRin

MDRoutE and MDRinE control MDRout and MDRin control

connection to external bus. connection to internal bus.

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 Fetching a word from memory
(contd..)
 Timing of the internal processor operations
must be coordinated with the response time of
memory Read operations.
 Processor completes one internal data transfer in one
clock cycle.
 Memory response time for a Read operation is
variable and usually longer than one clock cycle.
 Processor waits until it receives an indication that
the requested Read has been completed.
 Control signal (MFC) is used for this purpose.
 MFC is set to 1 by the memory to indicate that the
contents of the specified location have been read and are
available on the data lines of the memory bus.

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 Fetching a word from memory
(contd..)
MOVE (R1) R2
1.Load the contents of Register R1 into
MAR. Steps can be
performed separately,
2. Start a Read operation on the memory some may be
bus. combined.
3. Wait for MFC response from the
memory.
4. Load MDR from the memory bus.
5. Load the contents of MDR into Register
R2.

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 Fetching a word from memory
(contd..)
Steps 1 and 2 can be combined.
- Load R1 to MAR and activate Read control signal simultaneously.
Steps 3 and 4 can be combined.
- Activate control signal MDRinE while waiting for response
from the memory.
Last step loads the contents of MDR into Register R2.
Memory Read operation takes 3 steps.

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 Storing a word into
memory
MOVE (R1) R2: Memory operation takes 3 steps.

Step 1:
- Place R1 onto the internal processor bus.
- Load the contents of the bus into MAR.
- Activate the Read control signal.
- R1out, MARin, Read.
Step 2:
- Wait for MFC from the memory.
- Activate the control signal to load data from external bus to MDR.
- MDRinE, WMFC
Step 3:
- Place the contents of MDR onto the internal processor bus.
- Load the contents of the bus into Register R2.
- MDRoutI, R2in

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 Execution of a complete
instruction
MOVE R2, (R1): Memory operation takes 3 steps.

Step 1:
- Place R1 onto the internal processor bus.
- Load the contents of the bus into MAR.
- R1out, MARin, Write.
Step 2:
- Place R2 onto the internal processor bus.
- Load the contents of the internal processor bus into MDR.
- Activate Write operation.
. - R2out, MDRin, Write
Step 3:
- Place the contents of MDR into the external memory bus.
- Wait for the memory write operation to be complete.
- MDRoutE, WMFC

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 Execution of a complete
instruction
Add the contents of a memory location pointed to by Register R3
to register R1.
ADD (R3) R1

To execute the instruction we must execute the following tasks:

1.Fetch the instruction.
2. Fetch the operand (contents of the memory location pointed to by
R3.)
3. Perform the addition.
4. Load the result into R1.

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Execution of a complete
instruction
Task 1: Fetch the instruction
Recall that:
- PC holds the address of the memory location which has the
next instruction to be executed.
- IR holds the instruction currently being executed.
Step 1
- Load the contents of PC to MAR.
- Activate the Read control signal.
- Increment the contents of the PC by 4.
- PCout, MARin, Read, Select4, Add, Zin.
Step 2
- Update the contents of the PC.
- Copy the updated PC to Register Y (useful for Branch instructions).
- Wait for MFC from memory.
- Zout, PCin, Yin, WMFC
Step 3
- Place the contents of MDR onto the bus.
- Load the IR with the contents of the bus.
- MDRout, IRin

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 Execution of a complete instruction
(contd..)
Task 2. Fetch the operand (contents of memory pointed to by
R3.) Task 3. Perform the addition.
Task 4. Load the result into R1.

Step 4: - Place the contents of Register R3 onto internal processor bus.

- Load the contents of the bus onto MAR.
- Activate the Read control signal.
- R3out, MARin, Read
Step 5: - Place the contents of R1 onto the bus.
- Load the contents of the bus into Register Y (Recall one operand in Y).
- Wait for MFC.
- R1out, Yin, WMFC
Step 6: - Load the contents of MDR onto the internal processor bus.
- Select Y, and perform the addition.
- Place the result in Z.
- MDRout, SelectY, Add, Zin.
Step 7: - Place the contents of Register Z onto the internal processor bus.
- Place the contents of the bus into Register R1.
- Zout, Rin

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Execution of a complete instruction
(contd..)

Step Action

1 PCout , MAR in , Read, Select4,Add, Zin

2 Zout , PCin , Yin , WMF C
3 MDRout , IRin
4 R3out , MAR in , Read R1out
5 , Yin , WMF C MDRout ,
6 SelectY, Add, Zin
7 Zout , R1in , End

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 Branch
instructions
 Recall that the updated contents of the PC are copied
into Register Y in Step 2.
 Not necessary for ADD instruction, but useful in BRANCH
instructions.:
 Branch target address is computed by adding the
updated contents of the PC to an offset.
 Copying the updated contents of the PC to Register Y
speeds up the execution of BRANCH instruction.
 Since the Fetch cycle is the same for all instructions,
this step is performed for all instructions.
 Since Register Y is not used for any other purpose at that
time it does not have any impact on the execution of the
instruction.

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 Multiple-bus
organization
Simple single-bus structure:
 Results in long control sequences, because only one
data item can be transferred over the bus in a clock
cycle.
Most commercial processors provide multiple internal paths
to enable several transfers to take place in parallel.
 Multiple-bus organization.

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 Multiple bus organization
(contd..)
Bus Incrementer
A Bus B Bus C

PC

Register
file

Constant MUX
4 A

ALU R

Instruction
decoder

IR

MDR Memory data lines

MAR Memory address lines

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 Multiple bus organization
(contd..)
 Three-bus organization to connect the registers and
the ALU of a processor.
All general-purpose registers are combined into a single
block called register file.
Register file has three ports.
 Two outputs ports connected to buses A and B,
allowing the contents of two different registers to be
accessed simultaneously, and placed on buses A and
B.
 Third input port allows the data on bus C to be loaded
into a third register during the same clock cycle.
Inputs to the ALU and outputs from the ALU:
 Buses A and B are used to transfer the source operands to
the A and B inputs of the ALU.
 Result is transferred to the destination over bus C.

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 Multiple bus organization
(contd..)
ALU can also pass one of its two input operands unmodified if
needed:
Control signals for such an operation are R=A or R=B.
Three bus arrangement obviates the need for Registers Y and Z
in the single bus organization.
 Incrementer unit:
Used to increment the PC by 4.
 Source for the constant 4 at the ALU multiplexer can be
used to increment other addresses such as the memory
addresses in multiple load/store instructions.
Multiple bus organization
(contd..)
Three operand instruction: ADD R4, R5, R6

Step Action

1 PCout, R=B, MAR in , Read, IncPC

2 WMFC
3 MDRoutB, R=B, IRin
4 R4outA, R5outB, SelectA, Add, R6in, End

1. Pass the contents of the PC through ALU and load it into MAR.
Increment PC.
2. Wait for MFC.
3. Load the data received into MDR and transfer to IR.
4. Execution of the instruction is the last step.
 Control
unit
To execute instructions the processor must generate the
necessary control signals in proper sequence.
 Hardwired control:
Control unit is designed as a finite state machine.
Inflexible but fast.
Appropriate for simpler machines (e.g. RISC machines)
 Microprogrammed control:
Control path is designed hierarchically using principles identical to
the CPU design.
Flexible, but slow.
Appropriate for complex machines (e.g. CISC machines)
 Hardwired
control
Step Action

1 PCout , MAR in , Read, Select4,Add, Zin

2 Zout , PCin , Yin , WMF C
3 MDRout , IRin
4 R3out , MAR in , Read R1out
5 , Yin , WMF C MDRout ,
6 SelectY, Add, Zin
7 Zout , R1in , End

• Each step in this sequence is completed in one clock cycle.

• A counter may be used to keep track of the control steps.
• Each state or count, of this counter corresponds to one control
step.
 Hardwired control
(contd..)
Required control signals are determined by the following
information:
 Contents of the control step counter.
• Determines which step in the sequence.
 Contents of the instruction register.
• Determines the actual instruction
 Contents of the condition code flags.
• Used for example in a BRANCH instruction.
 External input signals such as MFC.
 Hardwired control
(contd..)
Control unit organization

CLK Control step

Clock counter

•Control unit consists of

External a decoder/encoder block to
inputs
accept the following inputs:
Decoder/
IR - Control step counter.
encoder
- Instruction Register.
Condition
codes - Condition codes
- External inputs.
•Generates control signals.

Control signals
 Hardwired control
(contd..)
 Control hardware can be viewed as a state
machine: Changes state every clock cycle depending on
the contents of the instruction register, condition codes, and
external inputs.
Outputs of the state machine are control signals:
 Sequence of control signals generated by the
machine is determined by wiring of logic elements,
hence the name “hardwired control”.
 Speed of operation is one of the advantages of
hardwired control is its speed of operation.
Disadvantages include:
 Little flexibility.
 Limited complexity of the instruction set it can implement.