Chapter 3 Power Switching Devices and their Static Electrical Characteristics 72

devices. Similar techniques are extendable to devices other than diodes, such as thyristors. Field
control bevelling on more complex junction structures is achieved with double-negative or double-
positive bevelling as shown in parts e and f of figure 3.1. The bevelling is accomplished by grinding,
followed by etching of the bevel surface to restore the silicon crystalline mechanical and structure
quality. The processed area is passivated with a thin layer of polyimide, which is covered in silicon

3
rubber. Negative (as opposed to positive) bevels tend to be more stable electrically with ageing.
The foregoing discussion is directly applicable to the rectifier diode, but other considerations are also
important if fast switching properties are required. The turn-on and reverse recovery time of a junction
are minimised by reducing the amount of stored charge in the neutral regions and by minimising carrier
lifetimes. Lifetime killing is achieved by adding gold or platinum, which is an efficient recombination
centre. Electron and proton irradiation are preferred non-invasive lifetime control methods. Irradiation
gives the lowest forward recovery voltage and the lowest reverse leakage current. The improved
switching times must be traded off against increased leakage current and on-state voltage. Switching
Power Switching Devices times are also improved by minimising the length (thickness) of the n-region.

and their cathode

Static Electrical Characteristics

anode

cathode

There is a vast proliferation of power switching semiconductor devices, each offering various features, (a) (b)
attributes, and limitations. The principal device families of concern in the power switching semiconductor
range are the diode, transistor, and thyristor. Each family category has numerous different members.
The basic characteristics of the three families and a range of their members, both uni-polar and bipolar anode
anode
carrier types, will be presented.

3.1 Power diodes

The homojunction p-n diode is the simplest semiconductor device, comprising one pn junction. In n
+
n+
attempts to improve both static and dynamic diode electrical properties for different application cathode cathode
conditions, numerous diode types and material technologies have evolved.
(c) (d)

3.1.1 The pn fast-recovery diode

The doping concentration on each side of the junction influences the avalanche breakdown voltage, the
contact potential, and the series resistance of the diode. The junction diode normally has the p-side
highly doped compared with the n-side, and the lightly doped n-region determines most of the properties
of the device. The n-region gives the device its high-voltage breakdown and under reverse bias, the scl
penetrates deeply into the n-side. The lower the n-type concentration and the wider the n-side, the
higher will be the reverse voltage rating and also, the higher the forward resistance. These n-region
requirements can lead to thermal I2R problems in silicon. Larger junction areas help reduce the thermal
instability problem.
It is usual to terminate the lightly doped n-region with a heavily doped n+ layer to simplify ohmic contact
and to reduce the access resistance to the scl. For better n-region width control, n-type silicon is
epitaxially grown on an n+ substrate. The p+ anode is diffused or implanted into the epitaxial region, (e) (f)
forming an epitaxial diode.
Figure 3.1. Prevention of edge breakdown under junction reverse bias:
In devices specifically designed for high reverse bias applications, care must be taken to avoid (a) reduction of the space charge region near the bevel; (b) p-type guard ring; (c) glass guard ring;
premature breakdown across the edge of the die or where the junction surfaces. Premature edge (d) glass plus p-type guard ring; (e) double negative bevel; and (f) double positive bevel angle.
breakdown is reduced by bevelling the edge as shown in figure 3.1a, or by diffusing a guard ring as
shown in figure 3.1b, which isolates the junction from the edge of the wafer. The scl electric field is lower
at the bevelled edge than it is in the main body of the device. In the case of a lightly doped p-type guard 3.1.2 The p-i-n diode
ring, the scl is wider in the p-ring, because of its lower concentration, than in the p+ region. The The transient performance of diodes tends to deteriorate as the thickness of the silicon wafer is
maximum electric field is therefore lower at the pn-ring junction for a given reverse bias voltage. increased in attaining higher reverse voltage ratings. Gold lifetime killing only aggravates the adverse
Negatively charged glass film techniques are also employed to widen the scl near the surface, as shown effects incurred with increased thickness. The p-i-n diode allows a much thinner wafer than its
in figures 3.1c and 3.1d. Multiple guard rings are sometimes employed for high breakdown voltage conventional pn counterpart, thus facilitating improved switching properties.

BWW
73 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 74

The p-i-n diode is a pn junction with a doping profile tailored so that an intrinsic layer, the i-region, is
sandwiched between the p-layer and the n-layer, as shown in figure 3.2. In practice, the idealised i-
region is approximated by a high resistivity n-layer referred to as a v-layer. Because of the low doping in
the v-layer, the scl will penetrate deeply and most of the reverse bias potential will be supported across forward
bias
this region.

n i

reverse
bias

p.d. = area

p.d. = area

Figure 3.3. Diodes: (a) static I-V characteristic; (b) symbol for a rectifier diode;
(c) voltage reference or Zener diode; and (d) Schottky barrier diode.

Figure 3.2. Cross-section and electric field distribution of:

3.1.4 The Schottky barrier diode
(a) a pn diode and (b) a p-i-n diode.
The Schottky diode is a metal-semiconductor diode device which offers low on-state voltages, but in
silicon is presently restricted to applications imposing a reverse bias of less than 400V. At lower
voltages, less than 40V, devices of up to 300A are available and the maximum junction operating
The power p-i-n diode can be fabricated by using either the epitaxial process or the diffusion of p and
temperature is 175°C, which is higher than for conventional silicon pn junction devices.
n-regions into a high-resistivity semiconductor substrate. The i-region width Wi , specifies the reverse
The Schottky diode is formed by a metal (such as chromium, platinum, tungsten or molybdenum) in
voltage breakdown of the p-i-n diode, which is the area under the electric field in figure 3.2b, viz.,
homogeneous contact with a substrate piece of n-type silicon, as shown in figure 3.4a. The contact is
Vb ≈ ξb W ≈ 25Wi (in µm) (V) (3.1) characterised by a potential barrier Φb > 0 (termed Schottky barrier height) which determines the
forward and reverse properties of the Schottky diode.
The thickness Wi , along with the distribution of any gold within it, determines the nature of the reverse In forward conduction, electrons are emitted from the negative potential n-type silicon to the positive
and forward-conducting characteristics. These characteristics are more effective and efficient in fast p-i- potential metal, passing over the barrier potential. Unlike the bipolar pn diode, only electrons are
n diodes than in the traditional pn structures. carriers, hence the Schottky barrier diode is a unipolar device. The forward on-state voltage drop is
dominated by and proportional to the barrier potential Φb, while unfortunately the reverse leakage
current is approximately inversely related. Thus a Schottky diode with a low forward voltage drop will
have high reverse leakage current relative to the pn diode counterpart, as shown in figure 3.5.
3.1.3 The power Zener diode Chromium provides the lowest forward voltage drop but is limited to an operating temperature of
125°C and has a high leakage current. Platinum allows operating temperatures to 175°C with a leakage
Zener diodes are pn diodes used extensively as voltage reference sources and voltage clamps. The current several orders of magnitude lower than chromium. The trade-off is a higher forward voltage.
diode reverse breakdown voltage is used as the reference or clamping voltage level. A guard ring is used to improve device robustness, but its function is to act like a Zener diode and
The leakage current in a good pn diode remains small up to the reverse breakdown point where the thus protect the Schottky barrier under excessive reverse bias. An optimally designed epitaxial layer, as
characteristic has a sharp bend. Such an electrical characteristic is called hard. Premature breakdown at shown in figure 3.4b, is also employed which reduces the field at the less than perfect metal-
weak spots in the junction area or periphery cause high leakage currents before final breakdown, and semiconductor interface and allows the whole interface to go safely into reverse bias breakdown.
such diodes are said to have soft breakdown characteristics.
Zener diodes are especially made to operate in the breakdown range. Above a few volts, the There are a number of important differences between Schottky barrier and pn junction diodes.
breakdown mechanism is avalanche multiplication rather than Zener and the breakdown reference • In a pn diode, the reverse bias leakage current is the result of minority carriers diffusing into the
voltage VZ is obtained by proper selection of the pn junction doping levels. Once in breakdown VZ scl and being swept across it. This current level is highly temperature-sensitive. In the Schottky-
remains almost constant provided the manufacturer’s power rating, P = VZ I, is not exceeded. Where the barrier case, reverse current is the result of majority carriers that overcome the barrier. A much
breakdown mechanism is due to the Zener effect, the temperature coefficient for silicon devices, is higher leakage value results at room temperature, but is not temperature-dependent.
negative, about -0.1 per cent/K, changing to positive, +0.1 per cent/K, after about 4.5V when the • The forward current is mostly injected from the n-type semiconductor into the metal and little
avalanche multiplication mechanism predominates. excess minority charge is able to accumulate in the semiconductor. Since minimal minority
Zener diodes require a hard breakdown characteristic not involving any local hot spots. They are carrier recombination occurs, the Schottky barrier diode is able to switch rapidly from forward
available in a voltage range from a few volts to about 280V and with continuous power dissipations conduction to reverse voltage blocking.
ranging from 250mW to 75W, with heat sinking. Transient suppressing Zener diodes can absorb up to • Since under forward bias, barrier injection comes only from the semiconductor, and there is little
50kW, provided energy limits and current limits are not exceeded, as shown in figure 10.35. recombination in the scl; the device can be represented by the ideal diode equation (2.6).
Practically, Zener diodes are difficult to make, less than ideal in application, and should be avoided if • The majority electrons injected over the barrier into the metal have much higher energy than the
possible. The basic I-V characteristics, and electrical circuit symbol for the different types of diodes, are other metal electrons which are in thermal equilibrium. Those injected electrons are therefore
shown in figure 3.3. called hot, and the diode in some applications is referred to as a hot electron diode.
75 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 76

An significant point arising from this consideration of the Schottky barrier diode is the importance of
the connection of an n-type semiconductor region to aluminium metallization that occurs in unipolar and
bipolar semiconductor devices. A practical method of forming aluminium ohmic contacts on n-type
materials where Φb > 0, is by doping the semiconductor heavily (>1019 /cm3), above the degeneracy
level. Thus, in the contact region, if a barrier exists, the scl width is small enough (<3nm) to appear
transparent, allowing electron carriers to tunnel through the barrier in both directions. On the other hand,
aluminium makes a good ohmic contact on p-type silicon since the required p+ surface layer is formed
during the heat treatment of the contact after the aluminium is deposited. An ohmic contact acts as a
virtual sink for minority carriers, because it has an enormous supply of majority carriers.

(a)
3.1.5 The silicon carbide Schottky barrier diode

Silicon carbide Schottky diodes are attractive for high voltages because the field breakdown of silicon
carbide is eight times that of silicon. Additionally, the wide band gap allows higher operating
temperatures. Both nickel and titanium can be used as Schottky metals. Boron atoms (a dose of 1x1015
/cm2 at 30keV) are implanted to form the edge termination that spreads any field crowding at the edge of
the metal contact, as shown in figure 3.6. The lower barrier height of titanium produces a lower forward
voltage device, but with a higher reverse leakage current, than when nickel is used as the barrier metal.
Anode, Aℓ
Implanted edge termination Schottky
barrier
p
Nitride
passivation

n- epi-layer
(b)

Figure 3.4. The Schottky barrier diode: (a) basic structure and (b) space charge layer region
extending into the epi-substrate region under reverse bias. +
n substrate
Table of Schottky barrier heights ΦB of silicates on n-type silicon.
NiV/Ag

cathode

Figure 3.6. The silicon carbide Schottky barrier diode structure.

3.2 Power switching transistors

Two types of transistor are extensively used in power switching circuits, namely the enhancement mode,
+ power metal oxide semiconductor field effect transistor (MOSFET) and the insulated gate bipolar
transistor (IGBT). Effectively, the IGBT has a pnp bipolar junction transistor (BJT) output stage and an n-
- channel MOSFET input stage, in an integrated Darlington pair configuration. Many of the IGBT power
handling properties are associated with BJT limitations. Thus some attention to the BJT’s electrical
characteristics is necessary, even though it is virtually obsolete as a discrete power-switching device.
SiC BJTs may offer a short reprieve, only because of its extremely low on-state voltage characteristics.

• The BJT consists of a pnp or npn single-crystal silicon structure. It operates by the
injection and collection of minority carriers, both electrons and holes, and is
therefore termed a bipolar transistor.
• The MOSFET depends on the voltage control of a depletion width and is a majority
carrier device. It is therefore a unipolar transistor.
• The IGBT has the desirable voltage input drive characteristics of the MOSFET but the
power switching disadvantages of the minority carrier mechanisms of the BJT.

3.2.1 The bipolar npn power switching junction transistor (BJT)

+
As a discrete electrical device, the high-voltage, Si power-switching bipolar junction transistor, BJT, is
- virtually obsolete. The BJT has one unique redeeming electrical characteristic, viz.; it can be designed
to conduct hundreds of amperes with an extremely low on-state voltage of less than 100mV, when both
junctions are forward biased, saturated. Although superseded, its basic electrical operating
Figure 3.5. Schottky and epi diode I-V characteristics with different Schottky barrier potentials. characteristics are fundamental to the operation of other power switching devices. Specifically, the
77 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 78

MOSFET has a parasitic npn BJT, as shown in figure 3.14, that can cause false turn-on other than for the should be composed almost entirely of electrons injected into the base, rather than holes crossing from
fact that understanding of BJT characteristics allows circumvention of the problem. The fundamental the base region to the emitter. Any such holes must be provided by the base current, which is minimised
operation of thyristors (SCR, GTO, and GCT) relies on BJT characteristics and electrical mechanisms. by doping the base region lightly compared with the emitter such that an n+p emitter results. Such a
The IGBT has two parasitic BJTs, as shown in figure 3.16, that form an undesirable pnp-npn SCR junction is said to have a high injection efficiency, γi. A low lattice defect density also increases the
structure. Understanding of BJT gain mechanisms allows virtual deactivation of the parasitic SCR. injection efficiency.
The first bipolar transistors were mainly pnp, fabricated by alloying techniques and employed
germanium semiconductor materials. Most transistors are now npn, made of silicon, and utilise selective
diffusion and oxide masking.
αIe
A typical high-voltage triple-diffused transistor doping profile is shown in figure 3.7a. The n-collector
region is the initial high-resistivity silicon material and the collector n+ diffusion is performed first, usually
into both sides. One n+ diffusion is lapped off and the p-base and n+ emitter diffusions are sequentially
performed.
A planar epitaxial structure is often used for transistors with voltage ratings of less than 1000V. The RLoad
basic structure and processing steps are shown in figure 3.7b. The n-type collector region is an epitaxial
layer grown on an n-substrate. The base and emitter are sequentially diffused into the epitaxy. Ion
implantation is also used. This approach allows greater control on the depth of the n-type collector
region, which is particularly important in specifying device switching and high-voltage properties. Also, Rb
the parasitic series collector resistance of the substrate is minimised without compromising the pellet’s
mechanical strength as a result of a possible reduction in wafer thickness.

Figure 3.8. Common emitter junction bias conditions for an npn transistor
and the npn bipolar junction transistor circuit symbol.

The relationship between collector and emitter current is

ic
= bt γ i = α (3.2)
ie
The factor α is called the current transfer ratio. Since base current is necessary, α is less than 1, but
close to 1, if the BJT
• has a good base transport factor, bt ≈ 1
(narrow base width and with long minority carrier lifetimes – low base concentration) and
• a high emitter injection efficiency, γi ≈ 1
(high emitter doping relative to the base concentration).
In the common emitter configuration shown in figure 3.8, the ratio between the base current ib and the
collector current ic, is of practical importance. Since, by Kirchhoff’s current law, the base current is the
difference between the emitter and the collector current
ic ic i /i
= = c b (3.3)
ib ie − ic 1 − ic / ib
Figure 3.7. Impurity profile in two types of npn transistors: α
= =β (3.4)
(a) a planar triple-diffused npn transistor obtained by three consecutive diffusions into a uniformly 1−α
doped n-type substrate and (b) planar epitaxial npn transistor, obtained after two diffusions into n-
type epitaxial layer which is first grown on a low-resistivity n-type silicon substrate. The factor β, relating the collector current to the base current, is defined as the base-to-collector
current amplification factor. If α is near unity, β is large, implying the base current is small compared with
the collector current.
3.2.1i - BJT gain
Figure 3.8 shows an npn bipolar junction transistor connected in the common emitter configuration. In
3.2.1ii - BJT operating states
this configuration, injection of electrons from the lower n+p junction into the centre p-region supplies
In power switching applications, a transistor is controlled in two states which can be referred to as the
minority carrier electrons to participate in the reverse current through the upper np junction.
off-state or cut-off state and the conduction on-state. Ideally the transistor should appear as a short
The n+ region which serves as the source of injected electrons is called the emitter and forms the
circuit when on and an open circuit when in the off-state. Furthermore, the transition time between
emitter junction with the p-base, while the n-region into which electrons are swept by the reverse bias np
these two states is ideally zero. In reality, transistors only approximate these requirements.
junction is called the collector and, with the p-base, forms the collector junction.
The typical BJT collector output characteristics are shown in figure 3.9 which illustrates the various
To have an efficient npn transistor almost all the electrons injected by the emitter into the base should
BJT operating regions. The saturated on-state shown in figure 3.9 occurs when both the collector and
be collected. Thus the p-base region should be narrow and the electron minority carrier lifetime should
emitter junctions are forward biased. Consequently, the collector emitter voltage Vce(sat) is less than the
be long to ensure that the average electron injected at the emitter will diffuse to the collector scl without
base to emitter saturation voltage Vbe(sat).
recombining in the base. The average lifetime of electrons in the p-base increases as the p-base
The voltage breakdown phenomenon is of particular importance to the high-voltage, power-switching
concentration decreases, that is as the hole concentration decreases. The fraction of electrons which
BJT, and is due to the characteristics of the device structure and geometry.
reach the collector is called the base transport factor, bt. Electrons lost to recombination in the p-base
must be re-supplied through the base contact. It is also required that the emitter junction carrier flow
79 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 80

When a positive gate voltage is applied with respect to the source as shown in figure 3.10b, positive
charges are created on the metal gate. In response, negative charges are induced in the underlying
silicon, by the formation of a depletion region and a thin surface region containing mobile electrons.
Effectively the positive gate potential inverts the p-channel, forming an electron-enhanced low-
resistance n-channel, allowing current to flow freely in either direction between the drain and source.
Saturation The inversion channel is essentially devoid of the thermal properties associated with the typical BJT.
region
ib=4A An important parameter in mos transistors is the threshold voltage VTh, which is the minimum positive
gate voltage to induce the n-conducting channel. With zero gate voltage the structure is normally off.
ib=3A The device is considered to operate in the enhancement mode since the application of a positive gate
Linear voltage in excess of VTh induces an n-conducting channel. The typical temperature dependant output
ib=2A
region characteristics of the MOSFET are shown in figure 3.10c.

ib=1A
ib=0A Vb

Cut-off Vcbo
region

Figure 3.9. Output characteristics of a common emitter connected transistor

showing its operating regions and the voltage breakdown range.

3.2.1iii - BJT maximum voltage - first and second breakdown pinch-off

The collector junction supports the off-state voltage and in so doing develops a wide scl. This scl
increases in width with increased reverse bias, penetrating into the base. It is unusual that a correctly
designed high-voltage power switching BJT would break down as a result of punch-through of the
collector scl through the base to the emitter scl. Because of the profile of the diffused base, collector
junction voltage breakdown is usually due to the avalanche multiplication mechanism, created by the
high electric field at the collector junction. In the common emitter configuration shown in figure 3.9, the
transistor usually breaks down gradually, but before the collector junction avalanches at Vb. This occurs
because the avalanche-generated holes in the collector scl are swept by the high field into the base. The
emitter injects electrons in order to maintain base neutrality. This emitter junction current in turn causes
more collector current, creating more avalanche pairs leading to regenerative action. This voltage
dependant avalanche effect is modelled by
1 T 
M = (3.5) saturation
1 − (v ce /Vb )m T  region
constant
Thus the gain mechanisms of the transistor cause collector to emitter breakdown - first breakdown, at resistance
voltage Vceo, to occur before collector to base avalanche breakdown, at voltage Vcbo, which from
α M = 1 are related according to
constant current
Vceo =Vcbo (1 − α )1/m ≈ Vcbo / β 1/m
=Vb / β 1/m (V) (3.6) T 
where the avalanche breakdown voltage Vb is given by equation (2.3);
m ≈ 6 for a silicon p+n collector junction; and
m ≈ 4 for a silicon n+p collector junction.
Figure 3.10. Enhancement-type n-channel mos transistor:
Contradictory device properties are that the higher the forward gain, the lower the breakdown voltage. (a) device cross-section; (b) induced n-channel near pinch-off; and (c) drain I-V characteristics as a
A much higher collector emitter breakdown voltage level can be attained if the base emitter junction is function of gate voltage, showing the pinch-off locus and effects of increased temperature.
reverse biased in the off-state.
First breakdown need not be catastrophic provided junction temperature limits are not exceeded. If
local hot spots occur because of non-uniform current density distribution as a result of crystal faults,
doping fluctuation, etc., second breakdown occurs. Silicon crystal melting and irreparable damage
3.2.2i - MOSFET structure and characteristics
result, the collector voltage falls, and the current increases rapidly as shown in figure 3.9.
The conventional horizontal structure in figure 3.10a has severe limitations associated with increasing
die area that make it uneconomical for consideration as a viable high-current structure. A planar vertical
n-channel dmos structure like those shown in figure 3.11 is used to overcome the inherent poor area
3.2.2 The metal oxide semiconductor field effect transistor (MOSFET)
utilisation of the basic mos structure. The enclosing peripheral p floating field guard is not shown.
The basic low-power lateral structure of the enhancement mode, metal oxide semiconductor, field effect The dmos structure is a vertical current flow device. An n- epitaxial layer is grown on an n+ substrate.
transistor (MOSFET) is illustrated in figure 3.10a. The n+ source and drain regions are diffused or A series of p body regions are next diffused into the epitaxial layer. Then n+ source regions are diffused
implanted into the relatively lightly doped p-type substrate, and a thin silicon dioxide layer insulates the within the p body regions and a polycrystalline silicon gate is embedded in the silicon dioxide insulating
aluminium gate from the silicon surface. No lateral current flows from the drain to source without a layer. Source and gate metallization are deposited on the top surface of the die and the drain contact
conducting n-channel between them, since the drain-to-source path comprises two opposing series pn made to the bottom surface. Cell density is inversely related to voltage rating and varies from 200,000
junctions. to 1,000,000 cells per cm2.
81 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 82

With a positive gate voltage, the device turns on and majority carriers flow laterally from the source to where Ca is the capacitance per unit area of the gate oxide (ε / tox)
the drain region below the gate and vertically to the drain contact. Current can also flow freely in the Wc is the width of the channel
reverse direction in the channel since the channel is bipolar conducting once enhanced. νsat is the saturation velocity of electrons in silicon, (9.0x106 cm/s)
Lc is the effective channel length
µn is the conducting channel carrier mobility, (300 cm2/ V-s).
In the ohmic (linear) region, where V gs > Vth and V gs −Vth > Vds > 0 , the drain current is given by
Wc
I d = µn C (V −V )V − ½ Vds2  (3.9)
Lc a  gs TH ds
and when the gate voltage is below the threshold level, V gs < VTh ,
Id = 0 (3.10)

DRAIN

Figure 3.11. Two designs for the n-channel MOSFET and its circuit symbol
(courtesy of Infineon and International Rectifier).

Figure 3.12. MOSFET gate voltage characteristics:

The obtainable drain-to-source breakdown voltage is not limited by the gate geometry. The scl (a) transfer characteristics of gate voltage versus drain current and
associated with voltage blocking penetrates mostly in the n-type epitaxial layer. Thickness and doping (b) transconductance characteristics of gate voltage versus transconductance, gfs.
concentration of this layer are thus decisive in specifying the blocking capability of the power MOSFET.
The basic drain current versus drain to source voltage static operating characteristics (and their Figure 3.12a shows that drain current exhibits both a positive and negative temperature coefficient
temperature dependence) of the power MOSFET are illustrated in figure 3.10c. For a given gate voltage, with the drain current IDQ being the boundary condition. If the drain current is greater than IDQ there is a
there are two main operating regions on the drain current-voltage characteristic. possibility of destruction by over-current at low temperatures, while if the drain current is less than IDQ,
• The first is a constant resistance region, where an increase in drain to source voltage over-current can produce thermal runaway and destruction. Operation with a gate voltage corresponding
results in a proportional increase in drain current. (In practice, the effective resistance to IDQ avoids the need for any gate drive temperature compensation.
increases at higher drain currents.) At high gate voltages, the on-resistance of the resistive region and the drain current in the constant
• At a certain drain current level, for a given gate voltage, a channel pinch-off effect occurs current region, become somewhat independent of the gate voltage. This phenomenon is best illustrated
and the operating characteristic moves into a constant current region. in the Id versus Vds characteristic by the curve cramping at high gate voltages in figure 3.10c.
3.2.2iii - MOSFET transconductance and output conductance
3.2.2ii - MOSFET drain current Inspection of the static drain source characteristics of figure 3.10c reveals that as the gate voltage
When the power MOSFET is used as a switch, it is controlled in the on-condition, such that it is forced to increases from zero, initially the drain current does not increase significantly. Only when a certain
operate in the resistive region. This ensures that the voltage drop across the device is low so that the threshold gate voltage, VTh, has been reached, does the drain current start to increase noticeably. This
drain current is essentially defined by the load and the device power dissipation is minimal. Thus for is more clearly illustrated in figure 3.12b which shows the characteristics of drain current Id and small
switching applications, the on-resistance Rds(on) is an important characteristic because it will specify the signal transconductance gfs versus gate voltage, at a fixed drain voltage. It will be seen from these
on-state power loss for a given drain current. The lower Rds(on), the higher the current-handling characteristics that no conduction occurs until Vgs reaches the threshold level, VTh, after which the Id
capabilities of the device; thus Rds(on) is one important figure of merit of a power MOSFET. versus Vgs characteristic becomes linear, the slope being the transconductance gfs.
A quadratic MOSFET model allows the inversion layer charge between the source and the drain to The amplification factor, gain, forward transconductance, gfs, is defined as
vary. For power MOSFETs that have short channels, the drain current Id is related to the channel ∂I d
g fs 
dimensions and the gate voltage Vgs according to ∂V gs V
ds = constant

at low current, above pinch-off Differentiating equations (3.7) and (3.8), for Vds ≥ V gs −VTh , with respect to gate voltage, gives
Wc at low current
I d = ½ µn C a (V gs −VTh )2 (A) (3.7)
Lc
Wc Wc
if Vds ≥ V gs −VTh > 0 for n-channel MOSFETs, to the left of the pinch-off locus in figure 3.10c. g fs = µn C a (V gs −VTh ) = 2 µC I (mho) (3.11)
Lc Lc n a Dn
at high current after electron velocity saturation, the quadratic model is invalid and at high current
I Dn
I d = ½v sat Wc C a (Vgs −VT h ) (A) (3.8) gfs = ½v satWc C a = (mho) (3.12)
Vgs −VTh
83 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 84

At high electric fields, that is high currents, the carrier velocity νsat saturates. 3.2.2v - MOSFET p-channel device
In the ohmic region, V gs > 0 and V gs −Vth > Vds , the forward transconductance is P-channel MOSFETs are similar to n-channel devices except that the n and p regions are
interchanged. In p-channel devices the on-resistance, for a given die area, will be approximately twice
Wc
g fs = µn CV (3.13) that of a comparable n-channel device. The reason for this is that in the n-channel device the majority
Lc a ds carriers are electrons but in the p-channel device, the majority carriers are holes which have lower
mobility. If the area of a p-channel device is increased to produce an equal Rds(on), then the various
The output conductance, gd, is defined as capacitances of the p-channel device will be larger, and the device costs will be greater.
∂I d In the linear region, the drain current is
gd 
∂Vds Wc µpC a
V gs = constant −I d p = (V gs +VTh p )Vds − ½Vds2 
The output conductance quantifies the drain current variation with drain voltage variation for a constant
Lc
gate voltage. For saturation
Wc µpC a
Differentiating equations (3.7) and (3.8), with respect to drain voltage, gives zero, gd = 0, for each case −I d p = ½ (V gs +VTh p )2 
Lc
in the saturation region. In the ohmic region the output conductance is
The transconductance in the saturation region is
Wc
g d = µn C (V −V −V ) (3.14) ∂i D p W   Wc 
Lc a gs Th ds g fs p = = c  µpC a (V gs +VTh p ) = 2   µ p C a ( −I d p )
∂v gs Q  Lc   Lc 
A typical minimum threshold voltage is about 2V and exhibits temperature dependence of
approximately -10mV per K (α = 0.5 per cent/K), as shown in figure 3.13. At high gate voltages, the drain
current becomes constant as the transconductance falls to zero, implying the upper limit of forward drain
current. The temperature variation of transconductance is small, typically -0.2 per cent/K, which results
in extremely stable switching characteristics. The typical temperature coefficient for the gain of a bipolar
junction transistor, the MOSFET equivalent to gfs , is +0.8 per cent/K. The temperature dependence of the
MOSFET forward conductance is approximated by
−2.3
 T 
g fs (T ) ≈ g fs (25°C) ×   (mho) (3.15) V(BR)DSS
 300  Vgs(TH)
Vgs =0V
ID=1mA
since temperature effects are dominated by mobility variation with temperature.
Inherent in the MOSFET structure are voltage-dependent capacitances and on-state resistance.

gfs
3.2.2iv - MOSFET on-state resistance
Vds=50V
In the fully on-state the drain-source conduction characteristics of the MOSFET can be considered as
purely resistive. The on-resistance Rds(on) is the sum of the epitaxial region resistance, the channel
resistance, which is modulated by the gate source voltage, and the lead and connection resistance. One
reason for the wide proliferation of special gate geometries is to produce extremely short, reproducible
channels, in order to reduce Rds(on). In high-voltage devices, the on-resistance is dominated by the
resistance of the epitaxial drain region when the device is fully enhanced. For high-voltage n-channel
devices, the on-state resistance is approximated by Figure 3.13. Normalised drain-source on-resistance, transconductance, gate threshold voltage,
Rds (on) = 6.0 × 10 −7 ×V b2.5 / A (Ω ) (3.16) and breakdown voltage versus junction temperature.
where Vb is the breakdown voltage in volts
A is the die area in mm2.
Example 3.1: Properties of an n-channel MOSFET cell
A p-channel device with the same Vb as an n-channel device has an Rds(on) two to three times larger as
given by A silicon n-channel MOSFET cell has a threshold voltage of VTh = 2V, Wc = 10µm, Lc = 1µm, and an
Rds (on) = 1.6 × 10−6 ×V b2.5 / A (Ω ) (3.17) oxide thickness of tox = 50nm. The device is biased with Vgs = 10V and Vds = 15V.
i. Assuming a quadratic model and a surface carrier mobility of 300 cm2/V-s, calculate the
drain current, cell dissipation, forward transconductance, and output conductance.
The factor l/gfs of Rds(on) is added to give the total Rds(on). On-state drain-source loss can therefore be
ii. Assuming carrier velocity saturation (5x106 cm/s), calculate the drain current, cell
based on I d2 Rds ( on) . On-resistance Rds(on) increases with temperature and approximately doubles over the
dissipation, forward transconductance, and output conductance.
range 25°C to 200°C, having a positive temperature coefficient of approximately +0.7 per cent/K above
25ºC, as shown in figure 3.13. The temperature dependence of the on-state resistance is approximated Solution
by i. The MOSFET is biased in saturation since Vds > V gs - VTh . Therefore, from equation (3.7)
2.3 the drain current equals:
 T 
Rds (on) (T ) = Rds (on) (25°C) ×   (Ω) (3.18)
 300  Wc
I d = ½ µC a (V −V )2 where C a = ε / t ox
where the temperature T is in degrees Kelvin. This relationship (as does forward conductance in Lc gs Th
equation (3.15)) closely follows the mobility charge dependence on temperature. 3.85 × 8.85 × 10−12 10µm
= ½ × 300 × 10−4 × × × (10V − 2V)2 = 6.5 mA
Since Rds(on) increases with temperature, current is automatically diverted away from any hot spot. Thus 50 × 10−9 1µm
unlike the bipolar junction transistor, second breakdown cannot occur within the MOSFET. The The dc power dissipation is 6.5mAx15V=97.5mW.
breakdown voltage Vb has a positive temperature coefficient of typically 0.1 per cent/K as shown by From equation (3.11), the transconductance is:
V(BR)DSS in figure 3.13.
85 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 86

Wc 3.2.2vii - MOSFET on-state resistance reduction

g fs = µ C a (V −V ) Most power switching devices have a vertical structure, where the gate and source of the MOSFET (or
Lc gs Th
emitter in the case of the IGBT) are on one surface of the substrate, while the drain (or collector) is on
3.85×8.85×10-14 10 the other substrate surface. The principal current flows vertically through the substrate but the
= 300×10-4 × × ×(10V - 2V) = 1.64 mho
50×10-9 1 conductive channel is lateral due to the planar gate structure, as shown in figure 3.11. The structure
The output conductance gd is zero. resistance components between the drain and source are:
• the drift region;
ii. When the electron velocity saturates, the drain current is given by equation (3.8) • the JFET region;
I d = ½v sat Wc C a (Vgs −VT h ) • the accumulation region; and
• the channel region.
3.85×8.85×10-12 The drift region contribution dominates whilst the contribution from the ohmic contacts and n+ substrate
= ½ × 5×104 × 10-5 × × (10V - 2V) = 136 mA
50×10-9 are not significant, in high voltage devices. The channel voltage drop is proportional to channel length
The dc power dissipation is 136mA x 15V=2W, a dc operating condition well in excess of and inversely related to width. The channel should therefore be short, but its length is related to voltage
the cell capabilities. rating since it must support the off-state scl.
The transconductance is given by equation (3.12)
g fs = ½v satWc C a Whilst retaining the necessary voltage breakdown length properties, two basic approaches have been
pursued to achieve a more vertical gate (channel) structure, viz., the trench gate and vertical super-
3.85×8.85×10-12
= ½ × 5×104 × 10-5 × = 16.1 mho junction, as shown in parts b and c of figure 3.15. Both techniques involve increased fabrication
50×10-9 complexity and extra costs.
The output conductance gd is zero.
1 - Trench gate
♣ A channel is formed on the vertical sidewalls of a trench etched into the die surface as shown in figure
3.15b. The JFET resistive region is eliminated, which not only reduces the total resistance but allows
smaller cell size thereby increasing channel density and decreasing the short-circuit capacity. The
3.2.2vi - MOSFET parasitic BJT trench corners must be rounded to avoid high electric field stress points. By extending the gate into the
Figure 3.14 shows the MOSFET equivalent circuit based on its structure and features. The parasitic npn drift region, the gate to drain capacitance increases, hence increasing gate charge requirements.
bipolar junction transistor shown in figure 3.14b is key to device operation and limitations. S o urc e g a te
Capacitance exists within the structure from the gate to the source, Cgs, the gate to the drain, Cgd, and
from the drain to the source, Cds. The capacitance Cgs varies little with voltage; however Cds and Cgd vary n+
p
significantly with voltage. Obviously these capacitances influence the switching intervals, an aspect
considered in Chapter 4.4.2.
The emitter of the parasitic npn transistor is the source of the MOSFET, the base is the p-type body n
-
epi
and the collector is the drain region. In the construction of the MOSFET, the emitter and base of the npn
transistor are purposely shorted out by the source metallization to disable the parasitic device by
reducing its injection efficiency. However, this short circuit cannot be perfect and Rbe models the lateral n +s u b
p-body resistance, while Cob is essentially Cds. The npn transistor has a collector-emitter breakdown
voltage, between Vcbo and Vceo. If an external dv/dt is applied between the drain and source as shown in D rain
figure 3.14b, enough displacement current could flow through Cob to generate a voltage drop across Rbe
S o urce (a ) S o u rce
sufficient to turn on the parasitic bipolar device, causing MOSFET failure in second breakdown.
When the drain to source voltage is negative, current can flow from the source to drain through Rbe ga te g a te
and the base to collector junction of the parasitic npn transistor within the structure, the dashed line
n n ++
shown in figure 3.14b. This is termed the body diode, inherent in the MOSFET structure. p
p

Drain

g a te
- -
n+ n n p n e pi

n n +s u b

-
n D ra in D ra in
RD
Cgd Cds
(b ) (c )
Figure 3.15. Three MOSFET channel structures:
C gd (a) conventional planar gate; (b) trench gate; and (c) vertical superjunction.
R be
p+ C ds
Rbe 2 - Vertical super-junction
+
n
Cgs The structure has vertical p-conducting regions in the voltage sustaining n- drift area, that are extend to
the p-wells below the gate, as shown in figure 3.15c. In the off-state, the electric field is not only in the
Idiode
vertical direction but also in the horizontal plane. This means the n-drift region width can be decreased,
Source Gate Rg C gs SiO 2 Source the on-state resistance is decreased, and the gate charge is reduced for a given surface area. Up to
(a) (b) sixteen mask steps are needed which involves repeated cycles of n-type epi-layer growth, masked
boron implantation, and finally diffusion. The resultant specific resistance is near linearly related to
Figure 3.14. MOSFET – n-channel enhancement mode: (a) structure and breakdown voltage, as opposed to Rds (on) × Area ∝ V br2.5 , equation (3.16). Typically Rds(on) is five times
(b) equivalent circuit diagram with parasitic npn bipolar transistor forming an inverse diode. lower than for the conventional MOSFET, which only uses up to six mask steps.
 87 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 88

Whilst the trench gate concept can be readily applied to other field effect devices without voltage 3.2.3ii - IGBT in the on-state
rating limits, the vertical super-junction is confined to the MOSFET, and then at voltage ratings below The p+ substrate conductively modulates the n- region with minority carriers, which whilst conducting the
about 1000V. main collector current, produces a low on-state voltage at the expense of a 0.6 to 0.8V offset in the
output voltage characteristics due to the collector pn junction. From figure 3.16c, the IGBT collector
3.2.3 The insulated gate bipolar transistor (IGBT) current is approximated by
The high off-state and low on-state voltage characteristics of the bipolar junction transistor are combined
I c = I mos (1 + β pnp ) (3.19)
with the high input impedance properties of the MOSFET to form the insulated gate bipolar transistor,
+
IGBT, as shown in figure 3.16. The basic structure is that of a MOSFET but with a p implanted into the
drain region. This p+ collector provides reverse blocking capabilities of typically 40V, which can be 3.2.3iii - IGBT at turn-off
enhanced if p-wells through the substrate are used to isolate the die periphery. The gate must be shorted to the emitter or a negative bias must be applied to the gate. When the gate
voltage falls below the threshold voltage, the inversion layer cannot be maintained, and the supply of
3.2.3i - IGBT at turn-on electrons into the n- drift region is blocked, whence, the turn-off process begins. However, the turn-off
When the IGBT is in the forward blocking mode, and if a positive gate bias (threshold voltage) is applied, cannot be quickly completed due to the high concentration minority carrier injected into the n- drift region
which is enough to invert the surface of p-base region under the gate, then an n-type channel forms and during forward conduction. Initially, the collector current rapidly decreases due to the termination of the
current begins to flow. Simultaneously the anode-cathode voltage must be above 0.7V, the potential electron current through the channel (MOSFET turn-off), and then the collector current gradually
barrier, so that it can forward bias the p+ substrate / n- drift junction, J1. The electron current, which flows reduces, as the minority carrier density decays due to recombination in the externally inaccessible n-
from the n+ emitter via the channel to the n- drift region, is the base drive current of the vertical pnp drift region. This storage charge produces a tail current.
transistor. It induces the injection of hole-current from the p+ region to the n- base region. The The operational mechanisms are those of any minority carrier device and result in slower switching
conductivity modulation improves because of this high-level injection of minority carriers holes. This times than the majority carrier MOSFET. On-state voltage and switching characteristics can be
increases the conductivity of the drift region, significantly reducing the drift region resistance, which is significantly improved by using the trench gate technique used on the MOSFET, as considered in section
why the IGBTs can be used in high voltage applications. Two currents flow into the emitter electrode. 3.2.2 and shown in figure 3.15b. A less stable structure improvement involves using wider trenches,
One is the MOS electron-current flowing through the channel, and the other is the bipolar hole-current judiciously spaced, so that accumulated holes under the trench, enhance emitter injection of electrons.
flowing through the p+ body / n- drift junction, J2. This injection enhancement reduces the on-state voltage without degrading the switching performance.

collector
J1 Ic

p+
J1
minority carrier injection n+
collector Icp
Icp Imos n+ buffer
J2 n-

J2
J3 p
J3
n

emitter emitter (a) (b) Si02 (a)

emitter gate
emitter
gate
collector
Ic
Ic αpnp p
J1
minority carrier injection

Icp
Ic Imos n- substrate

αnpn J2
Icp p
J3
n

gate (b)
emitter emitter
(c) (d)
Figure 3.16. Insulated gate bipolar transistor (IGBT):
Figure 3.17. Insulated gate bipolar transistor structures and electric field profile:
(a) circuit symbol; (b) physical structure showing current paths: (c) normal operation equivalent
(a) fieldstop PT-IGBT and (b) conventional NPT-IGBT.
circuit; and (d) high current latching equivalent circuit.
89 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 90

Further performance enhancement is gained by using the punch through, PT-IGBT, structure shown in Mnpn αnpn + Mpnp α pnp = 1 (3.21)
figure 3.17a, which incorporates an n+ buffer region. The conventional non-punch through NPT-IGBT
1
structure is shown in figure 3.17b. Both collector structures can have the same emitter structure, where, as in equation (3.5), M =
whether a lateral gate as shown, or the MOSFET trench gate in figure 3.15b. 1 − (v ce /Vb )m
This dynamic latch-up mode is adversely affected by increased temperature and current magnitude
Figure 3.17 shows the electric field in the off-state, where the PT-IGBT develops a field as in the pin during the voltage rise time at turn-off.
diode in figure 3.2b, which allows a thinner wafer. The NPT-IGBT requires a thicker wafer (about 200µm Since v ce  Vb , M → 1 , and the multiplication effect is not significant in the on-state static latch-up
for a 1200V device) which results in a larger substrate resistance and a slower switching device. analysis. IGBTs are designed and rated so that the latch-up current is at least 10 times the rated current.
• The PT-IGBT has n+ and p+ layers formed by epitaxial growth on an n- substrate. High temperature characteristics (latching current density)
The electric field plot in figure 3.17a shows that the off-state voltage scl With a rise in temperature, the current gains of the npn and pnp transistors increase. This decreases the
consumes the n- substrate and is rapidly reduced to zero in the n+ buffer. latching current level. The effect is aggravated by an increase in the resistance of the p base region due
• The NPT-IGBT has a lightly doped n- substrate with the p-regions (p wells and p to a decrease in hole mobility.
collector) formed by ion implantation. The electric field distribution in figure
3.17b shows that the n- drift region has to be wide enough to support all the 3.2.4 Reverse blocking NPT IGBT
off-state voltage, without punch through to the p collector implant.
The conventional IGBT inherently has reverse voltage blocking capabilities, albeit low. Normally, the
3.2.3iv - IGBT latch-up collector boron ion p+ implant forms a transparent abrupt junction, optimised for on-state voltage and
The equivalent circuit in figure 3.16d shows non-ideal components associated with the ideal MOSFET. turn-off speed.
The parasitic npn bipolar junction transistor (the n+ emitter/ p+ well/ n- drift region are the npn BJT e-b-c) When negative voltage is impressed at the collector in figure 3.16, the p+ substrate / n- drift junction, J1,
and the pnp transistor (p+ collector/ n- drift/ p+ well are the pnp BJT e-b-c) couple together to form an is reverse biased, and the depletion layer expands to the n- drift region. An optimal design in resistivity
and thickness for the n- drift region is necessary in obtaining desirable reverse blocking capability. The
SCR thyristor structure, as considered in section 3.3. Latching of this parasitic SCR can occur:
width of the n- drift region is equivalent to the sum of depletion width at maximum operating voltage and
• in the on-state if the current density exceeds a critical level, which adversely
minority carrier diffusion length. It is necessary to optimize the breakdown voltage while maintaining a
decreases with increased temperature or
narrow n- drift region width, as the forward voltage drop increases with an increase in n- drift region
• during the turn-off voltage rise when the hole current increases in sensitive regions of
width. The following equation is the calculation for the n- drift region width:
the structure due to the charge movement associated with the scl widening.
2εV b
d1 = + Lp (3.22)
1 - IGBT on-state SCR static latch-up is related to the temperature dependant transistor gains which qN D
are related to the BJT base transport factor bt and emitter injection efficiency γi, defined for the BJT in
where d1: n- drift region width
equation (3.2)
Vb: maximum blocking voltage
α pnp + αnpn = bt pnp γ i pnp + bt pnp γ i pnp = 1 (3.20)
ND: doping concentration
Since the conductivity of the drift region under the gate electrode is increased by the introduction of Lp: minority carrier diffusion length =√Dpτp
electron current through the channel, most of the holes injected into the drift region are injected at the p-
body region under the channel and flow to the source metal along the bottom of n+ source. This Processing alternative for reverse blocking
produces a lateral voltage drop across the shunting resistance (Rbe in figure 3.16b) of the p-body layer. If Because the n region surfaces on the emitter side of the device, the uncontrolled field in this region
this voltage drop becomes greater than the potential barrier of the n+ source / p body layer junction, J3, produced by a reverse voltage, causes premature breakdown. To avoid this, the first processing step is
to surround each IGBT die region on the wafer by a deep boron p-well which is selectively driven in from
electrons are injected from the n+ source to the p-body layer, and the parasitic npn transistor (n+ source,
the emitter side. The collector side is mechanically ground to about 100µm, so as to expose to boron
p body and n- drift) is turned-on. If the sum of the two (npn and pnp) parasitic transistors’ current gains
diffusion. The remaining processes are essentially as for the conventional NPT IGBT, which results in a
reach unity in equation (3.20), latch-up occurs.
structure as shown in figure 3.18.
To avoid loss of control and possible IGBT failure, the factors in equation (3.20), which is valid for on- The reverse bias scl is modified and silicon nitride passivation of the emitter surface and an n-channel
state latch-up, are judiciously adjusted in the device design. field stop results in a controlled scl profile, as shown dashed in figure 3.18. Other than increased
processing complexity (hence costs) minimal on-state voltage - switching speed compromise arises.
Common to both device types is the gate structure, hence the base-emitter junction of the npn Effectively, a device with the performance lagging by one technology generation is achieved.
parasitic BJT have the same properties. In each structure, the shorting resistor Rbe decreases the Reverse blocking capability extension to the desirable PT IGBT structure is problematic since the n-
injection efficiency of the npn BJT emitter. This resistance is minimized by highly doping the p+ wells buffer region is of a higher concentration than the n-substrate. Thus the formed pn junction will have a
directly below the n-emitters and by shortening the length of the n-emitter. The gain αnpn in equation significantly lower avalanche breakdown voltage level, as predicted by equation 2.3.
(3.20) is decreased since the injection efficiency γi npn is lowered.
Conventional NPT igbt section reverse E fielded modified
Reduction of the pnp BJT gain of the PT-IGBT and NPT-IGBT is achieved with different techniques.
• For the NPT-IGBT, the emitter injection efficiency of holes from the p+ zone into the n- drift
region is high because of the large difference in doping concentrations at the junction. collector metallization
Adversely this yields a high injection efficiency γipnp. The base transport factor bt pnp is already p+ collector implant
low because of the large width of the n- drift region, and is further reduced by lifetime killing
of minority carriers in the n- drift region by using gold doping or electron beam radiation. n die edge
• For the PT-IGBT, the p+ emitting junction at the collector is a well-controlled shallow implant
thus reducing the injection efficiency γi pnp. Charge carrier lifetime killing in the n- drift region Deep p diffusion
to reduce the base transport factor bt pnp, is therefore not necessary. p from emitter side
n
2 - IGBT turn-off SCR dynamic latch-up can occur while the collector voltage is rising, before the emitter
collector current decreases. When the IGBT is switched off, the depletion layer of the n- drift / p- metal
body junction, J2 in figure 3.17, is abruptly extended, and the IGBT latches up due to the gate 2 p guard rings n channel stop
resulting displacement current. This limits the safe operating area. Equation (3.20) is modified
by equation (3.5) to account for voltage avalanche multiplication effects. Figure 3.18. Reverse voltage blocking NPT-IGBT structure.
91 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 92

3.2.5 Forward conduction characteristics • In a junction FET (JFET), the voltage dependant scl width of a junction is used to
control the effective cross-sectional area of a conducting channel. If the zero bias
Structurally, the IGBT can be viewed as a serial connection of the MOSFET and PiN diode. Alternatively, voltage cuts off the channel then the JFET is normally off, otherwise if a reverse
it is sometimes considered a wide base pnp transistor driven by the MOSFET in a Darlington bias is needed to cut-off the channel, the JFET is termed normally on.
configuration. The former view can be used to interpret the behaviour of the device, but the latter better
describes the IGBT. The electrical properties of SiC make the JFET a viable possibility as a power switch. Two normally on
The width of the undepleted n- drift region does not change rapidly with the increase in the collector JFET structures are shown in figure 3.19, where it is seen how the scl layer decreases the channel width
voltage due to the high concentration of the buffer layer, but maintains the same width as the n+ buffer as the source to gate voltage reverse bias increases. In SiC, the channel has a positive temperature
layer for all collector voltages. This results in a constant value of the pnp transistor’s current gain. coefficient, Ron ∝ T 2.6 , hence parallel die connection is viable. Natural current saturation with a positive
Additionally, the n+ buffer layer reduces the injection efficiency of the p+ substrate / n+ buffer junction, temperature coefficient means lengthy short-circuit currents of over a millisecond can be sustained.
J1. This reduces the current gain of the pnp transistor. Also, the collector output resistance can be Although the channel is bidirectional, in the biased off-state an integral fast, robust pn body diode is
increased with electron irradiation to shorten the minority carrier lifetime, which reduces the diffusion inherent as seen in figure 3.19b. The natural off-state properties of the MOSFET make the SiC variant
length. The IGBT saturated collector current expression involves the MOSFET current given by equation more attractive than the JFET. The simpler JFET structure has revived interest in its SiC fabrication.
(3.7), giving: s o u rc e s o u rc e
- + -
1 W g a te g a te
Id = × ½ µ c C a (V gs −VTh )2 (A) (3.23) m e ta l
1 − α pnp Lc + +
n n n+
Transconductance in the active region is obtained by differentiating the drain current with respect to Vge.
The IGBT’s saturated collector current and transconductance are higher than those of the power
MOSFETs of the same aspect ratio (Wc /Lc). This is because the pnp transistor’s current gain αpnp is - + + -
n p p n
significantly less than 1.
scl scl (a )
∂I d 1 Wc
g fs  = ×µ C a (V gs −VTh ) (mho) (3.24)
∂V gs V 1 − α pnp Lc channel
ds = constant
+
n
3.2.6 PT IGBT and NPT IGBT comparison
m e ta l
s
d r a in
Generally, faster switching speed is traded for higher on-state losses, and vice versa. g

s o u rc e s o u rc e
The N+ buffer layer improves turn-off speed by reducing minority carrier injection and by increasing the g a te

recombination rate during the switching transition. In addition, latch-up characteristics are improved by
p d
reducing the PNP transistor current gain. The trade-off is that the on-state voltage increases. However, n
+
n
+
p
+
p+
the thickness of the N- drift region can be reduced with the same forward voltage blocking capability
because the N+ buffer layer improves the forward voltage blocking capability. As a result, the on-state
voltage can be decreased. Hence, the PT-IGBT has superior trade-off characteristics as compared to -
n d r ift r e g io n
(b )
the NPT-IGBT in switching speed and forward conduction voltage. Most IGBTs are PT-IGBTs. The IGBT
static forward and reverse blocking capabilities for both types are similar because these characteristics
are determined by the same N- drift layer thickness and resistance. The reverse-blocking voltage of PT- n b u ffe r

IGBTs that contain the N+ buffer layer between the P+ substrate and N- drift region is lowered to tens of 4 H n + s u b s tr a te
volts due to the heavy doping regions bounding J1.

Table 3.1: PT IGBT versus NPT IGBT

b o d y d io d e
d r a in
IGBT TYPE PT IGBT NPT IGBT
Higher vce(sat) Figure 3.19. Cross-section of the SiC vertical junction field effect transistor:
Lower vce(sat) (a) trench gate with channel shown and (b) variation incorporating a pn body diode.
conduction loss Decreases slightly with temperature
(same switching speed) A slight positive temperature co-efficient at high Increases with temperature
current densities allows parallel connection. Suitable for parallel connection 3.3 Thyristors

switching speed Faster switching due to high gain The name thyristor is a generic term for a bipolar semiconductor device which comprises four
(same on-state loss) and reduced minority carrier lifetime semiconductor layers and operates as a switch having a latched on-state and a stable off-state.
More rugged due to wider base Numerous members of the thyristor family exist. The simplest device structurally is the silicon-controlled
short circuit rating rectifier (SCR) while the most complicated is the triac.
and low pnp gain
turn-on switching loss Largely unaffected by temperature Largely unaffected by temperature 3.3.1 The silicon-controlled rectifier (SCR)
Loss increases with temperature
turn-off switching loss Virtually constant with temperature The basic SCR structure and doping profile in figure 3.20 depicts the SCR as three pn junctions J1, J2,
but start lower than NPT devices
and J3 in series. The contact electrode to the outer p-layer is called the anode and that to the outer n-
layer is termed the cathode. With a gate contact to the inner p-region, the resultant three-terminal, 4
layer thyristor device is technically called the silicon-controlled rectifier (SCR).
3.2.7 The junction field effect transistor (JFET) A low concentration n-type silicon wafer is chosen as the starting material. A single diffusion process
is then used to form simultaneously the p1 and p2 layers. Finally, an n-type layer, n1, is diffused
The field effect for a FET may be created in two ways: selectively into one side of the wafer to form the cathode. The masked-out areas are used for the gate
• A voltage signal controls charge indirectly using a capacitive effect as in the contact to the p1 region. To prevent premature breakdown at the surface edge, bevelling is used as in
MOSFET, section 3.2.2. figure 3.1, to ensure that breakdown will occur uniformly in the bulk.
93 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 94

A number of observations can be made about the doping profile of the SCR which relate to its I c 1 = α1 I K + I co 1
electrical characteristics. By equating Ib2 and Ic1
The anode and cathode would both be expected to be good emitters of minority carriers into the n2
and p1 regions respectively because of their relative high concentrations with respect to their injected (1 - α2 )I A - I co 2 = α1 I K + I co 1
regions. Since IK = IA + IG
The n2 region is wide, typically hundreds of micrometres, and low concentration, typically less than
1014 /cc. Even though the hole lifetime may be long, 100µs, the base transport factor for hole minority α1 I G + I co 1 + I co 2 α1 I G + I co 1 + I co 2
IA = = (A) (3.25)
carriers, bt-n2 is low. The low-concentration provides high forward and reverse blocking capability and the 1 - (α1 + α 2 ) 1 - GT
associated reverse-biased scl’s penetrate deeply into the n2 region. Gold lifetime killing or electron
irradiation, most effective in the n2 region, is employed to improve the switching speed by increasing the where α1 + α2 is called the loop gain, GT.
number of carrier recombination centres.

Ib2 = α1IK

Ib1

Figure 3.21. Cross-section of the SCR showing its model derivation:

(a) schematic of the SCR cross-section; (b) the division of the SCR into two transistors; and
(c) the npn-pnp two-transistor model of the basic SCR.

At high voltages, to account for avalanche multiplication effects, the gains are replaced by Mα, where M
is the avalanche multiplication coefficient in equation (3.21). Hence, GT becomes M1α1 + M2α2. By
inspection of equation (3.25) a large anode current results when GT → 1, whence the circuit regenerates
with each transistor driving its counterpart into saturation. All junctions are forward-biased and the total
device voltage is approximately that of a single pn junction, with the anode current limited by the
external circuit. The n2-p1-n1 device acts like a saturated transistor and provides a remote contact to the
n2 region. Therefore the device behaves essentially like a p-i-n diode (p2-i-n1), where the voltage drop
across the i-region is inversely proportional to the recombination rate. Typical SCR static I-V
characteristics are shown in figure 3.22.

Figure 3.20. The silicon-controlled rectifier, SCR:

(a) net impurity density profile; (b) circuit symbol; and (c) cross-sectional view.

The two-transistor model of the SCR shown in figure 3.21 can be used to represent the p2-n2-p1-n1
structure and explain its electrical and thermal characteristics. Transistor T1 is an npn BJT formed from
regions n2-p1-n1 while T2 is a co-joined pnp BJT formed from SCR regions p2-n2-p1.
The application of a positive voltage between the anode and cathode does not result in conduction
because the SCR central junction J2 is reverse-biased and blocking. Both equivalent circuit transistors
have forward-biased emitter junctions and with reverse-biased collector junctions, both BJT’s can be
considered to be cut off.

3.3.1i - SCR turn-on

It is evident from figure 3.21c that the collector current of the npn transistor provides the base current for
the pnp transistor. Also, the collector current of the pnp transistor along with any gate current IG supplies Figure 3.22. The silicon-controlled rectifier static I-V characteristics.
the base drive for the npn transistor. Thus a regenerative current situation occurs when the loop gain
exceeds unity.
The base current of the pnp transistor T2 with dc current gain α2 is At low current levels, α1 and α2 are small because of carrier recombination effects, but increase
I b 2 = (1 - α2 ) I A - I co 2 rapidly as the current increases. The conventional gate turn-on mechanism is based on these current
gain properties. External gate current starts the regeneration action and the subsequent increase in
which is supplied by the collector of the npn transistor. The current Ico is the collector junction reverse
anode current causes the gains to increase, thus ensuring a high loop gain, whence the gate current
bias leakage current. The collector current of the npn transistor T1 with a dc current gain of α1 is given by
can be removed. The I-V characteristics in figure 3.22 show this property, where a minimum anode
95 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 96

current (latching current) IL is necessary for the loop gain to increase sufficiently to enable the SCR to The cathode-anode, reverse breakdown voltage VBR is shown in figure 3.22. The anode p2+n2 junction
latch on by the regeneration mechanism. J1 characterises SCR reverse blocking properties and VBR is given by (equation (3.6))

The SCR can be brought into conduction by a number of mechanisms other than via the gate (excluding VBR = V b (1 - α 2 )1/m
the light triggered SCR used in high-voltage dc converters). If a high resistivity n2 region, NDn2, is used (in conjunction with low temperature) and breakdown is due
• If the anode-cathode voltage causes avalanche multiplication of the central junction, the to punch-through to J2, then the terminal breakdown voltage will be approximated by (equation (2.2))
increased current is sufficient to start the regenerative action. The forward anode-cathode VPT = 7.67 × 10-16 N Dn2 Wn22
breakover voltage VBF is dependent on the central junction J2 avalanche voltage and the loop
gain GT according to where Wn2 is the width of the n2 region. This relationship is valid for both forward and reverse SCR
VBF = V b (1 - α1 - α 2 )1/m = V b (1 - G T )1/m (V) (3.26) voltage breakdown arising from punch-through.
where the avalanche breakdown voltage, at room temperature, for a typical SCR p+n central
junction J2 is given by equation (2.3)
V b = 5.34 × 1013 × N D-¾ (V) (3.27)
where ND is the concentration of the high resistivity n2 region when 1013 < ND < 5x1014 /cc.
• Turn-on can also be induced by means of an anode-to-cathode applied dv/dt where the peak
ramp voltage is less than VBF. The increasing voltage is supported by the central blocking
junction J2. The associated scl width increases and a charging or displacement current flows
according to i = d(Cv)/dt. The charging current flows across both the anode and cathode
junctions, causing hole and electron injection respectively. The same mechanism occurs at the
cathode if gate current is applied; hence if the terminal dvldt is large enough, SCR turn-on
occurs.
• The forward SCR leakage current, which is the reverse-biased pn junction J2 leakage current,
doubles approximately with every 8K temperature rise. At elevated temperatures, the thermally
generated leakage current (in conjunction with the gains increasing with temperature and
current) can be sufficient to increase the SCR loop gain such that turn-on occurs.

3.3.1ii - SCR cathode shorts

All SCR turn-on mechanisms are highly temperature-dependent. A structural modification commonly
Figure 3.24. The amplifying gate SCR:
used to reduce device temperature sensitivity and to increase dv/dt rating is the introduction of cathode
(a) cross-section of the structure and (b) two-SCR equivalent circuit.
shorts. A cross-sectional structure schematic and two-transistor equivalent of the cathode shorting tech-
nique are shown in figure 3.23. The cathode metallization overlaps the p1 region, which is the gate
contact region. The technique is based on some of the anode forward-blocking current being shunted 3.3.1iii - SCR amplifying gate
from the cathode junction via the cathode short. The cathode electron injection efficiency is effectively At SCR turn-on, only a small peripheral region of the cathode along the gate region conducts initially.
reduced, thereby decreasing α1 which results in an increase in the forward voltage-blocking rating VBF The conducting area spreads at about 50m/s, eventually encompassing the whole cathode area. If at
and dv/dt capability. The holding and latching currents (IH and IL) are also increased. turn-on a large anode current is required, that is a high initial di/dt, a long gate-cathode perimeter is
necessary in order to avoid excessively high, localised initial cathode current densities. The usual
method employed to effectively enlarge the SCR initial turn-on area is to fabricate an integrated
amplifying gate, as shown in figure 3.24. A small gate current is used to initiate the pilot SCR, which
turns on rapidly because of its small area. The cathode current of this pilot SCR provides a much larger
gate current to the main SCR section than the original gate triggering current. Once the main device is
fully on, the pilot device turns off if the gate current is removed.
An important property of the SCR is that once latched on, the gate condition is of little importance.
The regenerative action holds the device on and SCR turn-off can only be achieved by reducing the
anode current externally to a level below which the loop gain is significantly less than unity.

3.3.2 The asymmetrical silicon-controlled rectifier (ASCR)

The doping profiles and cross-sectional views comparing the asymmetrical SCR and conventional SCR
are shown in figure 3.25. In each case the electric field ξ within the p1n2 junction reverse-bias scl is
shown and because the n2 region is lightly doped, the scl extends deeply into it. The scl applied
reverse-bias voltage is mathematically equal to the integral of the electric field, ξ (area under the curve).
If, in the conventional SCR, the scl edge reaches the p2+ layer, then punch-through has occurred and the
-
SCR turns on. To prevent such a condition and to allow for manufacturing tolerances, the n2 region is
kept thick with the unfortunate consequence that on-state losses, which are proportional to n2 layer
thickness, are high.
Figure 3.23. Shorted cathode SCR: In the case of the ASCR, a much thinner n2- region is possible since a highly doped n layer adjacent to
(a) SCR cross-section showing some anode current flowing through cathode shorts and the p2+ anode is utilised as an electric field stopper. The penalty for this layer construction is that in the
(b) the SCR two-transistor equivalent circuit SCR with cathode shorts. reverse voltage blocking mode, the n2p2+ junction avalanches at a low voltage of a few tens of volts.
Thus the ASCR does not have any usable repetitive reverse-blocking ability, hence the name
asymmetrical SCR. By sacrificing reverse-blocking ability, significant improvements in lower on-state
voltage, higher forward-blocking voltage, and faster turn-off characteristics are attained.
97 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 98

Figure 3.26. Reverse conducting thyristor with an amplifying gate structure:

(a) cross-section of the structure and (b) typical doping profile of the SCR section.

Figure 3.25. Doping profile, cross-section, and the electric field of J2 in the forward biased off-state
for: (a) and (b) the conventional SCR; (c) and (d) the asymmetrical SCR.
3.3.4 The bi-directional-conducting thyristor (BCT)

Two anti-parallel connected SCRs can be integrated into one silicon wafer, as shown in figure 3.27. As a
result of integrated symmetry, both devices have near identical electrical properties. The mechanical
3.3.3 The reverse-conducting thyristor (RCT)
feature different to the triac, is that there are two gates – one on each side of the wafer. Also, unlike the
triac, the two SCR sections are physically separated in the wafer to minimise carrier diffusion interaction.
The RCT is electrically equivalent to an SCR in anti-parallel with a diode, but both are integrated into the
The equivalent circuit comprises two SCRs connected in anti-parallel. As such, one device turning off
same wafer. The reason for integrating the SCR and diode is to minimise external interconnecting lead
and supporting a negative voltage, represents a positive dv/dt impressed across the complementary
inductance. The circuit symbol, cross-sectional wafer view, and doping profile are shown in figure 3.26.
device, tending to turn it on. Also, any charge carries which diffusion from the SCR previously on,
exasperate the dv/dt stress experienced by the off SCR.
Since no reverse voltage will be applied to the RCT there is only the cathode-side deep p-diffused
The two central amplifying gate structures are as for the RCT, in figure 3.26a. A separation of a few
layer. This and the ASCR n-region type field stopper result in low forward voltage characteristics. As in
minority carrier lateral diffusion lengths, along with an increased density of cathode shorts along the
the ASCR case, the highly n-type doped anode end of the wide n-region also allows higher forward
separating edge of each cathode and in the amplifying gate region close to the anode of the
voltages to be blocked. Both anode and cathode shorts can be employed to improve thermal and dv/dt
complementary SCR, enhance the physical separation. The amplifying gate fingers are angled away
properties. As shown in figure 3.26a, an amplifying gate can be used to improve initial di/dt capability.
from the separation regions to minimise the shorting effect of the complementary SCR anode emitter
shorting.
The integral anti-parallel diode comprises an outer ring and is isolated from the central SCR section
The on-state voltage of each SCR is fine tuned, match for on-state loss, using electron irradiation.
by a diffused guard ring, or a groove, or by irradiation lifetime control techniques. The guard ring is
important in that it must confine the carriers associated with the reverse-blocking diode to that region so
that these carriers do not represent a forward displacement current in the SCR section. If the carriers
3.3.5 The gate turn-off thyristor (GTO)
were to spill over, the device dv/dt rating would be reduced - possibly resulting in false turn-on.
The gate turn-off thyristor is an SCR that is turned on by forward-biasing the cathode junction and turned
Gold or irradiation lifetime killing can be employed to reduce the turn-off time without significantly off by reverse-biasing the same junction, thereby preventing the cathode from injecting electrons into the
increasing the on-state voltage. p1 region. Other than its controlled turn-off properties, the GTO’s characteristics are similar to the
conventional SCR. The basic structure and circuit symbol are shown in figure 3.28.
99 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 100

The turn-off gain of the GTO, βQ, is defined as the ratio of anode current IA to reverse gate current IGQ,
that is
βQ ≡ I T / I GQ
(3.28)
< α1 / (α1 + α 2 - 1) = α1 / (GT - 1)
Thus for high turn-off gain it is important to make α1 for the npn section as close to unity as possible,
while α2 of the pnp section should be small. A turn-off current gain of 5 is typical.

During the turn-off process, the conducting plasma is squeezed to the centre of the cathode finger,
since the lateral p1 region resistance causes this region to be last in changing from forward to reverse
bias. This region has the least reverse bias and for reliable GTO operation, the final area of the
squeezed plasma must be large enough to prevent an excessive current density. Device failure would
be imminent because of localised overheating.

The doping profile is characterised by a low p1 region sheet resistance and an inter-digitated cathode
region to ensure even distribution of the reverse bias across the cathode junction at turn-off. Both turn-
off and temperature properties are enhanced by using an anode shorting and defocusing technique as
shown in figure 3.29a, but at the expense of reverse-blocking capability and increased on-state voltage.

The shown two-level cathode and gate metallization used on large-area devices allow a flat metal
disc plate for the cathode connection. As with the conventional SCR, a reverse conducting diode
structure can be integrated, as shown in figure 3.29b.
Figure 3.27. Cross-section structure of the bidirectional conducting phase-control SCR
with an amplifying gate structure.
3.3.6 The gate commutated thyristor (GCT)

GTO frequency limitations and the need for an external parallel connected capacitive turn-off snubber (to
3.3.5i - GTO turn-off mechanism limit re-applied dv/dt), have motivated its enhancement, resulting in the gate commutated thyristor, GCT.
In the on-state, due to the high injection efficiency of junctions J1 and J3, the central p-base is flooded As shown in figure 3.29c, a number of processing and structural variations to the basic GTO result in a
with electrons emitted from the n-cathode and the central n-base is flooded with holes emitted from the more robust, snubberless, and versatile high power switch.
p-anode. If a reverse gate current flows from the cathode to the gate, with a driving voltage tending to
reverse bias the gate-cathode junction – then p-base holes are extracted from the gate, suppressing the • n-type buffer
cathode junction from injecting electrons. Eventually the cathode junction is cut-off and the pnp An n-type buffer layer allows a thinner n-drift region. A 40% thinner silicon wafer, for the same
transistor section, now without base current turns off, thereby turning off the GTO. blocking voltage, reduces switching losses and the on-state voltage. An integral reverse
The turn-off mechanism can be analyzed by considering the two-transistor equivalent circuit model conducting diode is also possible, as with the conventional SCR and GTO.
for the SCR shown in figure 3.21c. The reverse gate current IGQ flows from the gate and is the reverse • transparent emitter
base current of the npn transistor T1. The base current for transistor T1 is given by A thin lightly doped anode p-emitter is used instead of the normal GTO anode shorts. Some
I B = α 2I A − I GQ , where I GQ = −I G . The reverse base current in terms of the gain of T1 is I RB = (1 − α1 )I K . electrons pass through the layer as if the anode were shorted and recombine at the anode
The GTO as a three terminal device must satisfy I A = I K + I GQ and to turn-off the GTO, IB < IRB. These contact metal interface, without causing hole emission into the n-base. Effectively, a reduced
conditions yield emitter injection efficiency is achieved without anode shorts. Consequently, gate current
(α1 + α 2 − 1) I A = (GT − 1) I A < α 2 IGQ triggering requirements are an order of magnitude lower than for the conventional GTO.
• low inductance
A low inductance gate structure, contact, and wafer assembly (<2µH) allow the full anode
current to be shunted from the gate in less than ½µs, before the anode voltage rises at turn-off.

3.3.6i - GCT turn-off

Unity turn-off gain, βQ = 1, means the modified GTO turns off as a pnp transistor without base current,
since the cathode junction is cut-off. Without npn BJT regenerative action, the pnp transistor rapidly
traverses the linear region, thus eliminating the need for a capacitive turn-off snubber in the anode
circuit. The high reverse gate current results in a short saturation delay time, enabling the accurate turn-
off synchronisation necessary for devices to be series connected.

3.3.6ii - GCT turn-on

With high gate current, turn-on is initially by npn BJT action, not SCR regeneration. The pnp transistor
section is inoperative since the carriers in the n-base are initially ineffective since they require a finite
time to transit the wide n-base.
The SCR on-state regenerative mechanism is avoided at both turn-off and turn-on switching
transitions thereby yielding a device more robust than the GTO thyristor.
As with the GTO, an inductive series turn-on snubber is still required to cope with the initial high di/dt
current. The GCT switch is thermally limited, rather than frequency limited as with the conventional GTO.

Figure 3.28. The gate turn-off thyristor: Electron irradiation trades on-state voltage against switching performance.
(a) circuit symbol and (b) the basic structure along an interdigitated finger showing plasma focussing
in the p1 region at the cathode junction at turn-off.
101 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 102

gate
cathode

J3

n
+ J2
p
J1
n-

n+ p n+ p n+ p n+ p n
+

anode
diode GTO
(a) (b)

gate anode
Figure 3.30. Two views of the typical triac structure,
showing main terminal M1 and M2, and a single gate.
+
n
p p
The four different trigger modes of the triac are illustrated in figure 3.32 and the turn-on mechanism for
each mode is as follows.
-
n
(a) M2 positive, Ig positive (Mode I)
The main terminal M2 is positive with respect to M1 and gate current forward-
biases the p2-n2 junction, J3. The active main SCR section is p1-n1-p2-n2.
n+ + (c)
p n Turn-on is that for a conventional SCR, as shown in figure 3.32a.
(b) M2 positive, Ig negative (Mode II)
In figure 3.32b, M2 is positive with respect to M1 but negative gate voltage is
cgt cathode diode applied. Junction J4 is now forward-biased and electrons are injected from n3
into p2. A lateral current flows in p2 towards the n3 gate and the auxiliary SCR
Figure 3.29: GTO structure variations: section p1-n1-p2-n3 turns on as the gain of the n3-p2-n1 transistor section
(a) schematic structure of GTO finger showing the anode defocusing shorts, n+; increases. Current flow in this auxiliary SCR results in a current flow across J3
(b) an integrated diode to form a reverse conducting GTO; and into n2, hence piloting the SCR p1-n1-p2-n2 into conduction.
(c) the reverse conducting gate commutated thyristor GCT. (c) M1 positive, Ig negative (Mode III)
Figure 3.32c shows the bias condition with M2 negative with respect to M1 and
the gate negative with respect to M1 such that J4 is forward-biased and
3.3.7 The light triggered thyristor (LTT) electrons are injected from n3 into the p2 region. The potential in n1 is
lowered, causing holes to be injected from p2 into the n1 layer which provide
The light triggered thyristor is series connected in HVDC applications. Five inch wafers, after 16 major base current for the p2-n1-p1 transistor section. This brings the p2-n1-p1-n4
processing steps (as opposed to 10 for the conventional high voltage thyristor), offer 8kV ratings with SCR into conduction.
on-state voltages of 2.3V at 3000A, with surge ratings of up to 63kA. Turn-off time is 350µs, and turn-on (d) M1 positive, Ig positive (Mode IV)
requires about 40mW of light power for 10µs, with a half microsecond rise time. The light causes the When M2 is negatively biased with respect to M1 and the gate is positively
generation of hole-electron pairs and these free charges create a change in the electrical characteristics biased such that J3 is forward-biased, as in figure 3.32d, electrons are injected
of the semiconductor region. Consequently a current flows across the exposed junction which is from n2 to p2 and diffused to n1. This increases the forward bias of J2 and
equivalent to gate current. Because of the low turn-on energy, multiple cascaded amplifying gates are eventually the SCR section p2-n1-p1-n4 comes into full conduction.
laterally integrated to achieve modest initial current rises limited to 300A/µs. Reapplied voltages are
limited to 3500V/µs. The various turn-on mechanisms are highly reliant on the judicious lateral separation of the various
A temperature dependant over voltage protection mechanism is also integrated into the wafer, the contacts and regions. The main advantage of the triac lies in the fact that two anti-parallel SCR’s in the
characteristics of which suffer from a wide production spread. one silicon structure can be triggered into conduction from the one gate. Because of the need for extra
structure layers, hence processing steps, some conventional SCR characteristics are sacrificed and poor
device area utilisation results. Two anti-parallel SCRs therefore tend to be more robust than a triac but
3.3.8 The triac unlike the BCT device in section 3.3.4, only one gate drive circuit is needed for the triac.

Pictorial representations of the triac are shown in figure 3.30. The triac is a thyristor device that can
switch current in either direction by applying a low-power trigger current pulse of either polarity between
the gate and main terminal M1. The main terminal I-V characteristics, device symbol, and four trigger
modes for the triac are shown in figure 3.31.
The triac comprises two SCR structures, p1-n1-p2-n2 and p2-n1-p1-n4 which utilise the n3 and p2
regions for turn-on. It should be noted that n2-p2, p1-n4, and p2-n3 are judiciously connected by terminal
metallizations, but are laterally separated from their associated active parts.
103 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 104

M2 positive
positive half cycle

IGT IGT
negative positive

IGT IGT
negative positive

M2 negative
negative half cycle

Figure 3.32. Current flow for the four different turn-on triggering modes of the triac.
Figure 3.31. The triac:
(a) I-V characteristics and circuit symbol and (b) its four firing modes.
3.4 Power packages and modules

Power thyristors are usually encapsulated as a floating disk in a ceramic package with Cu connection
disks, as in figure 5.45. This offers the following features compared with high current IGBT modules.
• increased reliability with power cycling failure decreased by a factor of 10
• lower packaging connection and internal inductance
• explosion rated and stable short circuit failure mode
• suitable for liquid immersion
• lower thermal resistance due to double sided cooling
105 Power Electronics Chapter 3 Power Switching Devices and their Static Electrical Characteristics 106

Advantageous features of high current IGBT modules are an electrically isolated base plate (based on blank
Aℓ3N4 or Aℓ203)) and low cost connections and heatsink mounting (see figures 5.8 and 5.65). The
relative features of aluminium oxide and aluminium nitride substrates can be found in Chapter 5.23. No
isolated pressure clamping arrangement is necessary with flat pack IGBT modules.

The emergence of SiC power switching devices has presented packaging challenges. Package internal
substrate and base plate assemblies currently prevent the high temperature capabilities of SiC from
being exploited at junction temperatures above 300°C.

Details of high temperature die and substrate attachment can be found in Chapter 5.27.

Reading list
Baliga, B. J., Modern Power Devices, John Wiley-Interscience, 1987.
Blicher, A., Thyristor Physics, Springer, New York, 1976.
Ghandhi, S. K., Semiconductor Power Devices, John Wiley-Interscience, New York, 1977.
Grafham, D. R. et al., SCR Manual, General Electric Company, 6th edition, 1979.
Van Zeghbroeck, B., Principles of Semiconductor Devices,
http://ece-www.colorado.edu/~bart/book, 2004.