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EEE112 Integrated Electronics and Design
NMOS IC Design Project (Version 2025)
Date
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5. Main Body 4 (Extra): Full Circuit Layout with TSMC 3nm Technology Using MOSIS
Design Rules
For the NMOS -based logic gate, the whole circuit was designed in TSMC’s 3nm process
technology, with 2λ set to 3nm. Placing active, poly-silicon, contact, and metal layers in one
layout creates a MOSIS-compliant integrated circuit. The objective was to build a simple design
that uses the W/L ratio for NMOSFETs obtained at VOUT of 0.2 V . the following is important
guidelines for the layout:
Table: Full Circuit Layout Design Parameters Using MOSIS Rules (TSMC 3nm Technology)
Mask Function Relevant MOSIS Dimension at Notes
Layer Rules 3nm Node
Mask 1: Defines source R1: Min width = 3λR2: Width ≥ Forms diffusion areas of
Active and drain regions Min spacing = 3λ 9nmSpacing ≥ NMOSFETs
9nm
Mask 2: Forms gate R3: Min width = 2λR4: Width ≥ Poly crosses active to form
Poly-Silicon terminals Min spacing = 2λR5: 6nmSpacing ≥ the gate channel
Gate overlaps active = 6nmOverlap =
2λ 6nm
Mask 3: Creates openings R10: Contact size = Size = 6nm × Contacts to gate, source, and
Contact for electrical 2λR11–R20: Spacing 6nmVarious drain regions
connection rules spacing rules
Mask 4: Routes power R8: Min width = 3λR9: Width ≥ Used for interconnections,
Metal and signal lines Min spacing = 3λ 9nmSpacing ≥ VDD and GND rails per R21,
9nm R22
Full Layout Combined view All applicable above Scaled with λ = Compact, rule-compliant,
(Merged) of all 4 masks 1.5nm manufacturable layout for
3nm CMOS technology
Mask 1: Active Layer
The Nwell region helps establish the source and drain areas for diffusion through elevated doped
atoms. To allow for consistency in the process and reduce parasitic capacitance, the minimum
width and spacing used in design was kept at 3 λ(9 nm) following both MOSIS rules R 1and R 2.
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Mask 2: Poly-Silicon Gate Layer
The gates of the transistor are created when poly lines cross the active areas. According to R3–
R5, the poly width and spacing are both 2 λ(6 nm), and the gate totally covers the active region
by 2 λ for a properly formed channel. At the midpoint of the active, poly crossing is used to keep
gates regularly.
Mask 3: Contact Layer
In this design, 2 λ ×2 λ contact holes (6 nm× 6 nm)are provided to link the gate, drain, and source
regions to the metal lines. In contact-to-poly, contact-to-metal, and contact-to-active spacings,
Rules R 10 through R 20 ensure that short circuits and mask misalignments do not occur.
Mask 4: Metal Layer
Metal lines act as links for the electrical circuit. All metal crossings follow the rule of being at
least 9nm wide in R8 and R9 layers. Both VDD and GND rails are made wider according to Rule
R 21 and R 22 for improved flow of electricity.
Final Layout
The four masks lay perfectly side by side so that all the spacing and overlap rules were met. With
this design, production is possible at 3nm and accurate logic in NMOS is achieved while
ensuring manufacturing efficiency.
