LAB MANUAL

LOGIC CIRCUIT DESIGN LAB

Department of Electronics and Communication

Engineering
CET
 LOGIC CIRCUIT DESIGN LAB

INDEX

PART A

1. Realization of functions using basic gates (SOP and POS forms)

2. Design and Realization of half /full adder and subtractor using basic gates and universal
gates.
3. 4-bit adder/subtractor and BCD adder using 7483.
4. Study of Flip Flops: S-R, D, T, JK and Master Slave JK FF using NAND gates.
5. Asynchronous Counter:3 bit up/down counter and Mod-N counter
6. Synchronous Counter: Realization of 3-bit up/down counter and Mod-N counter.
7. Ring counter and Johnson Counter.
8. Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)
9. Realization of combinational circuits using MUX & DEMUX.

PART B

1. Realization of Logic Gates and Familiarization of FPGAs

2. Adders in Verilog
3. Mux and Demux in Verilog
4. Flipflops and counters
5. Multiplexer and Logic Implementation in FPGA
6. Flip-Flops and their Conversion in FPGA
7. Asynchronous and Synchronous Counters in FPGA
8. Sequence generrators
9. Counters using IC

Department of ECE, CET 2

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 1 REALIZATION OF FUNCTIONS USING BASIC AND UNIVERSAL

GATES (SOP AND POS FORMS)
DATE:
AIM: Realize the given Boolean function using logic gates in both SOP and POS forms.
Two input SOP -
Two input POS: -
COMPONENTS AND EQUIPMENTS REQUIRED:
Sl Components and
Specification Quantity
No equipments
1 IC Depending upon
the function
2 IC trainer kit 1

THEORY:
SOP: - It is the Sum of product form in which the terms are taken as 1. It is denoted in the K-map
expression by sigma (∑)

Logic Circuit Diagram Of this expression:-

The Truth Table for this SOP expression

POS: - It is the product of the sums form in which the terms are taken as 0. It is denoted in the
K-Map expression by the Sign pie (π)

Department of ECE, CET 3

 LOGIC CIRCUIT DESIGN LAB

Logic Circuit Diagram Of this expression:-

Truth table

PROCEDURE:
1. Test all the components and IC packages using a digital tester and assure that the wires
are in good condition using multimeter.
2. Verify the dual in line package pinout of the IC before feeding the inputs.
3. Set up the circuits and observe the outputs. Enter the output states in truth table
corresponding to the input combination.

RESULT: Realized the Boolean functions using logic gates in both SOP and POS forms.

Department of ECE, CET 4

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 2 DESIGN AND REALIZATION OF HALF/FULL ADDER AND

SUBTRACTOR USING BASIC GATES AND UNIVERSAL GATES.
DATE:
AIM: To design and setup Half/Full Adder and Subtractor using basic gates and universal gates.

COMPONENTS AND EQUIPMENTS REQUIRED:

SL NO: COMPONENTS AND EQUIPMENTS SPECIFICATION QUANTITY
1. IC Trainer kit 1
2. IC 7408 1
7432 1
7486 1
7400 2
7404 1

THEORY:
Half Adder: The simplest binary adder is called a half adder. Half adder has two input bits and
two output bits. One output bit is the sum and the other is carry. They are represented by S and C
in the logic symbol.
S=A B
C = AB
Full Adder: A half adder has no provision to add a carry from the lower order bits when binary
numbers are added. When two input bits and a carry are to be added, the number of input bits
becomes three and the input combinations increases to eight. For this, a full adder is used. Like
half adder, it also has a sum bit and a carry bit. The new carry generated is represented by �� and
carry generated from the previous addition is represented by ��−1.

Department of ECE, CET 5

 LOGIC CIRCUIT DESIGN LAB

S=A B ��−1 .
�� = �� + ��−1 (A B)
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the half-
Subtractor are:

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean
functions describing the full-subtracter are:

PROCEDURE:
1. Verify whether all the components and wires are in good condition.
2. Set up the half adder circuit and feed the input bit combinations.
3. Observe the output corresponding to input combinations and enter it in the truth table.
4. Repeat the above steps for all circuits.

HALF ADDER

I/P O/P

A B C D
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Realisation Of Sum and Carry

S =A B C=A.B

Department of ECE, CET 6

 LOGIC CIRCUIT DESIGN LAB

HALF ADDER USING X-OR AND NAND GATE

FULL ADDER
Logic Symbol
Input Output
�� �� ��−1 �� ��

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

FULL ADDER USING X-OR GATE AND NAND GATE

Please draw half adder and full adder circuit using NAND Gates

Department of ECE, CET 7

 LOGIC CIRCUIT DESIGN LAB

1.

CIRCUIT DIAGRAM USING BASIC GATES:

Department of ECE, CET 8

 LOGIC CIRCUIT DESIGN LAB

CIRCUIT DIAGRAM USING BASIC GATES:

Please draw half Subtractor and full subtractor circuit using NOR Gates

RESULT:
The circuit for half/full adder and subtractor were setup and the output for various combinations
of input are observed.

Department of ECE, CET 9

 LOGIC CIRCUIT DESIGN LAB

EXPT NO. 3 4 BIT ADDER/SUBTRACTOR AND BCD ADDER USING 7483

DATE :
AIM:
To design and implement 4-bit adder / subtractor and BCD adder using IC 7483.
COMPONENTS AND EQUIPMENTS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1

THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It can be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the
addend bits of ‘B’ are designated by subscript numbers from right to left, with subscript 0
denoting the least significant bits. The carries are connected in chain through the full adder. The
input carry to the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input

Department of ECE, CET 10

 LOGIC CIRCUIT DESIGN LAB

carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be
represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4-bit adder to produce the binary
sum.
PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER

Department of ECE, CET 11

 LOGIC CIRCUIT DESIGN LAB

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

Department of ECE, CET 12

 LOGIC CIRCUIT DESIGN LAB

TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

Department of ECE, CET 13

 LOGIC CIRCUIT DESIGN LAB

LOGIC DIAGRAM:

BCD ADDER

Department of ECE, CET 14

 LOGIC CIRCUIT DESIGN LAB

K MAP ?

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C

PROCEDURE:

Department of ECE, CET 15

 LOGIC CIRCUIT DESIGN LAB

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT: The circuit for 4-bit adder / subtractor and BCD adder using IC 7483 were setup and
the output for various combinations of input are observed.

Department of ECE, CET 16

 LOGIC CIRCUIT DESIGN LAB

EXPT NO:4 STUDY OF FLIP FLOPS: S-R, D, T, JK AND MASTER SLAVE JK FF

USING NAND GATES
DATE :
AIM: To implement following flipflops using logic gates.

1. SR flip flop
2. JK flip flop
3. D flip flop
4. T flip flop
5. JK Master slave flip flop

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl No Components and equipments Specification Quantity

1 IC 7400,7404,7410 1,1,2

2 IC trainer kit 1

THEORY:

Department of ECE, CET 17

 LOGIC CIRCUIT DESIGN LAB

SR FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When I/Ps R=0 and
S=0 then O/P remains unchanged. When I/Ps R=0 and S=1 the flip-flop is switches to the stable
state where O/P is 1 i.e. SET. The I/P condition is R=1and S=0 the flip-flop is switched to the
stable state where O/P is 0 i.e. RESET. The I/P condition is R=1 and S=1 the flip-flop is switched
to the stable state where O/P is forbidden.
JK FLIP-FLOP: For purpose of counting, the J K flip-flop is the ideal element to use. The
variable J and K are called control I/Ps because they determine what the flip-flop does when a
positive edge arrives. When J and K are both 0s, both AND gates are disabled and Q retains its last
value.
D FLIP FLOP: This kind of flip flop prevents the value of D from reaching the Q output until
clock pulses occur. When the clock is low, both AND gates are disabled D can change value
without affecting the value of Q. On the other hand, when the clock is high, both AND gates are
enabled. In this case, Q is forced to equal the value of D. When the clock again goes low, Q
retains or stores the last value of D. D flip flop is a bistable circuit whose D input is transferred to
the output after a clock pulse is received.
T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input. It is useful for constructing binary
counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-
flop by tying both of its inputs high.
MASTER-SLAVE JK FLIP-FLOP: The Master-Slave Flip-Flop is basically two gated SR flip-
flops connected together in a series configuration with the slave having an inverted clock pulse.
The outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip flop.
This feedback configuration from the slave’s output to the master’s input gives the characteristic
toggle of the JK flip flop.
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip
flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated “slave”
flip flop when the clock input goes “LOW” to logic level “0”.

Department of ECE, CET 18

 LOGIC CIRCUIT DESIGN LAB

When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional
changes to its inputs are ignored. The gated “slave” flip flop now responds to the state of its
inputs passed over by the “master” section.

Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-
triggered.Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the
data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK
Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.

PROCEDURE:

1. Check the components.

2. Setup the flip flop using gates and verify the truth table.

SR FLIP FLOP
7400

7400

7400

7400

D FLIP FLOP

Department of ECE, CET 19

 LOGIC CIRCUIT DESIGN LAB

T FLIP FLOP

JK FLIP FLOP

MASTER SLAVE JK FLIP FLOP

Department of ECE, CET 20

 LOGIC CIRCUIT DESIGN LAB

RESULT: Implemented different flipflops using logic gates.

Department of ECE, CET 21

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 5 ASYNCHRONOUS COUNTERS

DATE:

AIM: To realize an asynchronous 3 bit up/down counter and decade counter.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl
Components and equipments Specification Quantity
No
1 IC 7476,7400 2,2 each
2 IC trainer kit 1

THEORY:

Asynchronous Decade Counter

This type of asynchronous counter counts upwards on each trailing edge of the input clock signal
starting from 0000 until it reaches an output 1001 (decimal 9). Both outputs Q0 and Q3 are now
equal to logic “1”. On the application of the next clock pulse, the output from the 74LS10
NAND gate changes state from logic “1” to a logic “0” level.As the output of the NAND gate is
connected to the CLEAR (CLR) inputs of all the 74LS73 J-K Flip-flops, this signal causes all of
the Q outputs to be reset back to binary 0000 on the count of 10. As outputs QA and QD are now
both equal to logic “0” as the flip-flop’s have just been reset, the output of the NAND gate
returns back to a logic level “1” and the counter restarts again from 0000. We now have a decade
or Modulo-10 up-counter.

3- bit Up-Down Counter

As we know that in the up-counter each flip-flop is triggered by the normal output of the
preceding flip-flop (from output Q of first flip-flop to clock of next flip-flop); whereas in a
down-counter, each flip-flop is triggered by the complement output of the preceding flip-flop
(from output Q^ of first flip-flop to clock of next flip-flop). The operation of such a counter is

Department of ECE, CET 22

 LOGIC CIRCUIT DESIGN LAB

controlled by the up-down control input. i.e, in the circuit diagram mode input(M) is the up-
down control input. When M=0, the output of XOR gate is Q output and it will act as a 3-bit up
counter. When M=1, the output of XOR gate is complement of Q output and it will act as a 3-bit
down counter.

PROCEDURE:

1. Check the components.

2. Setup the decade counter circuit; reset the outputs using clear input. Apply clock pulses
and observe the counting from 0000 to 1001.
3. Setup 3 bit up/down counter. Clear all FF. apply logic 0 to mode control pin and observe
the up counting. Preset all FF and apply logic 1 to mode control and observe down
counting.

Pin diagram of 7476

CIRCUIT DIAGRAMS

DECADE COUNTER

Department of ECE, CET 23

 LOGIC CIRCUIT DESIGN LAB

Truth table

Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

3 BIT UP/DOWN COUNTER

Department of ECE, CET 24

 LOGIC CIRCUIT DESIGN LAB

Truth Table

RESULT: The circuit for asynchronous 3 bit up/down counter and decade counter were setup
and the output for various combinations of input are observed.

Department of ECE, CET 25

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 6 SYNCHRONOUS COUNTERS

DATE:

AIM: To design and setup synchronous 3 bit up/down counter and decade counter using JK
flipflops.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl
Components and equipments Specification Quantity
No
1 IC 7476,7400,7408,7410 2,2,1,1 each
2 IC trainer kit 1

THEORY:

In Asynchronous binary counters the output of one counter stage is connected directly to
the clock input of the next counter stage and so on along the chain. The result of this is that the
Asynchronous counter suffers from what is known as “Propagation Delay” in which the timing
signal is delayed a fraction through each flip-flop. However, with the Synchronous Counter, the
external clock signal is connected to the clock input of EVERY individual flip-flop within the
counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same
time giving a fixed time relationship. In other words, changes in the output occur in
“synchronisation” with the clock signal. The result of this synchronisation is that all the
individual output bits changing state at exactly the same time in response to the common clock
signal with no ripple effect and therefore, no propagation delay.

PROCEDURE:

Department of ECE, CET 26

 LOGIC CIRCUIT DESIGN LAB

1. Test all the components and IC packages using digital IC tester.

2. Set up the circuits one by one and verify the counter states.

CIRCUIT DIAGRAM

DECADE COUNTER

Excitation Table

DESIGN

Department of ECE, CET 27

 LOGIC CIRCUIT DESIGN LAB

Circuit Diagram

Department of ECE, CET 28

 LOGIC CIRCUIT DESIGN LAB

3 BIT UP/DOWN COUNTER

Excitation Table

Design

Circuit Diagram

Department of ECE, CET 29

 LOGIC CIRCUIT DESIGN LAB

RESULT : The circuit for synchronous 3 bit up/down counter and decade counter using JK
flipflops were setup and the output for various combinations of input are observed.

Department of ECE, CET 30

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 7 RING COUNTER AND JOHNSON COUNTER

DATE:

AIM: To implement ring and Johnson counter using flip flop integrated circuits.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl
Components and equipments Specification Quantity
No
1 IC 7474 2
2 IC trainer kit 1

THEORY:

4-bit Ring Counter

The synchronous Ring Counter, is preset so that exactly one data bit in the register is set to
logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly applied
to all the flip-flops together in order to “RESET” their outputs to a logic “0” level and then a
“PRESET” pulse is applied to the input of the first flip-flop before the clock pulses are applied.
This then places a single logic “1” value into the circuit of the ring counter.
So on each successive clock pulse, the counter circulates the same data bit between the four flip-
flops over and over again around the “ring” every fourth clock cycle. But in order to cycle the
data correctly around the counter we must first “load” the counter with a suitable data pattern as
all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring counter
invalid.

Johnson Counter

The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with feedback
exactly the same as the standard Ring Counter , except that this time the inverted output Q of the
last flip-flop is now connected back to the input D of the first flip-flop as shown in circuit
diagram.
The main advantage of this type of ring counter is that it only needs half the number of flip-flops

Department of ECE, CET 31

 LOGIC CIRCUIT DESIGN LAB

compared to the standard ring counter then its modulo number is halved. So a “n-stage” Johnson
counter will circulate a single data bit giving sequence of 2n different states and can therefore be
considered as a “mod-2n counter”.

PROCEDURE:

1. Test all the components and IC packages using digital IC tester.

2. Set up the circuits verify the counter states.

Pin Diagram of 7474

Ring Counter

Truth Table
Clock Q0 Q1 Q2 Q4 D0 D1 D2 D3
1 1 0 0 0 0 1 0 0
2 0 1 0 0 0 0 1 0
3 0 0 1 0 0 0 0 1
4 0 0 0 1 1 0 0 0
5 1 0 0 0 0 1 0 0

Design

Department of ECE, CET 32

 LOGIC CIRCUIT DESIGN LAB

Circuit Diagram

Johnson Counter

Truth Table

Clock Q0 Q1 Q2 Q4 D0 D1 D2 D3
0 0 0 0 0 1 0 0 0
1 1 0 0 0 1 1 0 0
2 1 1 0 0 1 1 1 0
3 1 1 1 0 1 1 1 1
4 1 1 1 1 0 1 1 1
5 0 1 1 1 0 0 1 1

Department of ECE, CET 33

 LOGIC CIRCUIT DESIGN LAB

6 0 0 1 1 0 0 0 1
7 0 0 0 1 0 0 0 0

Design

Circuit Diagram

Department of ECE, CET 34

 LOGIC CIRCUIT DESIGN LAB

RESULT: The circuit for Ring and Johnson counter using flip flop integrated circuits were set
up and observed its outputs.

Department of ECE, CET 35

 LOGIC CIRCUIT DESIGN LAB

EXPT NO: 8 MULTIPLEXERS AND DE-MULTIPLEXERS USING GATES

AND ICs. (74150, 74154)

DATE :
AIM: To design and implement multiplexer and demultiplexer using logic gates and study of IC
74150 and IC 74154.
COMPONENTS AND EQUIPMENTS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2n input line and
n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information
from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In
the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the
selected gate to the associated data output line.

Department of ECE, CET 36

 LOGIC CIRCUIT DESIGN LAB

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

Department of ECE, CET 37

 LOGIC CIRCUIT DESIGN LAB

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

Department of ECE, CET 38

 LOGIC CIRCUIT DESIGN LAB

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

Department of ECE, CET 39

 LOGIC CIRCUIT DESIGN LAB

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT: The circuit for multiplexer and demultiplexer using logic gates were set up and the
output for various combinations of input are observed.

Department of ECE, CET 40

 LOGIC CIRCUIT DESIGN LAB

PART B

Department of ECE, CET 41

 LOGIC CIRCUIT DESIGN LAB

Basys 3™ FPGA Board- Overview

The Basys 3 board is a complete, ready-to-use digital circuit development platform based on the
latest Artix®-7 Field Programmable Gate Array (FPGA) from Xilinx®. With its high-capacity
FPGA (Xilinx part number XC7A35T- 1CPG236C), low overall cost, and collection of USB,
VGA, and other ports, the Basys 3 can host designs ranging from introductory combinational
circuits to complex sequential circuits like embedded processors and controllers. It includes
enough switches, LEDs, and other I/O devices to allow a large number of designs to be
completed without the need for any additional hardware, and enough uncommitted FPGA I/O
pins to allow designs to be expanded using Digilent Pmods or other custom boards and circuits.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher
performance, and more resources than earlier designs. Artix-7 35T features include:

 33,280 logic cells in 5200 slices (each slice

contains four 6-input LUTs and 8 flip-
flops)
 1,800 Kbits of fast block RAM.
 Five clock management tiles, each with a
phase-locked loop (PLL).
 90 DSP slices.
 Internal clock speeds exceeding 450MHz .
 On-chip analog-to-digital converter
(XADC)

Figure 1. Basys 3 FPGA board with callouts.

Department of ECE, CET 42

 LOGIC CIRCUIT DESIGN LAB

Figure 2. Basys 3 FPGA board with callouts.

Department of ECE, CET 43

 LOGIC CIRCUIT DESIGN LAB

Xilinx Vivado Design Flow

Department of ECE, CET 44

 LOGIC CIRCUIT DESIGN LAB

Expt No: 1 REALIZATION OF LOGIC GATES AND FAMILIARIZATION OF

FPGAs
Date:
Aim: (a) Familiarization of a basys 3 FPGA board and its ports and interface.
(b) Create the bitstream files for your FPGA board.
(c) Familiarization of the basic syntax of verilog
(d) Development of verilog modules for basic gates, synthesis and implementation in the
above FPGA to verify the truth tables.
(e) Verify the universality and non-associativity of NAND and NOR gates by uploading
the corresponding verilog files to the FPGA boards.
(f) Verify the functionality of each gates by assigning the inputs to switches in FPGA and
outputs to LEDs.

Components and Equipments Required:

Sl Components and
Specification Software Quantity
No equipments

1 FPGA Basys 3 Xilinx Vivado 1

Expected Simulation results

AND gate waveform

Department of ECE, CET 45

 LOGIC CIRCUIT DESIGN LAB

OR gate waveform

NOT gate waveform

NAND gate waveform

NOR gate waveform

Department of ECE, CET 46

 LOGIC CIRCUIT DESIGN LAB

XOR gate waveform

Procedure:
1. Write a Verilog module to realize a basic gate.
2. Write a test bench to verify the design.
3. Simulate the test bench and verify the design.
4. Synthesize the design, implement in FPGA and verify the outputs.

RESULT: Verilog code for basic gates were familiarized and the following codes were
synthesized and bitstream file was generated and dumped to FPGA and output was verified.

Department of ECE, CET 47

 LOGIC CIRCUIT DESIGN LAB

Expt No: 2 ADDERS IN VERILOG

Date:
Aim:
(a) Development of Verilog modules for half adder in 3 modeling styles
(dataflow/structural/behavioural).
(b) Development of Verilog modules for full adder in structural modeling using half
adder.

Components and Equipments Required:

Sl Components and
Specification Quantity
No equipments Software

1 FPGA Basys 3 Xilinx Vivado 1

Full Adder waveform

Procedure:
1. Write the Verilog module to realize half adder in three different styles.
2. Write a test bench to verify the design.
3. Simulate the test bench and verify the design.
4. Synthesize the design, implement in FPGA and verify the outputs.
5. Realize Full Adder using half adder and perform above steps.
RESULT: Verilog modules for half adder and full adder in 3 modeling styles were familiarized.

Department of ECE, CET 48

 LOGIC CIRCUIT DESIGN LAB

Department of ECE, CET 49

 LOGIC CIRCUIT DESIGN LAB

Expt No: 3 MUX AND DEMUX IN VERILOG

Date:
Aim:
(a) Development of verilog modules for a 4x1 and 8x1 MUX.
(b) Development of verilog modules for a 1x4 DEMUX.
Components and Equipments Required:

Sl Components and
Specification Software Quantity
No equipments
1 FPGA Lattice iCEstick 1

4x1 MUX waveform

8x1 MUX waveform

Department of ECE, CET 50

 LOGIC CIRCUIT DESIGN LAB

1x4 DEMUX waveform

Procedure:
1. Write the Verilog module to realize 4x1 MUX and 1x4 DEMUX.
2. Write a test bench to verify the design.
3. Simulate the test bench and verify the design.
4. Synthesize the design, implement in FPGA and verify the outputs.

RESULT: Developed verilog modules for a 4x1, 8x1 MUX and 1x4 DEMUX and observed its
outputs.

Department of ECE, CET 51

 LOGIC CIRCUIT DESIGN LAB

Expt No: 4 FLIPFLOPS AND COUNTERS

Date:
Aim:
(a) Development of verilog modules for SR, JK, T and D flipflops.
(b) Development of verilog modules for a binary decade/Johnson/Ring counters.
Components and Equipments Required:

Sl Components and
Specification Quantity
No equipments Software

1 FPGA Lattice iCEstick 1

SR Flipflop waveform

Department of ECE, CET 52

 LOGIC CIRCUIT DESIGN LAB

JK Flipflop waveform

D Flipflop waveform

Department of ECE, CET 53

 LOGIC CIRCUIT DESIGN LAB

T Flipflop waveform

Procedure:
1. Write the Verilog module to realize the counters
2. Write a test bench to verify the design.
3. Simulate the test bench and verify the design.
4. Synthesize the design, implement in FPGA and verify the outputs.

RESULT: Verilog code for SR, D, JK, D, T flipflops and binary decade/Johnson/Ring counters
were written and observed the outputs.

Department of ECE, CET 54

 LOGIC CIRCUIT DESIGN LAB

Expt No: 5 Flip-Flops and their Conversion in FPGA

Date:
Aim:
(a) Make gate level designs of J-K, J-K master-slave, T and D flip-flops, implement and test
them on the FPGA board.
(b) Implement and test the conversions such as T to D, D to T, J-K to T and J-K to D
Components and Equipments Required:
Sl Components and
Specification Quantity
No equipments Software
1 FPGA Lattice iCEstick 1

Theory:
Procedure:
1. Write the Verilog module to realize the flipflops.
2. Write a test bench to verify the design.
3. Simulate the test bench and verify the design.
4. Synthesize the design, implement in FPGA and verify the outputs.

RESULT:

Department of ECE, CET 55