FPGA Based Design

EE-410L

Complex Engineering Problem

Submitted By

Student Name Registration No.

Javeria Yasin BS-22-IB-104376
Muhammad Afnan BS-22-PB-103707

Batch: Semester:
2022-2026 6th
CEP Title:
Smart Parking System
Submit to:
Group no. : 11
Dr. Shahid Nazir

Department of Electrical Engineering

 Abstract

This project involves the design and implementation of a digital parking system using
FPGA. The system uses a set of switches to simulate password input and an LCD to
provide real-time feedback to the user. A state machine controls the flow, managing
password assignment, user input, and verification. The objective is to demonstrate a
practical application of FSMs, debouncing logic, and LCD interfacing on an FPGA
platform.
Smart Parking System CEP

1 Introduction
1.1 Background
With increasing demand for automated systems in smart cities, digital access control
systems are widely used in smart parking, secure gates, and embedded applications.
FPGA-based systems provide a flexible and powerful platform for implementing such
logic through hardware description languages like Verilog HDL.

1.2 Purpose
The primary goal of this lab is to simulate a basic version of a smart parking system
that uses password input and visual feedback through an LCD and LEDs. It demon-
strates user authentication, FSM logic, and LCD control at the hardware description
level.

2 Objectives
• Design a password-based FSM controller in Verilog HDL.

• Implement password entry and verification using hardware switches.

• Display system status and user feedback on a 16x2 LCD.

• Use LEDs to show password values and success/failure.

• Simulate and verify system behavior using Verilog test benches.

3 Equipment Used

Equipment Description
FPGA Board Xilinx Spartan-3/6
Verilog HDL Hardware Description Language
Xilinx ISE/Vivado FPGA design and simulation environment
16x2 Alphanumeric LCD Hitachi HD44780 compatible
LEDs & Switches For user input and feedback display
Simulation Tool ModelSim or ISim

4 System Design
The system is built on a finite state machine (FSM) with the following states:

• Idle State: Awaits user interaction.

• Assign State: A new password is generated.

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Smart Parking System CEP

• Verify State: User input is checked against the password.

• Result Display: Shows ”Goodbye” or ”Wrong password”.

The system takes 3-bit password input from switches (sw0, sw1, sw2) and uses
sw3 as a control button. LEDs represent the password, and an LCD displays system
messages. A 1Hz clock is derived from a high-frequency input to enable observable
transitions.

5 Code and Its Test Bench

5.1 Main Code

` t i m e s c a l e 1 ns / 1 ps

module ParkingSystem (
(∗ LOC = ”C9” ∗ ) i n p u t c l k ,
(∗ LOC = ”L13” ∗ ) i n p u t sw0 ,
(∗ LOC = ”L14” ∗ ) i n p u t sw1 ,
(∗ LOC = ”H18” ∗ ) i n p u t sw2 ,
(∗ LOC = ”N17” ∗ ) i n p u t sw3 ,
(∗ LOC = ”F12” ∗ ) output l e d 0 ,
(∗ LOC = ”E12” ∗ ) output l e d 1 ,
(∗ LOC = ”E11” ∗ ) output l e d 2 ,
(∗ LOC = ”F11” ∗ ) output l e d 4 ,
(∗ LOC = ”D16” ∗ ) output s f e ,
(∗ LOC = ”M18” ∗ ) output e ,
(∗ LOC = ”L18” ∗ ) output r s ,
(∗ LOC = ”L17” ∗ ) output rw ,
(∗ LOC = ”M15” ∗ ) output d ,
(∗ LOC = ”P17” ∗ ) output c ,
(∗ LOC = ”R16” ∗ ) output b ,
(∗ LOC = ”R15” ∗ ) output a
);

w i r e [ 3 : 0 ] sw = {sw3 , sw2 , sw1 , sw0 } ;

wire [ 4 : 0 ] led ;

assign led0 = led [0];

assign led1 = led [1];
assign led2 = led [2];
assign led4 = led [4];

reg [ 2 5 : 0 ] c l k d i v = 0;
wire clk 1hz = c l k d i v [ 2 5 ] ;

always @( posedge c l k ) b e g i n
c l k d i v <= c l k d i v + 1 ;
end

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Smart Parking System CEP

reg [ 2 : 0 ] password = 0 ;
reg [ 2 : 0 ] user input = 0;
reg password correct = 0;
reg [ 1 : 0 ] state = 0;

reg [ 1 9 : 0 ] debounce counter = 0;

reg sw3 sync = 0 ;
reg sw3 debounced = 0 ;
reg s w3 prev debo unced = 0 ;
reg sw3 posedge latched = 0;

always @( posedge c l k ) b e g i n
sw3 sync <= sw3 ;

i f ( sw3 sync != sw3 debounced ) b e g i n

d e b o u n c e c o u n t e r <= d e b o u n c e c o u n t e r + 1 ;
i f ( d e b o u n c e c o u n t e r == 2 0 'hFFFFF) b e g i n
sw3 debounced <= sw3 sync ;
d e b o u n c e c o u n t e r <= 0 ;
end
end e l s e b e g i n
d e b o u n c e c o u n t e r <= 0 ;
end

s w3 prev debo unced <= sw3 debounced ;

i f ( sw3 debounced && ! sw3 p rev d eb o u nc ed )

sw3 p o s e d g e l a t c h e d <= 1 ;
else if ( clk 1hz )
sw3 p o s e d g e l a t c h e d <= 0 ;
end

always @( posedge c l k 1 h z ) b e g i n
i f ( sw3 posedge latched ) begin
case ( state )
0: begin
password <= password + 1 ;
s t a t e <= 1 ;
end
1: begin
u s e r i n p u t <= sw [ 2 : 0 ] ;
p a s s w o r d c o r r e c t <= ( sw [ 2 : 0 ] == password ) ;
s t a t e <= 2 ;
end
2: begin
s t a t e <= 0 ;
password <= password + 1 ;
end
endcase

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Smart Parking System CEP

end
end

a s s i g n l e d [ 2 : 0 ] = ( s t a t e == 1 ) ? password : sw [ 2 : 0 ] ;
a s s i g n l e d [ 4 ] = ( s t a t e == 2 ) && p a s s w o r d c o r r e c t ;

LCD Controller l c d (
. clk ( clk ) ,
. sf e ( sf e ) ,
. e(e) ,
. rs ( rs ) ,
. rw ( rw ) ,
. d(d) ,
. c(c) ,
. b(b) ,
. a(a) ,
. state ( state ) ,
. password correct ( password correct ) ,
. password ( password )
);

endmodule

module LCD Controller (

input clk ,
output r e g s f e ,
output r e g e ,
output r e g r s ,
output r e g rw ,
output r e g d ,
output r e g c ,
output r e g b ,
output r e g a ,
input [ 1 : 0 ] state ,
input password correct ,
i n p u t [ 2 : 0 ] password
);

r e g [ 2 6 : 0 ] count = 0 ;
reg r e f r e s h ;
r e g [ 5 : 0 ] code ;

always @( posedge c l k ) b e g i n
count <= count + 1 ;
r e f r e s h <= count [ 2 0 ] ;

c a s e ( count [ 2 6 : 2 1 ] )
0 : code <= 6 ' h03 ;
1 : code <= 6 ' h03 ;
2 : code <= 6 ' h03 ;

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Smart Parking System CEP

3 : code <= 6 ' h02 ;

4 : code <= 6 ' h02 ;
5 : code <= 6 ' h08 ;
6 : code <= 6 ' h00 ;
7 : code <= 6 ' h06 ;
8 : code <= 6 ' h00 ;
9 : code <= 6 ' h0C ;
1 0 : code <= 6 ' h00 ;
1 1 : code <= 6 ' h01 ;

d e f a u l t : begin
case ( state )
0 : code <= 6 ' h10 ;
1: begin
c a s e ( count [ 2 6 : 2 1 ] )
1 2 : code <= 6 ' h24 ; 1 3 : code <= 6 ' h28 ;
1 4 : code <= 6 ' h26 ; 1 5 : code <= 6 ' h25 ;
1 6 : code <= 6 ' h26 ; 1 7 : code <= 6 ' h2C ;
1 8 : code <= 6 ' h26 ; 1 9 : code <= 6 ' h2C ;
2 0 : code <= 6 ' h26 ; 2 1 : code <= 6 ' h2F ;
2 2 : code <= 6 ' h22 ; 2 3 : code <= 6 ' h2C ;
2 4 : code <= 6 ' b001100 ; 2 5 : code <= 6 ' b000000 ;
2 6 : code <= 6 ' h27 ; 2 7 : code <= 6 ' h20 ;
2 8 : code <= 6 ' h26 ; 2 9 : code <= 6 ' h21 ;
3 0 : code <= 6 ' h27 ; 3 1 : code <= 6 ' h23 ;
3 2 : code <= 6 ' h27 ; 3 3 : code <= 6 ' h23 ;
3 4 : code <= 6 ' h22 ; 3 5 : code <= 6 ' h20 ;
3 6 : code <= 6 ' h26 ; 3 7 : code <= 6 ' h28 ;
3 8 : code <= 6 ' h27 ; 3 9 : code <= 6 ' h23 ;
4 0 : code <= 6 ' h22 ; 4 1 : code <= 6 ' h20 ;
4 2 : code <= ( 6 ' h30 + password ) ;
d e f a u l t : code <= 6 ' h10 ;
endcase
end
2: begin
i f ( password correct ) begin
c a s e ( count [ 2 6 : 2 1 ] )
1 2 : code <= 6 ' h24 ; 1 3 : code <= 6 ' h27 ;
1 4 : code <= 6 ' h26 ; 1 5 : code <= 6 ' h2F ;
1 6 : code <= 6 ' h26 ; 1 7 : code <= 6 ' h2F ;
1 8 : code <= 6 ' h26 ; 1 9 : code <= 6 ' h24 ;
2 0 : code <= 6 ' h26 ; 2 1 : code <= 6 ' h22 ;
2 2 : code <= 6 ' h27 ; 2 3 : code <= 6 ' h29 ;
2 4 : code <= 6 ' h26 ; 2 5 : code <= 6 ' h25 ;
d e f a u l t : code <= 6 ' h10 ;
endcase
end e l s e b e g i n
c a s e ( count [ 2 6 : 2 1 ] )
1 2 : code <= 6 ' h27 ; 1 3 : code <= 6 ' h27 ;
1 4 : code <= 6 ' h27 ; 1 5 : code <= 6 ' h22 ;

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Smart Parking System CEP

1 6 : code <= 6 ' h26 ; 1 7 : code <= 6 ' h2F ;

1 8 : code <= 6 ' h26 ; 1 9 : code <= 6 ' h2E ;
2 0 : code <= 6 ' h24 ; 2 1 : code <= 6 ' h27 ;
2 4 : code <= 6 ' b001100 ; 2 5 : code <= 6 ' b000000 ;
2 6 : code <= 6 ' h27 ; 2 7 : code <= 6 ' h20 ;
2 8 : code <= 6 ' h26 ; 2 9 : code <= 6 ' h21 ;
3 0 : code <= 6 ' h27 ; 3 1 : code <= 6 ' h23 ;
3 2 : code <= 6 ' h27 ; 3 3 : code <= 6 ' h23 ;
3 4 : code <= 6 ' h27 ; 3 5 : code <= 6 ' h27 ;
3 6 : code <= 6 ' h26 ; 3 7 : code <= 6 ' h21 ;
3 8 : code <= 6 ' h27 ; 3 9 : code <= 6 ' h22 ;
4 0 : code <= 6 ' h26 ; 4 1 : code <= 6 ' h24 ;
default : code <= 6 ' h10 ;
endcase
end
end
endcase
end
endcase

s f e <= 1 ;
{e , r s , rw , d , c , b , a} <= { r e f r e s h , code } ;
end

endmodule

5.2 Test Bench Code

` t i m e s c a l e 1 ns / 1 ps

module Park ingSystem tb ;

// I n p u t s
reg clk ;
r e g sw0 , sw1 , sw2 , sw3 ;

// Outputs
wire led0 , led1 , led2 , led4 ;
w i r e s f e , e , r s , rw , d , c , b , a ;

// I n s t a n t i a t e t h e Unit Under Test (UUT)

ParkingSystem uut (
. clk ( clk ) ,
. sw0 ( sw0 ) ,
. sw1 ( sw1 ) ,
. sw2 ( sw2 ) ,
. sw3 ( sw3 ) ,
. led0 ( led0 ) ,
. led1 ( led1 ) ,

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Smart Parking System CEP

. led2 ( led2 ) ,
. led4 ( led4 ) ,
. sf e ( sf e ) ,
. e(e) ,
. rs ( rs ) ,
. rw ( rw ) ,
. d(d) ,
. c(c) ,
. b(b) ,
. a(a)
);

// Generate 50 MHz c l o c k
always #10 c l k = ˜ c l k ;

// H e l p e r t a s k t o s i m u l a t e sw3 p r e s s
task press sw3 ;
begin
sw3 = 1 ;
#(2 0 0 0 0 0 0 ) ; // ho ld hi g h l o n g enough t o p a s s debounce ( ˜2 0ms a t 50MHz)
sw3 = 0 ;
#(2 0 0 0 0 0 0 ) ; // wa it b e f o r e next e v e n t
end
endtask

i n i t i a l begin
// I n i t i a l i z e i n p u t s
clk = 0;
sw0 = 0 ; sw1 = 0 ; sw2 = 0 ; sw3 = 0 ;

$ d i s p l a y ( ” S t a r t i n g ParkingSystem t e s t b e n c h ” ) ;

// ===== Step 1 : A s s i g n a password =====

// F i r s t p r e s s : a s s i g n password = 001
{sw2 , sw1 , sw0} = 3 ' b001 ;
press sw3 ( ) ;

// Wait f o r password t o show on LEDs

#5 0 0 0 0 0 0 ;

// ===== Step 2 : Enter c o r r e c t password =====

// Enter same password : 001
{sw2 , sw1 , sw0} = 3 ' b001 ;
press sw3 ( ) ;

// Wait f o r LCD message ”Goodbye”

#10 0 0 0 0 0 0 ;

// ===== Step 3 : A s s i g n next password =====

// P r e s s a g a i n : password = 010 now ( password i n c r e m e n t s )

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Smart Parking System CEP

{sw2 , sw1 , sw0} = 3 ' b010 ; // c u r r e n t s w i t c h e s d o n t matter h e r e

press sw3 ( ) ;

#5 0 0 0 0 0 0 ;

// ===== Step 4 : Enter wrong password =====

{sw2 , sw1 , sw0} = 3 ' b111 ; // Wrong i n p u t
press sw3 ( ) ;

// Wait f o r LCD message ”Wrong password ”

#10 0 0 0 0 0 0 ;

$ d i s p l a y ( ” Testbench complete . ” ) ;
$stop ;
end

endmodule

6 Code Explanation
6.1 FSM Logic
• State 0 (Idle): Waits for a press of sw3.

• State 1 (Assign): A new password is auto-incremented.

• State 2 (Verify): User input is compared with the password.

6.2 Password Handling

• reg [2:0] password; - Holds the system password.

• reg [2:0] user input; - Captures switch input.

• If matched, password correct is set high.

6.3 Clock Divider

reg [ 2 5 : 0 ] c l k d i v ;
wire c l k 1 h z = c l k d i v [ 2 5 ] ;
This creates a 1Hz signal from a 50MHz base clock to slow down system transitions
for human interaction.

6.4 LED Display

• led[0:2] shows the password or input value.

• led[4] turns ON if password is correct.

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Smart Parking System CEP

7 LCD Messaging Logic

The LCD displays different messages based on state transitions. Sample logic in-
cludes:

State LCD Line 1 LCD Line 2

Assign Hello, pass is X
Verify OK Goodbye —
Verify NOK wrong password

Characters are stored in ROM-style logic and sent sequentially via control signals
using a refresh counter.

8 Simulation and Results

8.1 Expected Behavior
• On reset, system stays idle.

• First press of sw3 assigns a password and shows it on LCD.

• Correct password turns ON success LED and shows ”Goodbye”.

• Wrong input shows ”Wrong Password” on LCD.

Here is the simulation output demonstrating the behavior of the Parking System
under test conditions:

Figure 1: Simulated Results

9 Hardware Implementation
The hardware implementation of the Parking System was carried out using an FPGA
development board. The Verilog code was synthesized and programmed onto the

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Smart Parking System CEP

board, interfacing it with input switches, output LEDs, and an alphanumeric LCD
module. Proper pin mapping was ensured using location constraints for accurate
signal routing. This implementation allowed real-time testing and validation of the
system logic.

Figure 2: Assign Password to Car

Figure 3: Pass the Car

Figure 4: Wrong Password

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Smart Parking System CEP

10 Discussion
The development of the FPGA-based Parking System highlights several key aspects
of embedded system design and digital logic implementation. One of the primary
goals of this CEPO was to create a secure, password-protected access mechanism
that could be realistically deployed in scenarios such as gated parking, private entry
systems, or any controlled-access environment. The design involved not only correct
digital logic but also emphasized the importance of user interaction, timing control,
and hardware interfacing.
A major strength of this project lies in its modular structure; separating pass-
word logic, debounce handling, state management, and LCD messaging into distinct,
well-organized blocks. This modularity improved both the readability and the main-
tainability of the code and also facilitated easier debugging during simulation and
hardware testing phases. The debounce circuit for the input switch (SW3) ensured
reliable and noise-free input, which is critical in real-world hardware environments
where mechanical switches are prone to signal bouncing.
The system was successfully tested using both testbenches and real FPGA hard-
ware. Simulation results verified the correct functioning of password assignment, user
input comparison, and visual feedback via LEDs and the LCD module. On hardware,
the implementation accurately reflected the simulation, displaying appropriate mes-
sages like “Hello, pass is X”, “Goodbye”, and “Wrong password” depending on system
state and user input.
However, the project is not without limitations. The password was implemented
using a simple counter logic which increments with each assignment rather than being
user-defined, limiting flexibility. Additionally, scalability is constrained by the number
of switches and display characters available. For larger-scale or more secure imple-
mentations, enhancements such as keypad input, EEPROM-based password storage,
or wireless communication can be integrated.
Overall, the project met its core objectives and provided a practical learning expe-
rience in applying Verilog for real-time digital system development, while reinforcing
concepts like finite state machines, clock division, synchronization, and peripheral
control. It serves as a solid foundation for more advanced embedded security sys-
tems.

11 Improvements in the Project

While the implemented FPGA-based Parking System successfully demonstrates the
fundamental operation of a password-protected access control mechanism, several
improvements can be made to enhance its functionality, usability, and scalability:

• User-Defined Password Input: Currently, the password is assigned using a

simple counter mechanism, which limits flexibility. Allowing users to set their
own password via switches or a keypad would make the system more practical.

• Keypad Integration: Instead of relying on just three switches for password

input, a 4x4 keypad could be added to allow multi-digit password entries, in-
creasing security and usability.

• EEPROM-Based Storage: Adding non-volatile memory (like EEPROM)

would enable persistent password storage even after power cycles, making the

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Smart Parking System CEP

system suitable for real-world deployment.

• LCD Message Enhancement: The current LCD messages are simple and
fixed. A more dynamic messaging system with scrollable text or graphical
feedback (using a graphical LCD) would improve user experience.

• Improved Debouncing and Multi-Input Handling: Although a basic de-

bounce mechanism is included, implementing a more robust solution using finite
state machines or dedicated debouncing modules would increase reliability.

• Security Features: Incorporating timeout features, limited attempts, or even

alarm triggering after multiple wrong password attempts can make the system
more secure.

• Wireless Control or RFID Integration: Modern systems often utilize RFID

tags or Bluetooth/NFC access. Integrating such features would modernize the
system and expand its applicability.

• Modular Display and Feedback: Including more detailed feedback like time
stamps, user identification, or access logs using an external memory or display
could be beneficial for security monitoring.

• Simulation Coverage and Timing Analysis: While functional simulations

were performed, further improvements could be made by conducting formal ver-
ification, synthesis reports, and timing analysis to ensure optimal performance
on the FPGA.

These enhancements would transform the project from a basic password demon-
stration into a fully functional, secure, and user-friendly access control system.

12 Conclusion
The Smart Parking System successfully demonstrates:
• FSM-based password authentication.

• LCD message display in Verilog HDL.

• Switch-driven user input and LED feedback.

The Smart Parking System designed and implemented represents a practical and ef-
ficient solution to modern urban parking challenges. By utilizing Verilog HDL and
FPGA-based development, the system successfully demonstrates the integration of
user authentication, state machine logic, and real-time display feedback through an
LCD. The ability to verify passwords securely and provide intuitive user interac-
tion using switches and LEDs highlights its applicability in real-world smart parking
environments. Moreover, the LCD messaging system adds a professional layer of com-
munication, enhancing user experience. This project not only reinforces key digital
design concepts but also offers a scalable prototype that can be extended for larger,
more complex parking systems involving sensors, vehicle tracking, and mobile inte-
gration. The successful simulation results validate the design’s robustness, making
it a strong foundation for future automation and embedded system applications in
smart infrastructure.

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References

[1] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd
ed., McGraw-Hill, 2009.

[2] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd ed.,
Pearson, 2003.

[3] Hitachi, HD44780U LCD Controller Datasheet, Hitachi, 2001.

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