Assignment Solutions
Q.1. Simplify the following functions
a) F(A,B,C,D)=∑m(0,2,4,5,6,7,8,10,13,15)
We will use a K-map to simplify the function. The '1's represent the
minterms.
Groups:
● Quad 1: m(4,5,6,7) simplifies to A′B
● Quad 2: m(0,2,8,10) simplifies to B′D′
● Pair 1: m(13,15) simplifies to ACD
Simplified Expression:
F(A,B,C,D)=A′B+B′D′+ACD
b) F(A,B,C,D)=πM(0,2,3,8,9,12,13,15)
This is a Product of Sums (POS) form. We'll use a K-map to group the '0's
(maxterms).
Groups:
● Quad 1: M(0,2,8,10) simplifies to (B+D)
● Quad 2: M(8,9,12,13) simplifies to (C+D′)
● Pair 1: M(2,3) simplifies to (A+B+C′)
Simplified Expression:
F(A,B,C,D)=(B+D)(C+D′)(A+B+C′)
Q.2. Simplify with Don't Cares
a) F(A,B,C,D)=∑m(0,2,4,5,6,8,10,15)+d(7,13,14)
We'll use a K-map, including the minterms and 'don't care' conditions, to
find the largest possible groups of '1's.
Groups:
● Octet 1: m(0,2,4,6,8,10,14) simplifies to D′
● Quad 1: m(5,7,13,15) simplifies to BD
Simplified Expression:
F(A,B,C,D)=D′+BD
b) F(w,x,y,z)=∑m(4,5,7,12,14,15)+d(3,8,10)
We will use a K-map with the '1's from the minterms and 'don't care'
terms.
Groups:
● Quad 1: m(4,5,12,13) simplifies to x′y′
● Quad 2: m(7,15) and m(3,11) with don't cares simplifies to yz
● Pair 1: m(8,10) with don't cares simplifies to x′z′
● Pair 2: m(14,15) simplifies to wxy
Simplified Expression:
F(w,x,y,z)=x′y′+yz+x′z′+wxy
Q.3. Minimize and Implement with NAND Gates
Minimize F(A,B,C,D)=∑m(4,5,6,7,8,12)+d(1,2,3,9,11,14) using a K-map.
Groups:
● Quad 1: m(4,5,6,7) simplifies to A′B
● Quad 2: m(8,9,12,13) with don't cares simplifies to AB′
● Pair 1: m(1,3) with don't cares simplifies to A′C′D
Simplified Expression:
F(A,B,C,D)=A′B+AB′+A′C′D
Implementation using NAND gates:
1. Double-inversion: The simplified expression is F=A′B+AB′+A′C′D.
2. Apply DeMorgan's Theorem: F=A′B+AB′+A′C′D
3. Final form for NAND gates: F=(A′B)⋅(AB′)⋅(A′C′D)
This shows the circuit can be implemented with a three-input NAND
gate at the output, fed by three two-input NAND gates for each term.
Q.4. Convert to Standard SOP Form
i) Y=AB+AC+BC
Y=AB(C+C′)+AC(B+B′)+BC(A+A′)
Y=ABC+ABC′+ABC+AB′C+ABC+A′BC
Y=ABC+ABC′+AB′C+A′BC
Standard SOP Form: Y=∑m(7,6,5,3)
ii) Y=A+BC+ABC
Y=A(B+B′)+BC+ABC
Y=A(B+B′)(C+C′)+BC(A+A′)+ABC
Y=(AB+AB′)(C+C′)+ABC+A′BC+ABC
Y=ABC+ABC′+AB′C+AB′C′+ABC+A′BC
Y=ABC+ABC′+AB′C+AB′C′+A′BC
Standard SOP Form: Y=∑m(7,6,5,4,3)
Q.5. Minimize and Implement with Logic Gates
Minimize F(A,B,C,D)=∑m(0,1,2,3,4,7,8,9,10,11,12,14) using a K-map.
Groups:
● Quad 1: m(0,1,8,9) simplifies to B′C′
● Quad 2: m(0,2,8,10) simplifies to B′D′
● Quad 3: m(8,9,10,11) simplifies to AB′
● Quad 4: m(0,4) with don't cares simplifies to C′D′
● Pair 1: m(1,3) simplifies to A′B′D
Simplified Expression:
F(A,B,C,D)=B′C′+B′D′+AB′+C′D′+A′B′D
Implementation using logic gates (SOP):
The simplified expression is a Sum of Products. The circuit will consist of
AND gates for each product term and one large OR gate to combine their
outputs. The inputs to the AND gates will be the variables or their
complements.
