EC792 HPCA

Language basics

Identifiers
◼ Any sequence of letters, digits, $, _
◼ First character must be letter or _
◼ Case sensitive
◼ Count, COUNT, count - are distinct
◼ Escaped identifier – any printable ASCII character
◼ \7400
◼ \Count is same as Count
◼ Reserved identifiers – keywords
◼ lower case
◼ always ALWAYS \always – are distinct hence avoid

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 EC792 HPCA

Comments
◼ /* ……. */
◼ //

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Value set
◼ Four basic values
◼ 0 – logic 0 or false
◼ 1 – logic 1 or true
◼ x – unknown
◼ z – high impedance
◼ case insensitive x or X , z or Z

◼ z at input interpreted as x

◼ Three types of constants

◼ Integer
◼ Real
◼ String

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Integer
◼ Simple decimal
◼ 32 , -15
◼ signed number in 2’C form
◼ Base format
◼ [size] ‘[signed] base value
◼ size – size of the constant in bits
◼ if size is not specified default is 32 bits

◼ if size is larger – padding 0 for unsigned, msb for signed

◼ if size is smaller – left most bits truncated

◼ signed – s or S if omitted unsigned

◼ base – o or O, b or B, d or D, h or H
◼ values of x, z and hex values a – f are case insensitive
◼ 5 ‘O 37, 4 ‘B 1x_01, 8 ‘SH2A, 6 ‘SO71
◼ 4 ‘D-4, (2+3) ‘D10, 3` B001 - incorrect

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Real
◼ Decimal
◼ 2.0, 5.678, 0.1

◼ 2. , .1 - incorrect

◼ Scientific notation
◼ 3.6e2, 5E-4

◼ not useful in synthesis

◼ implicit conversion to integer by rounding defined by
language
◼ 42.446, 42.45 – rounded to 42

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 EC792 HPCA

Strings
◼ sequence of character within double quotes
◼ “DSD”
◼ a character is treated as an 8 bit ASCII value
◼ Not useful in synthesis
◼ special characters using \
◼ \n , \t, \\, \”, \206

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Data types
◼ Net type
◼ represents physical connection between structural elements
◼ value from its driver – continuous assignment or gate output
◼ no driver – defaults to z
◼ Variable type
◼ abstract storage element
◼ Assigned values only within always or initial statement

◼ value saved from one assignment to next

◼ default value - x

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 EC792 HPCA

Net
◼ wire, tri
◼ net_kind [signed] [ [msb:lsb] ] net1, net2 …;
◼ default unsigned value
◼ wire cnt_start
◼ wire signed [7:0] prdata;
◼ better to express range in descending order
◼ ‘define SIZE 16
◼ wire signed [‘SIZE-1:0] pr_addr;
◼ No driver initialized to z

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Multiple drivers on wire/tri

◼ pairwise application of the following table

wire/tri 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x z

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Net
◼ Undeclared nets will default implicitly to type wire
◼ Can be changed using ‘default_nettype
◼ Can be set to none – for declaring explicitly
◼ vectored and scalared net
◼ vectored part select and group select not allowed

◼ wire vectored [7:0] grp_cnt

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Variables
◼ reg, integer, time, real, realtime
◼ reg [signed] [ [msb:lsb] ] reg1, reg2 …
◼ default unsigned; initialized to x
◼ no range – 1 bit
◼ reg [ [msb:lsb] ] memory1[upper:lower] …
◼ memory - array of reg variables
◼ assign values to each word individually or use a for loop
◼ reg [7:0] mem_a [63:0], mem_b[63:0];
◼ mem_a[1] = 8 ‘HFA;
◼ mem_a = mem_b – incorrect
◼ $readmem – loads binary values from file
◼ $readmemh – loads hexadecimal values
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 EC792 HPCA

Value holders for hardware modeling

◼ Wire
◼ Flip flop (edge triggered storage element)
◼ Latch (level triggered storage element)
◼ net – maps to a wire
◼ reg – maps to wire or a storage element depending on context

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Integer
◼ integer int1, int2, int3 [msb:lsb]
◼ no bit range – 32 bits minimum (or by implementation)
◼ signed values
◼ arithmetic operations – 2’C results
◼ reg [31:0] sel_reg; integer sel_int;
◼ sel_int[6], sel_int[20:10]
◼ sel_reg = sel_int; //conversion from integer to bit vector

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 EC792 HPCA

Variables
◼ Time – used to store and manipulate time variables
◼ real and realtime
◼ default is 0

◼ not useful in synthesis

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Arrays
◼ wire add_bus [0:4];
◼ wire [31:0] big_addr [0:1][0:3]
◼ integer fifo [0:15] [0:15];
◼ only an element of an array can be assigned
◼ big_addr[0][1] = 32’b0;
◼ big_addr[0][0][5:0]=6’100011

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 EC792 HPCA

Parameters
◼ constant specification
◼ parameter [signed][[msb:lsb]] param1=const_expr
◼ parameter BIT=1, BYTE=8; //implied range [31:0]
◼ parameter signed [3:0] MEM_DR = -5
◼ Value can be changed at compile time or by
specifying parameter value in module instantiation
◼ local to the module where it is defined
◼ ‘define - spans multiple files
◼ localparam
◼ Local to module cannot be changed at compile time or
module instantiation
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Expressions
◼ Operands and operators
◼ Operands
◼ Constant
◼ Parameter
◼ Net
◼ Variable
◼ Bit-select
◼ Part-select
◼ Memory and array element
◼ Function call
◼ If all operands in an expression are signed result is signed else result is
unsigned

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 EC792 HPCA

Operands
◼ Bit-select
◼ net_or_reg_vector[bit_select_expr]
◼ Part-select
◼ Constant part select
◼ net_or_reg_vector[msb_const_expr:lsb_const_expr]

◼ addr_bus[1:3]

◼ Indexed part select

◼ net_or_reg_vector[base_expr+:const_width_expr]

◼ net_or_reg_vector[base_expr-:const_width_expr]

integer mark; reg [0:15] inst_code;

inst_code[mark+:2] selects the bits mark and mark+1
inst_code[mark-:4] selects mark, mark-1, mark-2, mark-3
▪ If range is out of bounds or evaluates to an x or z the part select
value is x

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Memory and array element

◼ memory[word_address] – selects one word
◼ part select and bit select of an element of a memory or an array is
allowed
reg [1:8] hdlc_ram[0:63], intr_ack;
intr_ack = hdlc_ram[60];
hdlc_ram[60][2] - value at index 2 of 60th element
hdlc_ram[15][2:4] – value from index [2:4] of 15th element
hdlc_ram[0:2] – not allowed

reg [7:0] sense_data [15:0][15:0];

integer three_d [255:0][255:0][255:0];
wire xbar [3:0][3:0];
sense_data[2][3] sense_data[1][1][0] - ok
three_d[5][5][2] - ok
three_d[5][1:5][2] and xbar[0][2:0]– not allowed

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 EC792 HPCA

Part select and bit select

◼ Non constant part select is not supported
◼ Bit select
◼ Constant index – rewiring

◼ Non constant index in expression – multiplexer

◼ dout = data[index]
◼ Non constant index in target - decoder
◼ mem[addr] = Store;

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Operators
◼ Arithmetic : +, -, *, /, %, **
◼ Relational: >, <, >=, <=
◼ Equality : ==, !=, ===, !==
◼ Logical : &&, ||, !
◼ Bitwise : ~, &, |, ^, ~^, ^~
◼ Reduction: &,~&, |, ~| , ^, ~^
◼ Shift :<<, >>, <<<, >>>
◼ Conditional
◼ Concatenation and replication

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 EC792 HPCA

Arithmetic Operators
◼ +, -, *, /, %, **
◼ Integer division truncates fractional part
◼ % (modulus) gives the remainder with the sign of the first operand
◼ If any bit is x or z entire result is X
◼ Size of result – size of the largest operand (incl target on left)
◼ If any one operand is unsigned all operands are converted to unsigned
before any operation takes place
◼ Unsigned – net, reg variable, integer in base format without S
◼ Signed – integer variable, integer in decimal format, integer in base
format with S, signed reg variable, signed net
◼ $signed and $unsigned – system functions for conversion

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Relational operators
◼ >, <, >=, <=
◼ Result is 1 (true) or 0 (false)
◼ If either operand is X or Z result is X
◼ ‘b1000 >= ‘b01110 eqvt to ‘b01000 >= ‘b01110 - False
◼ 4’sb1011 <= 8’sh1A eqvt to 8’sb11111011 <= 8’sh00011010
– True
◼ If one of the operands is unsigned rest is treated as
unsigned

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 EC792 HPCA

Equality operators
◼ ==, !=, ===, !==
◼ Result is 1 (true) or 0 (false)
◼ Case comparisons === and !== are not supported for synthesis
◼ In case comparisons X and Z are compared strictly as values
◼ ‘b11x0 ==‘b11x0 is unknown

◼ ‘b11x0 ===‘b11x0 is 1

◼ ‘b010x !=‘b11x0 is 1 - difference in first bit

◼ 2‘b10 ==4‘b0010 is eqvt 4‘b0010 == 4‘b0010 is 1

◼ Smaller operand 0 extended for unsigned/ sign extended for

both signed

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Logical operators
◼ &&, ||, !
◼ Operate on logical values 0 or 1
◼ Result 0, 1 or x
◼ Vector operands – non zero vector is treated as 1
◼ ‘b0 && b1 is 0
◼ ‘b0110 || ‘b0100 is 1
◼ ‘b1 || ‘bx is 1 ‘b0 && ‘bz is 0 !x is x

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 EC792 HPCA

Bit wise operator

◼ ~, &, |, ^, ~^, ^~
◼ Smaller operand 0 extended for unsigned/ sign
extended for both signed
◼ Vector output
◼ Get directly mapped into primitive logic gates in
synthesis

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Reduction operator
◼ &,~&, |, ~| , ^, ~^
◼ Operates on all bits of a single operand and produces
1 bit result
◼ a=‘b0100
◼ |a is 1
◼ &a is 0
◼ ^a is 1

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 EC792 HPCA

Shift operator
◼ <<, >> - logical left, right
◼ <<<, >>> - arithmetic left, right
◼ Combinational hardware in synthesis
◼ Right operand considered as unsigned
◼ Logical shift, Arith left – fills vacated bits with 0s
◼ 8’h17 >> 2 – 8’b00000101 8’h17 << 2 – 8’b01011100
◼ 8’h17 <<< 4 – 8’b01110000
◼ 8’h17 << -2 – 8’b00000000 (left shifted 231 -2)
◼ Arith right shift
◼ Left operand unsigned – fill with 0s
◼ Left operand signed – fill with msb
◼ 4’sb1011 >>> 2 - 1110
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Conditional operator
◼ cond_expr ? expr1 : expr2
◼ if condr_expr =1 expr1 is selected else expr2
◼ count = (count != 255) ? (count + 1) : 0

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 EC792 HPCA

Concatenation & replication

◼ Joining bits to form larger expressions
◼ {expr1, expr2, ….exprN}
◼ wire [7:0] dbus;
◼ assign dbus[7:4] = {dbus[0], dbus[1], dbus[2], dbus[3]};
◼ assign dbus = {dbus[3:0], dbus[7:4]};
◼ {dbus, 5} – unsized constants not allowed
◼ Repetition by specifying a repetition number
◼ {repetition_no {expr1, expr2, …exprN}}
◼ wire [11:0] abus;
◼ assign abus = {3 {4’b1010}}; - 12’b101010101010
◼ assign abus = {{4 {dbus[7]}}, dbus};
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Precedence of operators
◼ +, -, !, ~, &, ~&, |, ~|, ^, ^~, ~^ (reduction)
◼ ** (power)
◼ *, /, %
◼ +, - (binary add and subtract)
◼ <<, >>, <<<. >>> (shift)
◼ <, <=, >, >= (relational)
◼ ==, !=, ===, !== (equality)
◼ & (bit wise and)
◼ ^, ^~, ~^ (bitwise)
◼ | (bitwise or)
◼ && (logical and)
◼ || (logical or)
◼ ?: (conditional)
◼ {}, {{}} (concatenation and repetition)
◼ operators associate left to right except conditional right to left

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 EC792 HPCA

Kinds of expressions
◼ Constant expression
◼ evaluates to a constant at compile time
◼ constant literals, parameter names, bit select and part select of a
parameter, constant function calls
◼ Scalar expression
◼ evaluates to a 1 bit result
◼ if a scalar result is expected and expression produces vector result
a non-zero vector is treated as 1
◼ Evaluating an expression
◼ determine expression size – size of largest operand
◼ determine signedness – if any operand is unsigned expression is unsigned.
Target does not determine signedness
◼ all operands are coerced to the signedness, size of operands extended
◼ expression evaluated
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More on structural modeling

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 EC792 HPCA

Module instantiation
◼ Unconnected ports can be left blank
◼ mod1 u1 (a, , b, , c);

◼ unconnected inputs are driven to z

◼ unconnected outputs are unused

◼ An implicit continuous assignment is assumed

between port and port expression
◼ if port and port expression are of different lengths

same rules as that of continuous assignment (right

to left)

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Module parameter values

◼ Higher level module can change the value of parameters in lower level
module
◼ defparam statement
◼ defparam hierpath1=value1, hierpath2 = value 2…..;

◼ defparam [Link]=5, [Link]=2;

◼ module instance parameter value assignment at any level of the

hierachy
◼ Parameter ports
◼ module module_name #(parameter param1=value1, param2 …..)
(port_list)
◼ use local parameter if a parameter does not vary from one instance
to another

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Module instance parameter value

assignment

◼ Positional association
◼ mod2 #(5,2) u1 (a,b,c,d)
◼ order must match order of parameters declared in the module
◼ Named association
◼ mod2 #(.param1(2),.param2(2)) u1 (a,b,c,d)
◼ need to specify only the parameters that have to be changed
◼ Can be used only to pass parameter values down one level of hierarchy
◼ External ports
◼ list of ports visible outside need not be same as internal ports
◼ module exter_p(.data(arb),.control(ctrl),.addr(byte));

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Generate
◼ Elaboration time selection or replication of certain statements
◼ Module and gate instantiation

◼ Continuous assignment

◼ Always and initial statement

◼ generate …. endgenerate
◼ generate loop

◼ generate conditional

◼ generate case

◼ Nested generate

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 EC792 HPCA

Generate loop
generate
for (initial_expr; final_expr; assignment)
begin: label
statements
end
endgenerate

module gray2bin1(gray,bin)
parameter SIZE=8;
input [SIZE-1:0] gray; output [SIZE-1:0] bin;
genvar i;
generate for (i=0; i< SIZE; i=i+1)
begin: bit
assign bin[i] = ^gray[SIZE-1:i];
end
endgenerate
endmodule

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generate loop and always

module gray2bin2(gray,bin)
parameter SIZE=8;
input [SIZE-1:0] gray; output reg [SIZE-1:0] bin;
genvar i;
generate for (i=0; i< SIZE; i=i+1)
begin: bit
always @(*)
bin[i] = ^gray[SIZE-1:i];
end
endgenerate
endmodule

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 EC792 HPCA

Generate conditional
if (condition)
statements
[else statements]
if (condition1)
statements
[elseif (condition2) statements
[else statements]]
◼ the condition must be a static condition,

computable at elaborate time

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n bit ripple carry adder

module adder_nbit(x,y,cin,sum,cout);
parameter N=4;
input [N-1:0] x,y; input cin;
output [N-1:0] sum; output cout;
genvar i;
wire [N-2:0] c;
generate
for (i=0;i<N; i=i+1)
begin : adder
if(i==0) full_adder fa (x[i],y[i],cin,sum[i],c[i]);
else if (i==N-1) full_adder fa (x[i],y[i],c[i-1],sum[i],cout);
else full_adder fa (x[i],y[i],c[i-1],sum[i],c[i]);
end
endgenerate
endmodule

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 EC792 HPCA

Generate case
◼ similar to generate conditional
case (case_expr)
case_value1 : statements
….
default: statements
endcase

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n bit ripple carry adder

module adder_nbit(x,y,cin,sum,cout);
parameter N=4;
input [N-1:0] x,y; input cin;
output [N-1:0] sum; output cout;
genvar i;
wire [N-2:0] c;
generate
for (i=0;i<N; i=i+1)
begin : adder
case (i)
0: assign {c[i],sum[i]} = x[i]+y[i]+cin;
N-1: assign {cout,sum[i]} = x[i]+y[i]+c[i-1];
default: assign {c[i],sum[i]} = x[i]+y[i]+c[i-1];
endcase
end endgenerate
end module

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 EC792 HPCA

Sub programs - Tasks and functions

Task
◼ Ability to execute common pieces of code from several different
places
◼ Task is a procedural statement
◼ Task definition and task call
◼ Can have zero, one or more arguments – input, output or inout
◼ Written within a module
task [automatic] task_id ([argument_declarations]);
[other_declarations]
procedural_statement
endtask
◼ Automatic – all local variables declared within the task are allocated
dynamically for each task call
◼ Non-automatic(static) each task call shares the same storage space

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 EC792 HPCA

Task calling
◼ Task enable statement – procedural statement
◼ task_id[(expr1,expr2….)];

◼ List of arguments must match order in task

definition
◼ Arguments are passed by value and not by

reference
◼ Task can contain timing controls and hence return

a value later in time than when it is called

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Example
module task_example(data,out);
input [7:0] data; output reg [3:0] out;

//task definition
task count_1s(input [7:0] dbyte, output reg [3:0] count);
begin
count =dbyte[0]+dbyte[1]+dbyte[2]+dbyte[3]+dbyte[4]+
dbyte[5]+dbyte[6]+dbyte[7];
end task

always @(*)
count_1s(data,out);

endmodule

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 EC792 HPCA

module mux16to1 (W, S16, f);

input [0:15]W;
input [3:0] S16;
output reg f;

always @(W, S16)

case (S16[3:2])
0: mux4to1 (W[0:3], S16[1:0], f);
1: mux4to1 (W[4:7], S16[1:0], f);
2: mux4to1 (W[8:11], S16[1:0], f);
3: mux4to1 (W[12:15], S16[1:0], f);
endcase

// Task that specifies a 4-to-1 multiplexer

task mux4to1;
input [0:3] X;
input [1:0] S4;
output reg g;
case (S4)
0: g = X[0];
1: g = X[1];
2: g = X[2];
3: g = X[3];
endcase
endtask

endmodule
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Functions

Item Tasks Functions

Arguments 0, 1, or more – input, At least one input and
output or inout cannot have output
and inout
Return value Multiple values via Only a single value via
output and inout function name
Timing control Yes No
statements
Execution In nonzero simulation In zero simulation
time time
Invoke functions/tasks Functions and tasks Functions only

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Function definition
function [automatic] [signed] [range_or_type] function_id ([input_declarations]);
[other_declarations]
procedural_statement
endfunction
◼ return type
◼ real, integer, time or realtime
◼ no range or type – 1 bit return value
◼ can be declared to be signed value
◼ implicitly declares a return reg variable internal to
the function
◼ automatic – local variables are allocated new for
each function call

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module mux16to1 (W, S16, f);

input [0:15]W;
input [3:0] S16;
output reg f;

// Function that specifies a 4-to-1 multiplexer

function mux4to1;
input [0:3] X;
input [1:0] S4;
case (S4)
0: mux4to1 = X[0];
1: mux4to1 = X[1];
2: mux4to1 = X[2];
3: mux4to1 = X[3];
endcase
endfunction

always @(W, S16)

case (S16[3:2])
0: f = mux4to1 (W[0:3], S16[1:0]);
1: f = mux4to1 (W[4:7], S16[1:0]);
2: f = mux4to1 (W[8:11], S16[1:0]);
3: f = mux4to1 (W[12:15], S16[1:0]);
endcase

endmodule
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Function call
◼ Function call is part of an expression
◼ func_id(expr1,expr2,…exprN)
◼ parameter value can be overridden by defparam
◼ Constant function
◼ function that can be evaluated to a constant at elaboration time
◼ useful for vector width declarations
module example_const_fn;
parameter vector_lsb=7, vector_msb=15;
reg [get_largest(vector_lsb,vector_msb):0] mac_address;

function integer get_largest(input integer first, second);

get_largest = (first > second)? first : second;
endfunction
endmodule
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