PREVIOUS QUESTION PAPERS AND IMPORTANT QUESTIONS UNIT-WISE

APR-MAY 15 UNIT-1 UNIT-2 UNIT-3 UNIT-4 UNIT-5

Nov/Dec 14 Apr/may 15 Unit I Unit II Unit III Unit IV Unit V
Part-A Part-A Part-A Part-A Part-A Part- A Part-A
1. Amdahl’s Law 1. 8 ideas 1. 8 ideas 1. ALU operations 1. measure CPU perform 1. strong/weak scaling 1. volatile / Non
2. Relative addressing [Link]/parallelism 2. pipelining 2. block diag: FA 2. basic perf eqn 2. UMA/ NUMA Volatile memory
3. Little Endian 3. overflow in Sub 3. Booth’s Mult 3. MIPS 3. Flynn’s classification 2. SRAM, DRAM
3. hardware comp
4. DMA 4. subword parallelism recoding Table 4. MIPS exec steps 4. Multithreading 3. locality of reference
5. Speculation 4. CPU, ALU?
5. R-Type instructions 5. Control Unit? 4. Merits-Booth’s algo 5. MIPS instrn formats 5. parallelism 4. /LOR types
6. Exception? [Link] Buffer [Link]/Throug 6. datapath 6. ILP 5. techniques-improve
7. Flynn’s classification [Link]- types
7. strong,weak scaling hPut 6. IEEE- single precision 7. PC 7. LLP Cache
8. Multithreading 8. UMA / NUMA 8. Hazard? 8. types of dependencies 6. CPU execution time
9. Programmed Interrupt 7. CPU Time 7. iEEE double precision
9. need-memory hierarchy 9. Types of hazard 9. data hazard types 7. VM
I/O 8. Power Wall 8. represent a floating pt
10. DMA-improve speed 10. exception? 10. IPC 8. TLB
10. Dirty Bit 9. Multiprocessor s/ms 9. subword parallelism 11. pipelining, stages 11. ways to implement 9. DMA
10. Instrn, instrn Set 10. overflow in sub 12. HMT 10. interrupts
11. instruction format? 11. overflow, underflow 12. Adv-Multithreading 11. Exception, types
12. logical instrns 12. big/ little endian 13. multicore processors 12. functions of IOP
13. Control operations 13. CLA- advantages 13. programmed I/O,
14. PC relativeaddressing DMA
15. Moore’s Law
16. Amdahl’s Law

Part-B Part-B Part-B Part-B

Part-B Part-B Part-B
11.a.i. AddressingMode 11.a. instructions 1. 8 ideas 1. Flynn’s classification
1. n-bit adder 1. Datapath, its control 1. memory
[Link] Time pblm 11.b. addressing modes 2. performance Eqn 2. HMT types
2. hazard, types technologies
[Link] Multipln 2. CLA
11.b.i. components 3. instruction format? 3. except handling in 3. ILP, enhance performance 2. cache policies
[Link] pt addition 3. sequential 4. Multicore processors
[Link]. performance eqn 4. logical instructions MIPS 3. cache mapping
13.a. Hazard types, Ex multiplication 5. types of dependences
12.a.i. booth bit pair 5. addressing modes 4. pipelined datapath technique
[Link] handling 4. booth’s recoding 6. types of data hazards
recoding 6. addressingmode-pblm 5. pipelined control 4. VM
[Link]. CLA [Link]’s classificatn 5. booth’s multiplication 7. parallel processing5. TLB
[Link] of compter
14.b. HMT,types 6. booth’s bit pair challenges
12.b. Restore/NonRestore 6. programmed I/O
Div 15.a. memory technolog
recoding 7. DMA
13.a. Data path & Control [Link], addr translatn
7. restoring/ NR division 8. DMA transfer modes
13.b. Hazard? Types 8. IEEE single, doubl 9. bus arbitration tech
14.a. ILP, challenges precision 10. interrupts
[Link] 11. IOP
[Link]. HMT
15.a.i. mapping functions
[Link]. bus arbitration
15.b.i. cache techniques
15.b.iiAny2 Std I/O i/face